Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Abstract: A technique for providing concurrent non-blocking access to a circular queue is provided. The concurrent non-blocking circular queue also may be configured such that cache-coherent requesters and a non-cache-coherent requester (e.g., software and hardware) both may concurrently access the queue. Further, the queue may be configured such that the probability of occurrence of the ABA race condition may be minimized.

Abstract: Several systems and methods are described for accessing one of multiple groups of peripheral devices. One of the systems includes a host system, multiple peripheral devices, and a host adapter. The peripheral devices are arranged to form multiple groups, each group including at least one peripheral device. The host system is coupled to the peripheral devices via the host adapter, and accesses the peripheral devices via the host adapter. The peripheral devices of each group receive a group access signal for controlling accesses from the host system. The host adapter includes a control register and signal routing logic. The signal routing logic is coupled to the control register and to each of the groups of peripheral devices. The control register stores a value for selecting one of the groups of peripheral devices. The host system may include a central processing unit (CPU) configured to write the value to the control register.

Abstract: Systems, devices, and methods. A double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

Abstract: A data transfer apparatus includes a reception unit for receiving data from the first external device; a storage unit for storing the data received by the reception unit; an output unit for receiving data and outputting the data to a second external device; a retransmission request receiving unit for receiving a retransmission request signal from the second external device; and a transfer control unit for having a first transfer performed when the receiving unit has received data from the first external device, the first transfer transferring the data using direct memory access (DMA) directly to both the output unit and the storage unit in parallel, and having a second transfer performed when retransmission request receiving unit has received the retransmission request signal, the second transfer transferring data, which has already been stored in the storage unit by the first transfer, to the output unit.

Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Abstract: The present invention provides a method for fibre channel control units to execute commands locally when a channel sends a repeat execute indicator in conjunction with certain other field settings, wherein the control unit will repeat and chain control words until certain predefined conditions occur.

Abstract: Extended low priority data is integrated into high priority I/O data in a scanned data transfer protocol using regular transmission fixed data blocks by allocating as little as a single word of the data block to the sequential transmission of this low priority data. Low priority data is buffered on both sides of this transmission to allow it to be transmitted over the course of many data block. As a result, the regular and predictable transfer of input and output data is not upset while allowing arbitrarily large low priority data to be sent at a relatively low data rate.

Abstract: The present invention discloses a method and apparatus for processing a packet of data received by a first-in-first-out (FIFO). In one embodiment, a message in the packet of data is recognized. Based on a plurality of control bits encoded in the message, a delimiting condition in the packet of data is determined. An operation is performed which is responsive to the delimiting condition. The operation controls the transfer of the packet of data from the FIFO to a memory.

Abstract: The present invention relates to a method of transmitting data stream including multi-path data stream sections to a connected digital television. This data stream transmitting method checks the number of maximum multiple paths of data streams recorded in a recording medium when a reproduction is requested, copies an uni-path stream section read from the recording medium so that the number of total same stream sections is equal to a target number which is determined based on the maximum number, assigns each stream section to a virtual channel to form multi-channel streams, and transmits the multi-channel streams to an outer device through a digital interface. Through this data stream transmitting method, it is possible to transmit an angle- or story-based stream segment a viewer wants to view among multi-path stream so that the stream of the selected angle or story may be presented seamlessly at the borders between neighboring stream sections by very simple algorithm.

Abstract: A method and apparatus assists communication between a writer of a shared file and the reader of the shared file without requiring the use of a shared file. When the writer fills a buffer with information and provides a write commend to write the buffer to a shared file, the buffer is not written to a file. Instead, the pointer to the buffer is passed to the reader, and the writer may be suspended until the reader indicates it has read the file. Alternately, two buffers may be used, with the contents of the buffer used by the writer copied to a second buffer, allowing the writer to reuse the first buffer before the reader has completed reading the contents of the second buffer.

Abstract: A method for more efficient buffer control of the configuration of hardware devices. In representative embodiments of the method described in the present patent document, (1) a given configuration is permitted to span exclusive access to the hardware by other processes and (2) different configurations may share the same data buffer. Current configuration of the hardware device is maintained by always placing the current configuration at the beginning of the data buffer. This first entry, comprising the current configuration, is the header of the buffer's data. All subsequent instructions will follow this header, as will any subsequent modifications to the devices' configuration. Since instructions contained in the buffer are to be executed sequentially, the device will always be set to the correct configuration, even when exclusive access between different data sets of the buffer is lost.

Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

Abstract: A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using &mgr;-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

Abstract: An electronic or information appliance, for example an LCD projector, air-conditioner or washing machine, which can use a data bus to read and write data at the same time. The electronic or information appliance comprises a data bus for transmitting data, an input device electrically connected with the data bus for providing data, an output device electrically connected with the data bus for receiving data, and a micro-controller electrically connected with the data bus for controlling the input device and output device. When the micro-controller reads a datum from the input device through the data bus, it writes the datum to the output device through the data bus at the same time to increase a data transmission speed between the input device and the output device.

Abstract: A circuit arrangement and method reduce the number of interconnects required for a digital signal processor by utilizing a shared bus to interconnect the digital signal processor to both a program memory and at least one external device. An instruction cache is utilized to cache selected instructions from a DSP program such that, whenever a cached copy of a DSP program instruction is available in the instruction cache, the cached copy can be fetched from the instruction cache instead of the program memory, thereby freeing the shared bus for performing an access to the external device. Caching of instructions and subsequent freeing of the shared bus for external device access may be conditioned on detection of a loop, whereby instructions from the loop are cached in the instruction cache and fetched during subsequent passes through the loop.

Abstract: A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

Abstract: An I/O expansion device for additional inputs and outputs, and an apparatus and a method for applying this device. The device includes a connector (CN1) for the connection with a parallel port, a plurality of 4-bit input/output ports, and an I/O expansion circuit (100) having a 4-bit data bus for data transfer between a plurality of 4-bit input/output ports and the connector. The I/O expansion circuit (100) includes a control input CTRL including a strobe PROG for controlling fetch of the command for selecting the input/output ports and an operation mode, a data input DIN that recieves a command in accordance with the state transition of the strobe PROG and data to be transferred to the input/output port selected by the command and a data output DOUT for giving the state of the selected port through the connector.

Abstract: A keyboard is programmatically adapted to enable an application in a run time environment to distinguish operator keys (ALT/CTRL), not otherwise recognizable on a standard keyboard and special keys not otherwise recognizable on a non-standard keyboard by the application, when actuated. In one embodiment, a native Dynamic Link Library (DLL) is created in memory to capture the keystroke stream and maintain state information about the keyboard. A Java Native Interface (JNI) is created in the DLL and provided to a Java application. At initialization time, the Java application loads the native DLL with extended program instructions relating to key recognition in its static constructor. The Java application receives notification when an ALT or CTRL key is actuated. At that time the Java application calls the native DLL to receive the extended program instruction to determine whether the right or left ALT or CTRL key was actuated.

Abstract: A stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the steps of: 1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device; 2) receiving a signal in the controller from the I/O device at any time during the sending step, to terminate the transmission burst; 3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent; 4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and, 5) repeating the above steps until the stream of data is received in its entirety by the I/O device.

Abstract: Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

Abstract: A digital bus arrangement and an associated method are disclosed. The bus arrangement includes an input synchronization layer and an output synchronization layer. Data transfer between the modules is synchronized using a master clock signal such that data originated by one module is latched and placed on the bus in one clock cycle. Thereafter, in a second or subsequent clock cycle, the data is synchronously latched at the other modules of the system such that the data is available to an intended module. No logic circuitry is present between the input and output synchronization layers.

Abstract: Signals are transmitted through a plurality of transmission channels, each including at least a pair of signal lines for transmitting an interface signal, between a transmitter and a receiver. A predetermined signal is modulated by a modulator with a high-frequency signal, and the modulated signal is provided to a signal line of one of the plurality of transmission channels. A demodulator receives the modulated signal transmitted via this signal line, and demodulates the modulated signal from the signal line based on the frequency of the high-frequency signal. According to the above-described configuration, an interface control method and apparatus which can newly exchange other data and control signals while conforming to existent interface specifications are provided.

Abstract: A method of transferring file of the present invention by the two simultaneous data transmissions comprises the steps of transmitting data in a forward direction starting from a first specified position to a bottom in the file, and transmitting data in a backward direction starting from a second specified position to a top in the file. And a method of transferring file in FTP of the present invention comprises the steps of establishing a control connection, establishing multiple data connection, dividing a file into segments from each arbitrary point in the file, transferring segments through each of the multiple data connections, respectively, and synthesizing file from the segments transferred through the multiple data connections.

Abstract: An arbitration protocol is provided for determining between a pair of subsystems within a networking system having a plurality of subsystems which subsystem might obtain access to a common hardware resource. The protocol allows the networking system to determine which subsystem becomes the sender and which becomes the receiver. The protocol is based on a point-to-point communication between two peer subsystems . It is based on an asymmetrical quality such that the first or priority subsystem has a zero latency in accessing the switch while the second subsystem must wait at least one clock cycle before obtaining access to the network system after requesting it and after the end of control by the first subsystem.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: Transactions are scheduled over a half duplex link between a first device and a second device. Information flowing over the half duplex link is divided into a plurality of service periods. According to one embodiment of the present invention, the transfer of a read request transaction, from the first device to the second device, is scheduled in one service period. The transfer of a write transaction, from the first device to the second device, is scheduled such that the write transaction will not be transferred across the half duplex link in the same service period as returning memory read data is transferred across the half duplex link. According to another embodiment of the present invention, a first transaction associated with a first agent is scheduled in a first service period according to a global schedule. The global schedule associates the first service period with the first agent.

Abstract: A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory and transmitted in a weakly ordered fashion over a bus to a graphics device. The graphics device reorders the incoming data into the same order as which the data was written into the contiguous region of system memory, thereby allowing the use of order dependent encoded commands with the weakly ordered bus interface.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A concurrent write duplexing device with extension of memory bus according to the present invention includes: a primary memory having a first memory in which changed information is stored and a first memory controller for controlling the first memory; a secondary memory having a second memory in which the operating system is loaded to change an operation mode from the standby module to the active module upon failure of duplexing separation and a second memory controller for controlling the second memory; a bus transceiver part for exchanging data with a CPU through a system bus and having a bus transceiver in the first memory controller and a bus transceiver in the second memory controller, to thereby determine as to whether the first and second memory controller operate; and a memory switch part for exchanging data between the active module and the standby module and having memory switches which set direction of memory bus in accordance with an operation mode of module, so that write operation performed in t

Abstract: A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between adjacent data blocks. The FIFO buffer has a read-pointer address register and a write-pointer address register and a bank of write-capture registers including at least a first pair and a second pair. The first pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a first data block written to the FIFO buffer register while the second pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a second data block written to the FIFO buffer. The first pair and second pair alternate in capturing and saving beginning and ending addresses of a plurality of data blocks written to the FIFO buffer.

Abstract: The present invention relates to an ATM-LAN(Asynchronous Transfer Mode-Local Area Network) switch, and in particular to an information transferring apparatus between processors of the ATM-LAN which is capable of efficiently performing an information transfer between a plurality of processors which perform an information transmission and receiving operation through a backplane based on the Ethernet protocol. The information transfer apparatus between processors of an ATM-LAN switch according to the present invention is capable of implementing an efficient information transfer between processors by providing a backplane sub-board for thereby checking an information transfer state between the processors without using a large number of devices for an Ethernet communication. In addition, it is possible to enable a stable information transfer between processors in the case of a hot swap and dual operation by providing a control logic to the backplane sub-board.

Abstract: A method and an apparatus for simulation of data in a computing system environment having a controlling program, a main memory, a plurality of hosts, at least one adapter and a queued-direct input/output device using a queued-direct input/output protocol. A pageable virtual machine is provided under control of a virtual-machine hypervisor in processing communication with one or more hosts. Simulation is then provided by strictly separating a set of protocol control blocks between those that contain main-memory addresses and those that do not. Copies of those control blocks that contain main-memory addresses is created and their addresses converted by the hypervisor from addresses used by the program in its virtual machine to real-memory addresses usable by the adapter.

Abstract: Repositioning within an input/output device is accomplished without any knowledge of where the input/output device is currently positioned. The input/output device is repositioned to a predetermined position, in order for a program to be retried. The predetermined position is determined from a previously executed program. The previously executed program is scanned looking for commands. For each command found, a position identifier is adjusted based upon the type of command. When the scan and adjustments are complete, the position identifier represents the predetermined position used for repositioning the input/output device.

Abstract: Repositioning within an input/output device is accomplished without any knowledge of where the input/output device is currently positioned. The input/output device is repositioned to a predetermined position, in order for a program to be retried. The predetermined position is determined from a previously executed program. The previously executed program is scanned looking for commands. For each command found, a position identifier is adjusted based upon the type of command. When the scan and adjustments are complete, the position identifier represents the predetermined position used for repositioning the input/output device.

Abstract: An improved interface is established between a field management system and a calibrator for calibrating a process device to provide increased efficiency. The interface includes a communication module for communicating with the calibrator in accordance with a calibrator-specific protocol and a translation module for translating calibration information between an FMS-compatible format and a common data format. The interface allowing calibration information to flow between the calibrator and the FMS.

Abstract: An interface architecture includes a plurality of pipelines each controlled by a respective line processor. An onboard ESCON protocol conversion device distinguishes customer data to be stored on a disk or read from disk versus header information. Transmit and receive frame dual port rams store transmitted frame and received frame information, stripping frame/header information from user data. Data to be stored in Global Memory is stored temporarily in FIFOs. An assembler/disassembler in each pipeline receives data from FIFOs (on a write), and transfers data to FIFOs (on a read). A buffer dual port ram (DPR) is configured to receive data for buffering read operations from and write operations to the GM. Data transfers between the assembler/disassembler and the buffer DPR pass through Error Detection And Correction circuitry (EDAC). A plurality of state machines arranged as an Upper Machine, Middle Machine and Lower Machine facilitate movement of user data between DPR and Global Memory (GM).

Abstract: The present invention provides a system in which adjoining modules are connected with a bus so that unidirectional data transfer through modules each having a CPU and a shared memory can be realized, and in this system controls are provided so that data from adjoining modules and data form a CPU or a shared memory in the module is simultaneously transferred by a switch in the module according to a destination for transfer.

Abstract: A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To permit parallel flow-through operation, each of the two buffers is organized into a number of fixed-sized pages that are accessible via the peripheral bus only one page at a time. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two pages in a data path simultaneously: one for receipt and another for transmission.

Abstract: For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a system for, and method of, writing back the results of the multiple-result instruction. In one embodiment, the system includes: (1) multi-result node creation circuitry that creates a multi-result node having at least first and second results for the multiple-result instruction and (2) node transmission circuitry, coupled to the multi-result node creation circuitry, that transmits the first and second results of said multi-result node sequentially over the result bus.

Abstract: A universal serial bus (USB) device or host provides a universal serial bus (USB) controller with a direct memory access (DMA) mode. In a DMA mode, a universal serial bus (USB) transmit endpoint may be programmed for a direct memory access (DMA) transmit channel, or a universal serial bus (USB) receive endpoint may be programmed for a direct memory access (DMA) receive channel. For a USB device, a DMA transmit channel performs data transfer to a universal serial bus (USB) host, and a DMA receive channel handles data transfer from the USB host. For a USB host, a DMA transmit channel performs data transfer to the USB device, and a DMA receive channel handles data transfer from the USB device. A universal serial bus transmit protocol and a universal serial bus receive protocol for the DMA mode of the USB controller permit a maximum packet size of universal serial bus (USB) data to be programmed to a value greater than the physical size of a USB transmit or receive buffer of a USB transmit or receive endpoint.

Abstract: In a data linking method of extracting data of a host data base on a computer into a portable remote terminal, an item definition data base which defines a record attribute, an object storage data base which stores object data on a record basis, a relation definition data base which defines relations among object data and a definition data base which defines relations among the respective data bases, and conducts synchronous processing of writing.

Abstract: Isochronous information is transferred between an IO device and a first buffer (N) of a plurality of buffers in a system memory. The isochronous information stored in the plurality of buffers is also stored in a memory cache accessible to a system processor. The state of the memory cache is managed according to an isochronous “X-T” contract that is independent of the “X-T” contact with which data are moved between the IO device and system memory. Further, data associated with a given buffer are moved into and out of the memory cache substantially simultaneously with the transfer of isochronous information between the IO device and other buffers in the system memory.

Abstract: When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.

Abstract: The present invention provides for an apparatus for transferring information in a network computing system environment. The apparatus comprises of a main storage and an information transfer interface mechanism in processing communication with the main storage. The interface mechanism is capable of coupling to a plurality of input/output devices. The apparatus also comprises of means for transferring a packet of data between the interface mechanism and the main storage and means for concurrently transferring and processing a plurality of other packets of data between the interface mechanism and said main storage.

Abstract: A host bridge having a dataflow controller is provided. In a preferred embodiment, the host bridge contains a read command path which has a mechanism for requesting and receiving data from an upstream device. The host bridge also contains a write command path that has means for receiving data from a downstream device and for transmitting the received data to an upstream device. A target controller is used to receive the read and write commands from the downstream device and to steer the read command toward the read command path and the write command toward the write command path. A bus controller is also used to request control of an upstream bus before transmitting the request for data of the read command and transmitting the data of the write command.

Abstract: An on-demand transfer (ODT) engine is located in each peripheral in a host/peripheral system communicating using a burst mode bus, e.g., a PCI bus. Each peripheral transfers blocks by setting, e.g., a starting address and block size of a data block to be transferred. Importantly, the starting location of a data transfer stream is maintained in a common memory area, e.g., in the host, while the length of the data transfer block is maintained in the ODT engine. By maintaining the length of the data block in the ODT engine, the peripheral can change the length of a block in a continual data stream on the fly, without the need to communicate with the host computer or common data transfer device such as a DMA. In the disclosed embodiment, up to 128 data streams may be simultaneously transferred.

Abstract: A system for compressing data and transferring the compressed data between a plurality of apparatus within a short period of time includes a dividing unit for dividing data into a plurality of divided strings of byte data, a compressing unit for concurrently compressing the strings of byte data which have been divided by the dividing unit, an expanding unit for concurrently expanding the compressed strings of byte data which have been transferred, a mixing unit for mixing the divided groups of byte data which have been compressed by the compressing unit, a distributing unit for distributing the groups of byte data which have been mixed by the mixing unit and transferred, and a combining unit for combining the groups of byte data which have been expanded by the expanding unit.

Abstract: Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.