Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Abstract: A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a transmit buffer is preferably provided for every other device on the bus with which it will communicate. One or more logic circuits, for example, a scheduler, is provided to coordinate exchange transactions between pairs of devices. Time delays are preferably provided between exchange transactions of different device pairs so as to prevent interference. Coherency checking is preferably implemented to avoid discrepancies introduced by information being held in a buffer pending an exchange transaction. Devices coupled to a common bus preferably maintain a transmit buffer for each other device on the bus with which they will be communicating.

Abstract: A distributed computer system and a method for replicating data in a distributed computer system. The system includes a plurality of processing nodes. A processing node comprises at least one processor and at least one local memory, where the local memory is in communication with each processing node. The system also includes maintenance software to determine whether data is read substantially more frequently than it is written and to replicate the data that is read substantially more frequently than it is written among the plurality of processing nodes. The method includes reviewing classes of data, identifying whether at least a portion of data of a certain class used by the processing nodes is read substantially more frequently than it is written and replicating copies of the data of that class in the local memories.

Abstract: A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ports, and an upstream data handler coupled to the upstream port. The data handlers are configured to implement a USB protocol. The upstream data handler is configured to provide data received via the upstream port to each of the downstream data handlers. Accordingly, the upstream data handler is shared between the various downstream data handlers.

Abstract: Direct memory access (DMA) controllers are used in digital processing of image data in image processing devices such as digital copiers, scanners, printers and fax machines. The DMA controllers are controlled for memory access by a predetermined resume signal that is sent from one DMA controller to another.

Abstract: A method and apparatus for the optimization of memory read operations via read launch optimizations in memory interconnect are disclosed. In one embodiment, a write request may be preempted by a read request.

Abstract: A method and a device for controlling data transmission between IDE apparatuses allow an IDE controller of an IDE control device to send read control signal to an IDE apparatus via a set of IDE interfaces and a signal control transmission line and then to send write control signal to another IDE apparatus via another set of IDE interfaces and another signal control transmission line. Thus, the output data from the IDE apparatus through the data transmission line can be accelerated the transmission speed thereof between IDE apparatuses so as to save the time for transmitting data.

Abstract: An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. For multiple channel transfers to hard disk drive storage, a multiplexed IDE host interface is provided with shared pins for data, address, and chip-select lines of the IDE interface so that multiple hard drives may be interfaced using the common pins of the integrated circuit.

Abstract: A system and method for managing a Fibre Channel adapter is disclosed. When a close request is received by the Fibre Channel adapter, the adapter is set to a quasi-open state. In a quasi-open state, the adapter keeps the link to the Fibre Channel network open, releases extended resources, and maintains minimal resources in order to keep the link open. When a request is received by the adapter while in a quasi-open state, the request is rejected thereby preventing other devices from logging into the quasi-opened device and informing other devices that the quasi-opened device is not currently communicating across the Fibre Channel network. An information handling system and a computer program product for implementing the Fibre Channel adapter quasi-open state are further disclosed.

Abstract: An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.

Abstract: Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.

Abstract: A data transfer technique between a source port and a destination port of a transfer controller with plural ports. In response to a data transfer request (401), the transfer controller queries the destination port to determine if it can receive data of a predetermined size (402). If the destination port is not capable of receiving data, the transfer controller waits until said destination port is capable of receiving data (412). If the destination port is capable of receiving data, the destination port allocates a write reservation station to the data (403). Then the transfer controller reads data of the predetermined size from the source port (404) and transfers this read data to the destination port (405). The destination port forwards this data to an attached application unit, which may be memory or a peripheral, and then disallocates the write reservation station freeing space for further data transfer (406).

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: A system and method for operating a distributed control network for irrigation management. The system incorporates several irrigation controllers wherein each of the controllers can transmit, receive and respond to commands initiated by any device or satellite controller on the network, a communication bus that is connected to the controllers, a central computer that is connected to the bus, several sensing devices that are connected to each controller, and several sprinkler valves that are connected to each controller. The controllers can be operated in local mode via a user interface and in a remote mode via a wireless connection. The controllers are capable of monitoring and acknowledging the commands that are transmitted on the bus.

Abstract: A computer system with a plurality of peripheral busses is adapted to permit multicast signals to be transmitted by a device on one peripheral bus to multiple devices on the other peripheral bus. In an exemplary embodiment, two PCI busses are provided, and master devices on either bus are capable of transmitting multicast signals to multiple targets on either bus. Targets of a multicast cycle are identified by a target identification signal on a first and a second multicast bus. A bus bridge relays the data for the multicast cycle between devices. In an exemplary embodiment, a sideband signal from the master to the bridge indicates a multicast signal has been transmitted on one of the PCI busses. In response, the bridge relays the multicast data to the second PCI bus, while also transmitting a sideband signal to devices on the second bus indicating multicast data is being transmitted on that bus. Targets identified on the second bus then capture the multicast data.

Abstract: An apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system. The apparatus includes a data buffer and a control unit. The data buffer includes a first plurality of storage locations each corresponding to one of a plurality of tag values. The data buffer may receive a plurality of data packets associated with the graphics transactions. The data buffer may also store the data packets in the storage locations according to tag values. The control unit includes a storage unit having a second plurality of locations. Each of the locations in the storage unit corresponds to one of the tag values and may provide an indication of whether a given data packet has been stored in the data buffer. The control unit may further determine an order in which the plurality of data packets is read from the data buffer.

Abstract: In one form, a computer system includes a system processor operable to process data. The system includes a number of memory array chips coupled to the system processor by a system bus. Such a memory array chip includes random access memory partitioned into rows, each row having a number of memory words. The random access memory has an internal buffer and the buffer is operable to hold a plurality of the memory words. Such a memory array chip includes an embedded processor and an internal bus coupling the embedded processor to the internal buffer. The internal bus is capable of concurrently transferring the plurality of memory words of the internal buffer for processing by the embedded processor.

Abstract: A display apparatus for displaying images based on signals received from a host. The apparatus includes a determining means for determining an interface type of the host, a plurality of storage means each storing specification information relating to display for one of interface types to be connected, and an output means for outputting, from one of the storage means to the host, the specification information corresponding to the interface type determined by the determining means.

Abstract: Data is moved between zones of a central processing complex via a data mover located within the central processing complex. The data mover moves the data without sending the data over a channel interface and without employing processor instructions to perform the move. Instead, the data mover employs fetch and store state machines and line buffers to move the data.

Abstract: A computer comprises a medium drive configured to reproduce data recorded in a video recording medium and an audio recording medium. When a reproduction switch is turned on if the computer is not powered, it is determined whether the video recording medium or the audio recording medium is loaded. If the video recording medium is loaded, the operating system is activated and the reproduction application is also activated.

Abstract: Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

Abstract: A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Abstract: A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.

Abstract: An apparatus for reordering packet transactions within a peripheral interface circuit. The apparatus includes a source tagging unit and a control unit. The source tagging unit may be configured to generate a plurality of tag values each corresponding to one of a plurality of packet commands. The control unit may include a first storage unit including a first plurality of locations and a second storage unit including a second plurality of locations. Each of the locations corresponds to one of the plurality of tag values. Each of the first plurality of locations may provide an indication of whether a given tag value corresponds to a first packet command in a given data stream. A first given location of the second plurality of locations corresponds to the tag value indicated by the first storage unit and stores a tag value of a second packet command in the given data stream.

Abstract: Disclosed is a method for one computing device (the “provider”) to provide peripheral services to another device (the “host”). A user directly runs the host. The host accesses the provider as if the provider were a set of peripheral devices attached to the host. In this way, the host and provider become, in effect, one device with the combined capabilities of both devices. The provider switches between two modes: In standalone mode, the provider acts as an individual device; upon switching to auxiliary mode, the provider provides peripheral services to the host but can still run applications and present an input/output interface to its own user. When the peripheral device provided to the host is a display screen, the host can map the provided screen into the host's own video memory, thus hiding implementation details from applications that use the screens. One device can simultaneously act as provider and host.

Abstract: A method and system are described for efficiently overriding a value of a net in an array during execution of a test routine. The logic simulator machine is simulating a logic design which includes the array and multiple nets. A current value of the net is set equal to an override value. A normal update to the array is permitted to occur during execution of a single cycle of the test routine. A determination is then made regarding whether the override value is still stored in the array for the particular net. If the override value is not still stored in the array for this net, normal updates to the array are prohibited during a single cycle of the test routine. During this cycle of the test routine, the override value is then again stored in the net as the current value of the net. This override value is thus made available to be read during this cycle of the test routine while writes to the array are disabled.

Abstract: Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

Abstract: A video game system includes a game program executing system executing a game program and one or more controllers supplying user inputs to the game program executing system. An interface between the controllers and the game program executing system is programmable to periodically poll the controller without involvement of the game program executing system.

Abstract: A communications controller may be programmed to store an identification code (identification data string) for a produce device in a non-volatile read/write memory, e.g., an electrically erasable programmable read only memory (EEPROM), FLASH memory, etc. The identification string may be generic or unique for the device and may be programmed before, during or after manufacture of the device. In addition, the identification string may be reprogrammed whenever a change is made to the device, e.g., after an upgrade.

Abstract: The present invention provides a method, a network device and a system for allowing for resuming a preceding incomplete synchronization session is provided, wherein the preceding incomplete synchronization session has been interrupted during its performing. In principle the resuming of the preceding incomplete synchronization session is based on the following operations according to the inventive concept. A communication connection for synchronization of data between a first and a second device is establishing. The first and the second device comprise each a predefined set of data records to be synchronized. A first and a second update identifier are communicated between the first and the second device. The first update identifier specifies a preceding complete synchronization session having been performed between them and the second update identifier specifies a preceding incomplete synchronization session having been performed between them.

Abstract: A controller is presented comprising one or more initiators coupled to one or more targets via a transaction bus and a corresponding number of data busses. The initiator(s) receive transaction requests from external logic, buffer the transaction and assign it a unique identifier, which is passed to an appropriate target via the transaction bus. The targets receive and queue the unique identifier until it can process the transaction, at which time it prompts the initiator to provide it the buffered transaction via a data bus dedicated to the target.

Abstract: A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

Abstract: A reconfigurable input/output controller (IOC) allows an adaptive computing engine (ACE) to communicate with external devices. The external devices can comprise a separate system on chip (SOC) or can be other devices or resources such as audio/visual output devices, memory, network or other communications, etc. The IOC allows different modes of transfer and performs necessary translation of input and output commands. In one embodiment, the IOC adheres to standard messaging and communication protocol used by other nodes in the ACE. This approach allows a uniform approach to the ACE design and provides advantages in scalability and adaptability of the ACE system. One feature of the invention provides a physical link adapter for accommodating different external communication types such as, RS231, optical, Firewire, universal synchronous bus (USB), etc.

Abstract: A method and system for flexibly and efficiently assigning channel path identifiers (CHPIDs) used by operating system software in computer systems to identify the communication path to I/O devices via channels. To avoid wasted CHPIDs, which may be limited in number, CHPIDs are assigned only to channels which are installed on and configured to the computer system. The CHPIDs may be re-assigned concurrently with ongoing system operations via a user interface and/or an imported, pre-defined CHPID mapping.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: A control facility that allows a non-programmer to use and manipulate replicated data without disrupting replication of the data itself. The control facility can be used and customized for a variety of software applications and storage platforms to perform off-host processing of the replicated data. In response to a single user command during replication of data from a primary node to a secondary node, a control message is obtained from the primary node and a control command associated with the control message is automatically executed on the secondary node. A portion of the data is diverted from first storage at the secondary node to second storage in response to obtaining the control message, the portion of the data is copied to the first storage in response to completing the execution of the control command, and the data is automatically re-directed to the first storage in response to completing the copying.

Abstract: The present invention provides an improved method and system for link detection and handling. The method includes detecting one of the plurality of link sectors; generating an interrupt signal; determining a buffer method selection; buffering the plurality of data sectors only, if a link skip buffer method is selected; and buffering the plurality of data sectors and the plurality of link sectors, except for a link block, and allocating a sector in a buffer for the link block, if a link buffer method is selected. The present invention provides a hardware approach to link sector detection and handling. Instead of passing the data to a system software prior to link sector detection, the method and system in accordance with the present invention performs the link sector detection in the controller hardware. When the controller detects the link sectors, it automatically either skips or buffers the link sectors depending upon the configuration of the controller.

Abstract: An architecture for data retrieval from a plurality of coupling queues. At least first and second data queues are provided for receiving data thereinto. The data is read from the at least first and second data queues with reading logic, the reading logic reading the data according to a predetermined queue selection algorithm. The data read from by reading logic and forwarded to an output queue.

Abstract: The invention is a method and system for print stream determination. The system's method begins with the initiation of a print stream processing application to which a print stream is directed. A print job is determined from a set of characteristics resident in the print stream. The print processing application will determine the optimal use of the system's peripheral devices for performing the job. The optimal use is determined by comparing each of the job's characteristics with each of the characteristics of the potential device driver. The comparison begins with determination of a value for each of the job characteristics wherein the value is representative of a desired result. A value for each of the device driver characteristics is determined wherein the value is representative of a potential result. Each of the desired results is compared to each corresponding potential result. If no corresponding potential result can be established, then an alternative peripheral device is sought.

Abstract: A buffer circuit for a peripheral interface circuit in an I/O node of a computer system. A buffer circuit includes a first buffer and a second buffer. The first buffer may be configured to store a plurality of selected packet commands within a plurality of storage locations. The second buffer is coupled to the first buffer and may be configured to store a plurality of index values. Each index value corresponds to one of the storage locations in the first buffer. The buffer circuit further includes a write logic circuit that is coupled between the first buffer and the second buffer. The write logic circuit may be configured to successively read each of the plurality of index values from the second buffer and to cause a selected packet command to be stored in each storage location corresponding to each of the plurality of index values within the first buffer.

Abstract: A buffer circuit for rotating outstanding transactions. A buffer circuit includes a buffer and a command update circuit. The buffer may be configured to store packet commands that belong to a respective virtual channel of a plurality of virtual channels. The packets may be stored in the buffer to await transmission upon a peripheral bus. Once a given packet is selected for transmission, a peripheral bus cycle corresponding to the given packet command may be generated upon the peripheral bus. The command update circuit may be configured to generate a modified packet command in response to receiving a partial completion indication associated with the peripheral bus cycle. The command update circuit may also be configured to cause the modified packet command to be stored within the buffer.

Abstract: A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.

Abstract: A method is described for storing and processing/filtering signals, as well as a memory arrangement, a signal processing arrangement and, in particular, a digital filter arrangement having a plurality of filter modules for digital processing/filtering of input values, having a memory area and a signal processing module, which contains in particular at least one multiplier-accumulator which has at least one multiplier and at least one adder. The input values, coefficients, and output values of the arrangement can be stored in the memory area and called up again therefrom as needed. The input values are gated with the coefficients to form output values. In order to alleviate the load on a higher-level microprocessor by digital processing/filtering of the input values, it is proposed that the digital filter arrangement have a Direct Memory Access controller for coordinating data transmission of the filter coefficients, input values and output values between the multiplier-accumulator and the memory area.

Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a first target device to a host system and in addition information that specifies whether the data is mirrored, and if so, identifies a second target device on which the data is to be read. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Abstract: An apparatus for connecting circuit modules is disclosed. The apparatus for connecting circuit modules that receives an input and an output signal at one circuit module and uses a transmitter/receiver to transmit data to and receive data from the second circuit module. Each transmitter/receiver is selectable between a bidirectional mode that transmits and simultaneously receives via two transmission lines, and a unidirectional mode that transmits on a first transmission line and receives from a second transmission line.

Abstract: A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

Abstract: A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction.

Abstract: Disclosed herein is a apparatus and method for packing a 16-bit number into an 8-bit result byte. The method and apparatus utilize a parallel processing right shift circuit and a filter to obtain desired results. The parallel processes are comprised of a plurality of multiplexers capable of discretely analyzing smaller groups of bits. In this manner, higher throughput may be obtained than previously known.

Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.

Abstract: Methods and systems for overlapping data flow within an extended copy command over a network, including, at a router in a network: receiving an extended copy command from a first host to a first target device; determining an initial network status if the network status is unknown; initializing a set of read-write parameters; and executing the extended copy command for a first segment of the extended copy command, and for one or more subsequent segments, by overlapping one or more read and one or more write commands of the extended copy command.