Abstract: A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two memory portions in a data path simultaneously: one for receipt and another for transmission. Specifically, each data path uses a memory portion to hold data that is currently being received, while using another memory portion containing data that was previously received for simultaneous transmission from the host adapter. Each of the data paths transfers data in a continuous manner irrespective of the context (e.g.

Abstract: A disk-array controller of the present invention has data-buffers 70-75 accessible from a host device and disk units, various selectors 42-69, XOR circuits 78-79, parity check circuits 76-77. By changing the settings of these components, transmission passes are changed. The settings can be programmed more than one by set registers 340-394 and execution counters 34-39. Using time-sharing buses such as PCI buses 15, 18, each program performs parallel processing because plural programs time-share the transmission bus during the period of acquiring access permission to the bus.

Abstract: The present invention provides for a computer program product for use with a computer system having a main storage device in processing communication with an information transfer interface mechanism capable of coupling to a plurality of input/output devices. The computer program device comprises of a data storage element included in the main storage device having a computer usable medium with computer readable program means for receiving and retrieving data and computer readable code means for concurrently receiving multiple packets of data from said interface mechanism. It also includes computer readable code means for concurrently storing multiple packets of data concurrently in said data storage element as well as computer readable code means for storage and retrieval of multiple packets of data concurrently between said interface mechanism and said data storage element.

Abstract: A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation—one which might affect the storage hierarchy as perceived by other devices within the system—is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the “sync” instruction supported by the PowerPC™ family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes.

Abstract: A computer system (100) comprises a processor (110), a memory (300), an interface (101) and peripheral devices (120-1, 120-2, 120-3). The interface has a pointer generator (160), a port (150), a decoder (170), and a parameter register (180). The port (150) transmits data words D(k) (380-k) from the memory (300) to the peripheral devices (120-1, 120-2, 120-3) or vice versa. Communication parameters are stored as parameter sets {P.sub.m } in parameter fields (185-m) of the parameter register (180). The decoder (170) selects a parameter set {P.sub.i } using from control words C(k) stored in the memory (300). Data queues can simultaneously be transmitted to two or more peripheral devices (120-1, 120-2, 120-3).

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.

Abstract: A method of bootstrapping executable code to a microprocessor controller from a personal computer (PC) via a bidirectional interface, e.g., a standard PC parallel port comprised of an external 25-pin D-shell connector. By bootstrapping its code from the PC, the microprocessor controller, which controls an adapter, e.g., a modem adapter, coupled to the PC is able to retrieve the most current version of the code stored in the PC.

Abstract: The present invention provides an improved disc drive. In one embodiment of the present invention a disc drive capable of spinning a disc, which contains more than one type of data is disclosed. A first type of data is associated with a first speed, and a second type of data is associated with a second speed that is faster than the first speed. The disc drive includes a drive mechanism, which may spin the compact disc at the first and second speeds and retrieve data from the compact disc at either speed. The disc drive also includes an elastic buffer, which is in communication with the drive mechanism. The buffer receives data from the drive mechanism at a variable input data rate and outputs data at a variable output data rate. Whereby when the drive mechanism spins the compact disc at the second speed the buffer may receive the first type of data without causing the drive mechanism to slow down to the first speed, and the buffer may output the first type of data at the variable output data rate.

Abstract: A method of and an apparatus for duplicating direct access storage devices (DASDs) such as hard disk drives (HDDs). The apparatus includes a portable HDD duplicator which can be connected to an existing personal computer (PC), and perform fast data duplication directly from a source HDD to a multiplicity of target HDDs simultaneously. The method includes the steps of providing direct data paths between the source HDD and the target HDDs and performing high speed data duplication and comparison functions by reading the source HDD and writing to the target HDDs at the same time.

Abstract: A method for accessing a shared resource is provided. An assigned usage rate is received from a resource coordinator and a desired usage rate is determined. When it is determined that the desired usage rate is higher than the assigned usage rate, a shared resource may be accessed at an enhanced usage rate if a usage reserve has been accumulated. When a shared resource is accessed at an enhanced usage rate, the usage reserve is decremented by an amount based on a difference between the enhanced usage rate and the assigned rate. When there is no usage reserve accumulated, access to the shared resource is limited to the assigned usage rate. When the desired usage rate is not higher than the assigned usage rate, a shared resource is accessed at the desired usage rate. When the desired usage rate is less then the assigned usage rate, the usage reserve is accumulated up to a reserve maximum. The reserve maximum may be based on configuration data.

Abstract: Disclosed are a switching system and method for a Small Computer System Interface (SCSI). The SCSI has a plurality of ports coupled to devices having differing priorities including a highest priority (initiator) and lower priorities (targets). The present invention interconnects a plurality of the highest priority initiator devices to the lower priority target devices. A plurality of analog switches are each coupled to one of the initiator device ports and to the lower priority target device ports, preferably on a singular target bus, for selectively interconnecting the coupled initiator device to the lower priority target device ports. A controller is coupled to the initiator devices and to the plurality of analog switches, and is responsive to requests for connection from the initiator devices for arbitrating amongst the initiator devices to operate the analog switches to interconnect only one of the initiator device ports to the lower priority target device ports.

Abstract: An architecture for the isochronous transfer of information within a computer system in which a first isochronous stream of information is transferred, and asynchronous information is transferred independently from the transfer of the first stream. A translation is performed between the first stream and a second isochronous stream of information, and the second stream transfers information at a rate substantially the same as the rate at which the first stream transfers information. The second stream and the asynchronous information are concurrently transferred. In another embodiment of the present invention, a first isochronous stream of information is transferred, and the first stream is divided into a plurality of first service periods. Each first service period has a first duration and contains a first amount of information. A second isochronous stream of information is transferred independently from the transfer of the first stream.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A network interface device minimizes access latency in initiating a DMA transfer request by selectively supplying a long bit comparison result, generated in a write controller configured for writing data into a buffer memory, directly to a read controller based on a determination that the buffer memory stores less than one complete frame. The media access controller determines the length of the data frame, and supplies the determined length to the write controller. The write controller compares the determined length to a prescribed threshold, and outputs a long bit value for storage in a buffer memory location contiguous with the stored data frame. The long bit can then be used to select a receive buffer threshold optimized for larger frames.

Abstract: System and method reading data from storage by speculatively accessing storage and overlapping data bus access with status determination, thereby reducing storage read access latency. Also, a system and method is provided for reducing storage read access latency by accessing a data bus substantially simultaneously with availability of data from storage. Upon receipt of a storage read request, and before status determination, the requested data is read from storage. Optionally, depending upon bus architecture or the need to minimize control circuitry, control of the data bus may speculatively be sought so that data may be loaded to the data bus upon availability from main storage, still whether or not status has been resolved. Subsequently, if status cancels the read request, further data bus loading is terminated.

Abstract: The present invention provides a system in which adjoining modules are connected with a bus so that unidirectional data transfer through modules each having a CPU and a shared memory can be realized, and in this system controls are provided so that data from adjoining modules and data form a CPU or a shared memory in the module is simultaneously transferred by a switch in the module according to a destination for transfer.

Abstract: A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer.

Abstract: To reduce access frequency to a CPU for recording/reproducing digital audio data, a control system of FIFO memories of the invention applied to an sound codec apparatus comprises means (2, 4, 7, 9 and 10) for controlling a first and a second FIFO memory (3 and 8) to store recording data sequentially and to output stored recording data sequentially when the apparatus is used exclusively for recording; and controlling the first and the second FIFO memory to store the reproducing data sequentially and to output the stored reproducing data sequentially when the apparatus is used exclusively for reproducing.

Abstract: Methods and associated apparatus for performing concurrent I/O operations on a common shared subset of disk drives (LUNs) by a plurality of RAID controllers. The methods of the present invention are operable in all of a plurality of RAID controllers to coordinate concurrent access to a shared set of disk drives. In addition to providing redundancy features, the plurality of RAID controllers operable in accordance with the methods of the present invention enhance the performance of a RAID subsystem by better utilizing available processing power among the plurality of RAID controllers. Under the methods of the present invention, each of a plurality of RAID controllers may actively process different I/O requests on a common shared subset of disk drives. One of the plurality of controllers is designated as primary with respect to a particular shared subset of disk drives.

Abstract: A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To permit parallel flow-through operation, each of the two buffers is organized into a number of fixed-sized pages that are accessible via the peripheral bus only one page at a time. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two pages in a data path simultaneously: one for receipt and another for transmission.

Abstract: A system for serializing and synchronizing data stored in a tape drive emulation system utilizes a physical lock system and control data MUTEXes to assure serialization.

Abstract: An improved transceiver pair that are tightly integrated into a computer system. The transceiver pair include a base transceiver and a remote transceiver, with a high speed serial connection between them. The base transceiver has a base transmitter with a parallel input port for accepting parallel, encoded data and a serial output port for transmitting a serial, encoded data stream. The remote transceiver has a receiver with a serial input port for receiving the serial, encoded data stream and an audio/video output port for passing deserialized data to an audio and video control unit after decoding. The high speed serial connection links the base serial output port to the remote serial input port. The remote receiver further includes a feedback input port adapted for receiving feedback data forwarded from a sensor. The sensor may respond to palpable, optical or sonic input or to physical contact.

Abstract: A memory system includes a data memory and a distinct cache status memory for storing status information regarding the data memory. A memory controller generates timing and control signals for accessing the data memory in a page mode while concurrently accessing the cache status memory in a word mode. In the preferred embodiment, the data memory is accessed in a four word per page mode while a read-modify-write operation is performed on an associated cache status memory. In order to conserve pins on the memory controller, the cache status memory shares a substantial portion of the address lines which are received by the data memory. Supplemental cache status address lines are generated by programmable control logic, which may be incorporated into the memory controller. Programmable control logic generates supplemental address lines based on the maximum number of data memory modules, the size of an addressed data memory module and the number of cache status columns.

Abstract: A solution to the problem of undesired serialization of bus controlled instrument measurement delays for multiple instances of programmatically controlled measurement processes is to configure the bus operations and the control programs to allow the issuance of a command within the context of a first collection of such instruments, without having to wait for the corresponding data before issuing commands within the context of a second collection. This is done by instructing the equipment in the collection to signal that they have data instead of the more customary immediately issued "@ address talk", which is then followed by the delay needed by the equipment to make the measurement. Instead, the "have data" signals are associated with the devices that originated them and then the bus instructions that request the data are issued. In conjunction with this, the usual bus I/O commands in the controlling programs may be replaced with calls to a library that operates in just this fashion.

Abstract: A data input-output device includes a single memory, an input interface unit for storing data in the memory, an operation unit for fetching the data from the memory, for performing operations on the data, and for updating the data in the memory when necessary, an output interface unit for transmitting the data in the memory that has been operated on by the operation unit to outside of the device, and a bus control unit for setting a priority for each of these units and for controlling memory access by these units according to the priorities every time a predetermined number of bytes of data is transferred.

Abstract: A multi-path access control device for an integrated system is presented which allows simultaneous access to multiple external devices coupled thereto by multiple functional units. The multiple functional units are coupled to the shared access control device across two or more high speed, shared data buses. The control device includes multiple bus ports, each coupled to a different data bus, and a non-blocking crossbar switch coupled to the bus ports for controlling forwarding, with zero cycle latency, of requests from the functional units. Multiple external device ports are coupled to the non-blocking crossbar switch for receiving requests forwarded by the crossbar switch, and each external device is coupled to a different external device port. The crossbar switch allows multiple requests at the bus ports directed to different external devices to be forwarded to different external device ports for simultaneous accessing of different external devices coupled thereto pursuant to the multiple requests.

Abstract: A computer system includes a first device on the first data bus, a second device on the second data bus, and a bridge device that delivers requests for data from the first device to the second device and returns the requested data to the first device. The bridge device includes a first data storage buffer that stores data requested by the first device during the first request, and a second data buffer that simultaneously stores data requested by the first device during a second request.

Abstract: In a microcontroller, a synchronous serial port is coupled to a DMA unit such that a series of DMA writes to the synchronous serial port can be followed by a series of DMA reads from the synchronous serial port, all without intervention or the execution of the microcontroller.

Abstract: The invention relates to a method and an arrangement for operating a bus system having at least one master unit and at least one slave unit, having a bus and a bus control unit for the bus arbitration and for controlling the data transfer. The data transmission is split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus is cleared for the data transmissions of other master units in a first data transmission configuration, or the bus is blocked between the request data transfer and the response data transfer, in a second data transmission configuration and slave units. In the case of a response transfer, the master and slave are changed round.

Abstract: Processing streaming data on demand in a computer system. A service cycle is divided into a first plurality of input/output (I/O) phases for a second plurality of streams of real-time data. For each of the first plurality of I/O phases, a disk job, if any, is scheduled for one of the second plurality of streams of real-time data, and a second plurality of network jobs, each of the disk jobs corresponding with each of the second plurality of streams of real-time data.

Abstract: A method and apparatus that takes advantage of the connectivity of a unit to speed up communication of needed files to the unit. The method uses each port as a channel to input or pump a portion of the file. If a unit has N equally fast ports, it could possibly pump a file in N portions and take 1/N amount of pumping time. This saves the time of craft personnel performing the load without any degradation of the file. Once all portions are received, the unit has sufficient processing capability to rejoin the portions back into the needed file. The method also allows for the possibility that a port or channel will not be operating properly and automatically sends the portions through the remaining available channel(s) and port(s).

Abstract: A method for controlling the transmission of information between electronic components in a motor vehicle, which components can be either data sources or data sinks, in which a cascade design is used to facilitate the transmission of information. By separating the control signal from the actual streams of data, a flexible, chain type of structure is obtained.

Abstract: A communication system is provided that includes a mechanism for selectively addressing memory banks depending upon the configuration of that system. The communication system can therefore operate in accordance with two possible modes of operation. According to a first mode, the local CPU can access one set of memory banks concurrent with an external device accessing the other set of memory banks. According to a second mode of operation, either the local CPU can access the memory banks or an external device can access the memory banks, one exclusive of the other. In one version of the second mode of operation, address signals to the memory banks can be physically connected leaving signals free to be used as general purpose input/output signals. The mechanism by which memory banks can be addressed and data transferred to and from those banks readily lends itself to communication applications to which the present system may be attributed.

Abstract: An improved system and method for the transference of data with minimal delay and loss is disclosed. Primarily useful in maintaining the flow of an isochronous data stream, the present invention minimizes delay through the use of a shared buffer for both the data source and destination and without reliance upon an interrupt to transfer data. The present invention minimizes data loss through the use of a double buffer, the size of which is adjusted to accommodate interrupt latency without increasing transference delay.

Abstract: Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system are described herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system. These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system. In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses which make up the bus arrangement. Systems described may include any number of individual buses within their bus arrangements.

Abstract: An information recording and reproducing apparatus according to the present invention includes a read-ahead history buffer which is used as a ring buffer. A read-ahead operation is performed, every time a reproduction request is made by a host device, so as to maintain the read-ahead data after the last block for which reproduction has been requested at a predetermined value. Data which has already been requested by the host device and has not been overwritten by the read-ahead operation is treated as history data. As a result, data centered around (i.e., preceding and following) the last block for which the host device has requested reproduction is always secured as cache data.

Abstract: A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

Abstract: A method for queuing hardware control blocks, such as SCBs, for a system including a system processor coupled to a plurality of host adapter devices and a buffer memory controller device by an I/O bus is based on use of an endless new hardware command block queue, and an endless done hardware command block queue. The hardware command blocks for a plurality of devices, where each device includes a device processor, are managed by forming an endless queue for a device in a memory external to the device. A first pointer to the endless queue is maintained in a memory that is not within the memory space of the device processor. A second pointer to the endless queue is maintained in a memory addressable by the device processor. The first and second pointers address the head and tail hardware command block array sites of the endless queue.

Abstract: Disclosed is an exclusive control method in an I/O subsystem having an exclusive controller which is provided with an exclusive control table and which permits a host interface to use the I/O device when the I/O device is not used by any other host interface while prohibiting the use when another host interface is using the I/O device.

Abstract: A computer system automatically senses characteristics of diverse peripheral devices connected to a common communications port, and automatically maximizes the communications speed with the devices. Coupled in daisy chain fashion to the communications port, all peripheral devices receive every signal issued from the controller port, each device responding only to signals addressed to that device or signals addressed to a universal address. The controller first receives an identifier from peripheral devices attached to the controller port. The controller then interprets the received identifiers to determine a maximum communications speed for each device. Next, the controller and the attached peripheral devices are configured to communicate at the maximum communications speed of the slowest device. This guarantees that all messages sent by the controller are compatible with all peripheral devices.