Abstract: A video signal transmitting device having analog and digital video signal output functionality is adapted to transmit a video signal, and has a cable unit, a digital visual interface integrated input port disposed at one end of the cable unit and adapted to receive the video signal, and a digital visual interface output port and an analog video signal output port disposed at the other end of the cable unit. The digital visual interface integrated input port has a first pin set for digital video signals, and a second pin set for analog video signals. The digital visual interface output port is connected to the first pin set through the cable unit, and the analog video signal output port is connected to the second pin set through the cable unit so as to achieve an effect of respectively outputting digital video signals and analog video signals.

Abstract: A USB host system includes a USB host controller including a transfer memory for USB data transfer. In the transfer memory, a plurality of transfer descriptor regions are allocated. Transfer descriptor setting means sets, for the USB host controller, a transfer descriptor for executing USB transfer. The transfer descriptor setting means can set, for one end point of a USB device, a plurality of transfer descriptors using the plurality of transfer descriptor regions, respectively.

Abstract: In accordance with certain aspects of the automatic protocol determination for portable devices supporting multiple protocols, a portable device detects which one of the multiple protocols is being used by the host device for subsequent communication with the portable device. This detection is based on the content of a command received from a host device. The detected protocol is then used by the portable device for subsequent communication with the host device. The host device may also send, to the portable device, a notification of which of the multiple protocols is being used by the host device.

Abstract: A video signal transmitting device having analog and digital video signal output functionality is adapted to transmit a video signal, and has a cable unit, a digital visual interface integrated input port disposed at one end of the cable unit and adapted to receive the video signal, and a digital visual interface output port and an analog video signal output port disposed at the other end of the cable unit. The digital visual interface integrated input port has a first pin set for digital video signals, and a second pin set for analog video signals. The digital visual interface output port is connected to the first pin set through the cable unit, and the analog video signal output port is connected to the second pin set through the cable unit so as to achieve an effect of respectively outputting digital video signals and analog video signals.

Abstract: The invention provides a task scheduling method which can prevent overflowing of a buffer on a host system or a data encoding/decoding apparatus even when the transfer rate falls in case the compressed data and the non-compressed data are simultaneously transferred between the host system and the data encoding/decoding apparatus. In a task scheduling method, the compressed audio/video data is transferred from the buffer of the host system to an external device with a first transfer priority. The non-compressed audio/video data is transferred from the buffer to the external device with a second transfer priority lower than the first transfer priority.

Abstract: A method, system, and storage medium for the InfiniBand™ Poll verb to support a multi-threaded environment without the use of kernel services to provide serialization for mainline Poll logic. Poll is the verb, which allows a consumer to determine which of its work requests have completed, and provides ending status. In addition to multiple concurrent threads using Poll against a single Completion Queue, Poll is serialized with Destroy Queue Pair and Destroy Completion Queue. Completion Queues are used to maintain completion status for work requests. Queue Pairs are used to submit work requests and are related to a Completion Queue at the time they are created.

Abstract: A processing apparatus which stores a first information piece about attributes identifying a specific process generating data input/output requests in such a manner that the first information piece is associated with a second information piece identifying at least one of the physical paths as at least one first physical path, and which, when transmitting first data input/output requests generated by the process identified by the first information piece to the storage apparatus, transmits the first data input/output requests to the storage apparatus via the first physical path identified by the second information piece associated with the first information piece and, when transmitting second data input/output requests generated by a process not identified by the first information piece to the storage apparatus, transmits the second data input/output requests to the storage apparatus via at least one second physical path different from the first physical path of the plurality of physical paths.

Abstract: A data processor capable of preventing the occurrence of overrun, while efficiently performing DMA transfer. An SIO of a data processor starts the transmission of transmission data only when transmission data is stored in a transmission buffer and a reception buffer has no space available for data storage.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: A data transfer control device including: a node to which is input data to be transferred through serial transfer paths; a LINK circuit which splits the input data into first to pth channels in predetermined units in sequence, and outputs the thus-split data and a split transfer notification for each channel; first to pth parallel/serial conversion circuits which convert the split data and the split transfer notification that are output for each channel into a serial signal; and first to pth transceivers which output the serial signal which has been input from the first to pth parallel/serial conversion circuits to the serial transfer paths for the first to pth channels.

Abstract: The present invention relates to a system and methodology to mitigate memory current requirements in an industrial controller and to facilitate efficient on-line editing, storage and retrieval of user programs and data. A segmented memory architecture is provided, wherein a first memory segment is loaded with programmed instructions and other data that is relatively static in nature. A second memory segment is provided for storage of dynamic information such as controller data table variables that change frequently and/or rapidly during program execution of the controller. An execution memory is concurrently loaded with the user program to facilitate high performance program execution and to enable on-line edits of the user program during operation of the controller.

Abstract: A communication system performs bidirectional communication through a same communication path every communication cycle period between a master station and a slave station. From the start of the communication cycle period until an interval period shorter than the communication cycle period elapses, the master station transmits master data represented at a first ratio of first pulse width to the communication cycle period to the slave station. In a remaining period after the interval period in the communication cycle period, the slave station transmits slave data represented at a second ratio of second pulse width to the interval period to the master station.

Abstract: A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ports, and an upstream data handler coupled to the upstream port. The data handlers are configured to implement a USB protocol. The upstream data handler is configured to provide data received via the upstream port to each of the downstream data handlers. Accordingly, the upstream data handler is shared between the various downstream data handlers.

Abstract: A lightweight messaging method and apparatus that includes creating a temporary receive data area, and if a receive operation is seen first, then creating an operational receive data area, and waiting for a corresponding send operation to fill the operational receive data area with sent data; and if the send operation is seen first, then filling the temporary receive data area with sent data, when the corresponding receive operation is seen, creating the operational receive data area, and moving the sent data from the temporary receive data area to the operational receive data area.

Abstract: A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.

Abstract: A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: A method and computer system for implementing, in a multithreaded environment, an almost non-blocking linked list allow a lock-free access provided that certain conditions are met. The approach involves: associating a pointer and an auxiliary data structure with each linked list, using a compare-and-swap (CAS) operation, and making a slight modification of values associated with nodes under certain conditions. The CAS operation guards against setting the pointers incorrectly during insertion and removal operations. The auxiliary data structure, also referred to as the ‘black list,’ holds a dynamic list of values, typically pointer values, associated with nodes that are in the process of being removed by a thread.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

Abstract: A method is provided for optimizing a SyncML slow sync between a proprietary client and server. When a slow sync is detected, the client and server can depart from the normal SyncML protocol and process summary data without having to compare all items on a field-by-field basis.

Abstract: A system and method of operation are provided for using a network interface to process incoming messages sent by a client device to a network server. The network interface includes a First-In-First-Out (FIFO) buffer for assembling the incoming messages from a serial to a parallel form and a regular-expression pattern matching circuit connected to the FIFO buffer. The regular-expression pattern matching circuit is adapted to, concurrent with the assembly of the incoming messages from a serial to a parallel form, perform HTTP message header recognition and parsing, and provide to the server parsed HTTP message headers in a compact form. The regular-expression pattern matching circuit generates client response messages automatically based on a content of the parsed HTTP message headers. The system performance and quality of service of the network server is improved.

Abstract: The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.

Abstract: An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. For multiple channel transfers to hard disk drive storage, a multiplexed IDE host interface is provided with shared pins for data, address, and chip-select lines of the IDE interface so that multiple hard drives may be interfaced using the common pins of the integrated circuit.

Abstract: A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices.

Abstract: A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the data storage means in correspondence with a command contained in data (a frame) sent from the host processing device through the channel, and a channel processor, among the plurality of channel processors, is assigned for executing the data-input-and-output process for the data (frame) according to a type of command contained in the data (frame). Thus, the storage control device of the present invention can use the full-duplex channel efficiently.

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: It is an object of this invention to expand an SBP-3 protocol such that two data buffers can be independently controlled. To achieve this object, a target sends responses to status blocks corresponding to two commands included in one ORB in the SBP-3, and an initiator receives these responses to the commands independently of each other. The number of times of execution and time interval are designated for each command. The target repeats a command the designated number of times at the designated time interval.

Abstract: A clustered storage array consists of several nodes coupled to one or more storage systems. The nodes provide a LUN-device for access by a client, the LUN-device mapping to a source logical unit corresponding to areas of storage on the one or more storage systems. A target logical unit corresponds to different areas of storage on the one or more storage systems. The source logical unit is migrated in parallel by the several nodes to the target logical unit.

Abstract: Apparatus, methods and systems for controlling data flow between data processing systems. In an example embodiment, the apparatus includes descriptor logic for generating a plurality of descriptors including a frame descriptor defining a data packet to be communicated between a location in the memory and a data processing system, and a pointer descriptor identifying the location in the memory. The apparatus also includes a descriptor table for storing descriptors generated by the descriptor logic for access by the data processing systems.

Abstract: The invention relates to a method for processing consistent data sets by asynchronous application of a subscriber in an isochronous, cyclical communication system. According to the invention, by connecting a communication memory and a consistency, transmission and reception buffer, copying processes leading ti delay can be kept to a minimum.

Abstract: A method for utilizing concurrent context switching to support isochronous processes preferably comprises a main context that is configured to support system execution tasks, a first concurrent context that supports a first set of concurrent execution and loading procedures, and a second concurrent context that supports a second set of concurrent execution and loading procedures. A context control module preferably manages switching and loading procedures between the main context, the first concurrent context, and the second concurrent context. The context control module may perform successive concurrent context switching procedures by alternating between the first concurrent context and the second concurrent context to thereby sequentially support any desired number of isochronous processes.

Abstract: Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route a data strobe signal to a first number of the plurality of data channels for reading the data from the memory when the at least one multiplexer is in a first selected state, and wherein the at least one multiplexer is configured to route the data strobe signal to a second number of the plurality of data channels, wherein the second number is greater than the first number, for reading the data from the memory when the at least one multiplexer is in a second selected state. Such methods and systems may also comprise a clock for generating a data strobe signal, and a flip-flop for latching the data from the memory into the control circuit with the data strobe signal, wherein the data strobe signal does not leave the control circuit.

Abstract: Label contention in a label switched network is resolved by applying a contention resolution scheme that reconciles policies for handling unidirectional and bidirectional label switched path setup.

Abstract: A data transfer device is disclosed for writing data to and reading data from a disk drive system through a plurality of ports of the data transfer device. The data transfer device includes a first buffer for serially receiving, from a host system, control portions of data read requests and data write transfers; a second buffer for serially receiving, from the host system, data portions of data write transfers received by the first buffer; and N temporary storage devices, wherein N is a positive integer, coupled to the first buffer and the second buffer, the N temporary storage devices for parallelly receiving and temporarily storing consecutive control portions of the data read transfers and data write transfers from the first buffer. Up to N of the data read transfers and data write transfers are transferred to the disk drive system through the plurality of ports simultaneously.

Abstract: A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.

Abstract: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

Abstract: There are provided, on the POS device unit side, a physical keyboard having a plurality of physical keys arranged thereon; a screen keyboard comprising a plurality of screen keys arranged and displayed on a screen having a touch panel arranged thereon adjacent the physical keyboard; and a key data transfer control unit which connects each of the physical keyboard and the screen keyboard to an input port, and transfers key data from an output port in accordance with the sequence of key operations of the physical keyboard and the screen keyboard. A keyboard control unit which notifies the key data transferred from the key data transfer control unit to the application processing unit for execution of processing is provided in the POS main body. When physical keys and screen keys are operated in succession, the key data are transferred in the sequence of key operations and notified to the application.

Abstract: A memory system is provided which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: Method and apparatus for playing analog audio in an electronic audio system having multiple audio codecs, only one of which has a direct hardware connection to the analog audio source. First analog audio data is received from the analog audio source at a first audio codec, and converted to digital audio data using the first audio codec. The digital audio data is stored in a memory, and read back from the memory, transferred to a second audio codec. The digital audio data is then converted to second analog audio data using the second audio codec, and output from the second audio codec. An audio controller may be used to store the digital audio data in a loopback buffer within the memory, read the digital audio data from the loopback buffer, and may further be programmed to operate in a prepare loopback state, a loopback running state, and a recording state.

Abstract: A parallel processing system includes a plurality of stages operatively coupled in parallel and operating simultaneously. Each stage including a process unit generating a predetermined function and a buffer coupled via a slow output and a slow input ports to the process unit. The buffer also includes a fast input port and a fast output port. A controller drives the buffer to operate in a Slow Read Phase when data is written from the buffer into the process unit, a Slow Write Phase when data is written into the buffer from the process unit, a Fast Write Phase when data is written at a fast rate into the buffer and a Fast Read Phase when data is read from the buffer.

Abstract: A channel based network is provided that allows one or more hosts to communicate with one or more remote fabric attached I/O units. A split-model network driver includes a host module driver and I/O unit module driver. The host module driver and the I/O unit module driver each includes a messaging layer that allows the hosts and I/O units to communicate over the switched fabric using a push-push messaging protocol. For a host to send data, the host either initiates a RDMA write to a pre-registered buffer or initiates a message Send to a pre-posted buffer on the target. For the RDMA case, the initiator would have to send the target some form of transfer indication specifying where the data has been written. This notification can be done with either a separate message or more preferably with immediate data that is included with the RDMA write.

Abstract: The present invention discloses a method, system and article of manufacture for performing analytic modeling on a computer system by handling a plurality of predefined system criteria directed to a modeled computer system. The present invention provides means for the user of an analytic model to specify (i.e. enable) any number of predefined system criteria that must all be simultaneously satisfied. The modeling methodology uses a variation of the well-known Mean Value Analysis technique in its calculations. Response times, resource utilizations, and resource queue lengths are initially estimated for a small user arrival rate. An iterative method is used to gradually increase the user arrival rate by a constant value. For each iteration, response times, resource utilizations, and resource queue lengths are calculated. Then for all the criteria, which have been enabled, it is checked to see if the value limits specified for those criteria have exceeded.

Abstract: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

Abstract: A protocol enabling the exchange of information between data switching node components and a supervisory management processor is provided. The protocol defines a data frame format, data fields, data field values of a group of command frames. The exchange of information therebetween via the defined frames enables the production of data switching equipment having a generic implementation with a deployable, upgradeable and expandable feature set providing and enhancing support for current and future services.

Abstract: A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal paths away from the DRAM to the other device for the duration of the refresh the shared signal paths include at least some of the address and data signal paths.

Abstract: The present invention provides a method and a control apparatus (1) for assigning ID numbers to a number of IDE devices (31–38) included in one network server. The control apparatus includes a host electronic circuitry (10), a plurality of controllers (21–24) electrically connecting to the host electronic circuitry, the plurality of IDE devices (31–38), a plurality of power switches (41–48) and a plurality of display devices (61–68). The host includes a plurality of sets of ID indication pins and an ID set pin, and each controller electrically connects with and controls a pair of IDE devices. Prior to boot up, the user sets jumpers in the host to assign unique values to the sets of ID indication pins. The controllers read the values and then assign unique ID numbers to the IDE devices. The IDE devices spin up in a sequence determined by their assigned ID numbers.

Abstract: A clustering disk subsystem comprising a switch holding a table which can modify a destination of a request from a host computer, wherein the switch transfers an access request to another channel according to a destination channel status such as heavy load or fault, and the channel which received the request processes the request by proxy for load balancing between internal disk controllers in a clustering disk subsystem. The subsystem has an effect in which load balancing or fail-over between channels or disk controllers can be performed without any special hardware or software in the host. As a result, good performance can be obtained even when access requests from the host computer are concentrated in a specific channel or disk controller.

Abstract: A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.

Abstract: A computer system has a central processing unit, an input/output unit and two network units. The central processing unit is connected to the input/output unit via two network units. The central processing unit sends a frame, included in data, to the input/output unit via one network unit and simultaneously sends the same frame to the input/output unit via the other network unit. The input/output unit receives the same frames via both network unit. The input/output unit sends either of the same frames, whichever is received faster than the other, to the internal circuits.

Abstract: Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.

Abstract: A method for controlling communication. The method sends a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus, sends a control signal from the first processor to a selector, the selector switching electrical communication at least one signal line of the processor bus from the first bus to a second bus, sends a second instruction from the first processor to a second device, sends a control signal from the first processor to the selector, the selector switching electrical communication of the at least one signal line of the processor bus from the second bus to the first bus, and sends data from the first device to the first processor.