Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: A communication system that performs data communications based on an SCSI command defined in the SCSI standard, the communication system includes; a peripheral device that performs at least one of writing and reading to/from a recording medium inserted into a slot; and an information processing device connected to the peripheral device, including: an OS kernel; an adding unit that adds communication data to a free area of Inquiry data generated by issuing Inquiry command to the OS kernel; and a transmitting unit that transmits the Inquiry data to the peripheral device including the communication data added by the adding unit, wherein the peripheral device includes: a receiving unit that receives the Inquiry data transmitted by the transmitting unit; and an extracting unit that extracts the communication data added to the received Inquiry data.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2 . . . Mn each of which has a local memory, is disclosed. Objects A and B in each local memory are disclosed which each include primitive fields (11). However, the simultaneous operation of the application program (50) can result in a “non-primitive” reference field (10) in one machine which must then be replicated in all other machines. However, the reference field (10) references another object (H) in the one machine's local memory so corresponding objects (T, K) must be created in the local memory of each other machine and be referenced by the corresponding non-primitive field (10).

Abstract: Provided are a method, system, and article of manufacture, in which a logical path is established between a control unit and a channel over a fiber channel connection. Code for persistent information unit pacing is loaded into the control unit and the channel. An indicator is set in node descriptors of the control unit and the channel to indicate concurrent enablement of persistent pacing while retaining the established logical path between the control unit and the channel.

Abstract: According to one embodiment, a communication system includes a first communication control apparatus and a second communication control apparatus. The first communication control apparatus includes an acquiring unit, a generating unit, and a transferring unit. The second communication control apparatus includes a receiving unit and a processing unit. The acquiring unit acquires a computer file. The generating unit generates transfer information including the computer file and added information indicating a content of processing designated by a user of the first communication control apparatus from among plural contents of processing relating to the computer file. The transferring unit transfers the transfer information to the second communication control apparatus. The receiving unit receives the transfer information.

Abstract: A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch while one or more others perform a transfer.

Abstract: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.

Abstract: Embodiments of a secure module recorder system and method for securing recording and storing of information is provided. The system may include at least one secure module and a docking station having at least one receptacle for holding one of the secure modules. The secure module may include a tamper-resistant case, an input port for receiving an analog signal, a recording circuit for converting the analog signal into digitally formatted data, a memory device for storing the digitally formatted data, a playback circuit for reading the digitally formatted data from the memory device and converting the digitally formatted data into an analog playback signal, and an output port for transmitting the analog playback signal. The docking station may further include a first interface for receiving the analog signal from an external device and a second interface disposed within the receptacle for interfacing with the input port of the secure module.

Abstract: A transfer apparatus includes a connection status detection block, a storage status detection block, a no-operation status detection block, and a transfer block. The transfer block can automatically transfer candidate data to a memory device when a connected status is detected by the connection status block, the transfer candidate stored status is detected by the storage status detection block, and a no-operation status is detected by the no-operation status detection block.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.

Abstract: A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.

Abstract: An article of manufacture, apparatus, and a method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The method includes the host computer system obtaining a transport command word (TCW) for an I/O operation having both input and output data. The TCW specifies a location of the output data and a location for storing the input data. The host computer system forwards the I/O operation to the control unit for execution. The host computer system gathers the output data responsive to the location of the output data specified by the TCW, and then forwards the output data to the control unit for use in the execution of the I/O operation. The host computer system receives the input data from the control unit and stores the input data at the location specified by the TCW.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.

Abstract: A computer includes an extensible firmware interface with a storage device enumeration function that performs storage device enumeration operations in parallel.

Abstract: The present invention discloses a method of editing a multi-media playing schedule for a digital photo frame, a system and a computer readable storage medium thereof, which are characterized in that users can edit a multi-media playing schedule on the data processing apparatus when the digital photo frame is electrically connected to the data processing apparatus, and after editing of the multi-media playing schedule is finished, the multi-media playing schedule is transmitted to the digital photo frame and stored in the digital photo frame. Therefore, the problem of being unable to edit complicated multi-media playing schedules due to simple operation interface of digital photo frames can be solved.

Abstract: A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a transmit buffer is preferably provided for every other device on the bus with which it will communicate. One or more logic circuits, for example, a scheduler, is provided to coordinate exchange transactions between pairs of devices. Time delays are preferably provided between exchange transactions of different device pairs so as to prevent interference. Coherency checking is preferably implemented to avoid discrepancies introduced by information being held in a buffer pending an exchange transaction.

Abstract: A clustered storage array consists of multiple nodes coupled to one or more storage systems. The nodes provide a LUN-device for access by a client. The LUN-device maps to a source logical unit corresponding to areas of storage on the one or more storage systems. A target logical unit corresponds to different areas of storage on the one or more storage systems. The source logical unit is migrated in parallel by the multiple nodes to the target logical unit. Data to be copied from the source logical unit to the target logical unit are grouped into data chunks. Two or more of the plurality of nodes concurrently attempt to acquire an exclusive lock for a set of data chunks. The node acquiring the exclusive lock migrates the set of data chunks from the source logical unit to the target logical unit, while the exclusive lock is used to prevent other nodes from migrating the set of data chunks.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: According to some embodiments, an apparatus may be capable of exchanging information with t potential universal serial bus endpoints, where t is an integer greater than 1. Moreover, x endpoint state machines may be established, where x is an integer greater than 1 and less than t. A first endpoint state machine may then be assigned to a first potential endpoint having a pending work item. Before the apparatus has completed the pending work item associated with the first potential endpoint, the first endpoint state machine may be flushed, and the first endpoint state machine may be re-assigned to a second potential endpoint.

Abstract: A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.

Abstract: The present invention relates to service and maintenance solutions for programmable and/or reconfigurable modules (CM1, . . . , CMn), which are included in the nodes of a communications network (140). The module (CM1) contains a first digital storage unit (M1), which holds information pertaining to the accomplishment of a primary function of the module. A secondary function of the module involves control of the primary function. The module has an optical bi-directional interface (Iw) towards the first digital storage unit. Data in the first digital storage unit may be read out (D0) and may also be updated (Di) by the portable software carrier unit via the optical bi-directional interface. Data read-out as well as data updating may be accomplished independently of the primary function. Preferably, an access module (A) controls the bi-directional interface in response to an authorization signal (SA) from an authorization unit (120, 121, 122, 123).

Abstract: A scalable first-in-first-out queue implementation adjusts to load on a host system. The scalable FIFO queue implementation is lock-free and linearizable, and scales to large numbers of threads. The FIFO queue implementation includes a central queue and an elimination structure for eliminating enqueue-dequeue operation pairs. The elimination mechanism tracks enqueue operations and/or dequeue operations and eliminates without synchronizing on the FIFO queue implementation.

Abstract: The present invention provides an improved method and system of improving the efficiency, and ensuring the integrity, of a data transfer in a serverless backup, or third party copy, system having one or more physical storage devices. The present invention provides improvements to the processing of serverless copy, or EXTENDED COPY, commands, and transfers of data associated with such commands. These improvements increase the speed at which such commands are executed and completed, and increase the capabilities of copy managers in serverless backup systems. The improvements also make better use of the storage devices involved in the data backup process. The method broadly includes determining a desired manner of execution of segment descriptors, or instructions, as a function of components of those instructions. Other aspects of the invention allow for execution of data segments of any size, and validation of segment descriptors and target descriptors prior to data transfer.

Abstract: A storage system that includes: a plurality of microprocessors; a plurality of storage areas to be formed to a drive group; an assignment section that assigns, to each of the microprocessors, an ownership of accessing any of the storage areas; a management section that manages, as an operating ratio, a proportion of a time to be taken for each of the microprocessors to execute a request issued to each of the storage areas; a search section that searches, for transferring the ownership assigned to an arbitrary one of the microprocessors to any of the another microprocessor determined based on the operating ratio, one or more of the storage areas under the ownership of the arbitrary microprocessor for a transfer-target storage area; and a transfer section that transfers, to the another microprocessor, the ownership of the transfer-target storage area that is assigned to the arbitrary microprocessor.

Abstract: A method, apparatus and software is disclosed for processing input/output (I/O) requests for a mirrored storage volume in recovery mode in which the processing of normal I/O is optimised using the recovery map for the volume.

Abstract: A processing of consistent data sets by asynchronous application of a subscriber in an isochronous, cyclical communication system is provided. Accordingly, by connecting a communication memory and a consistency, transmission and reception buffer, copying processes leading delay can be kept to a minimum.

Abstract: Disclosed is provided an apparatus and a method for operating a macro command and inputting a macro command, wherein the apparatus including a storing unit storing control signals received from a control device for selecting of a menu item of a host device, a creating unit creating the macro command combined with the control signals, and an executing unit reading the macro command and executing functions corresponding to the respective menu item of the host device according to a combination sequence of the control signals included in the read macro command.

Abstract: The invention provides a motherboard that uses a high-speed, scalable system bus such as PCI Express® to support two or more high bandwidth graphics slots. The lanes from the motherboard chipset may be directly routed to two or more graphics slots. For instance, the chipset may route (1) thirty-two lanes into two ×16 graphics slots; (2) twenty-four lanes into one ×16 graphics slot and one ×8 graphics slot (the ×8 slot using the same physical connector as a ×16 graphics slot but with only eight active lanes); or (3) sixteen lanes into two ×8 graphics slots (again, physically similar to a ×16 graphics slot but with only eight active lanes). Alternatively, a switch can convert sixteen lanes coming from the chipset root complex into two ×16 links that connect to two ×16 graphics slots. The system according to the invention is agnostic to a specific chipset.

Abstract: A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller (500). Data is then transferred in response to the data pointers from BUFFER (512) and Buffer (514) and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.

Abstract: A memory control apparatus generates a plurality of commands whose unit of data transfer is smaller than the unit of data transfer of a memory access request, and when the memory access requests are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request source. The plurality of memory access requests are executed by time division and concurrently.

Abstract: A data transfer interface system is provided that directly transfers data from one data storage drive to another data storage drive under the control of a host. The host and data storage drives are jointly connected to one another with data lines and control lines. Each data storage drive is connected separately to the host with a read/write command line. The host initializes the data storage drives providing initialization data to the drives where the data may include position information and commend information. After initialization, the host concurrently instructs one data storage drive to read the data from the drive while the other data storage drive writes the data to memory.

Abstract: A method for implementing large scale parallel file I/O processing includes steps of: separating processing nodes into compute nodes specializing in computation and I/O nodes (computer processors restricted to running I/O daemons); organizing the compute nodes and the I/O nodes into processing sets, the processing sets including: one dedicated I/O node corresponding to a plurality of compute nodes. I/O related system calls are received in the compute nodes then sent to the corresponding I/O nodes. The I/O related system calls are processed through a system I/O daemon residing in the I/O node. The plurality of compute nodes are evenly distributed across participating processing sets. Additionally, for collective I/O operations, compute nodes from each processing set are assigned as I/O aggregators to issue I/O requests to their corresponding I/O node, wherein the I/O aggregators are evenly distributed across the processing set.

Abstract: A memory control apparatus generates a plurality of commands whose unit of transfer is smaller than the unit of data transfer of a memory access request, and when the memory access request are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request are executed by time division and concurrently.

Abstract: An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.

Abstract: A system that executes a long transaction in a system with limited transactional hardware resources. During operation, the system executes the long transaction in a non transactional mode, which does not use transactional hardware resources. The system defers stores generated during the long transaction so that the stores are not committed to the architectural state of a processor until the transaction is successfully completed. If the long transaction successfully completes, the system commits the long transaction, which involves performing multiple hardware transactions to commit the deferred stores to the architectural state of the processor.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for processing an ordered sequence of elements in one or more queues. A first element is received from a queue at a first processor. The first element is processed during a first processing time. A second element is received from a queue at a second processor. The second element is processed during a second processing time. The first and second processed elements are committed serially to a write queue, such that a temporal order between the first and second elements in the queues is maintained regardless of the durations of the first and second processing times.

Abstract: A method to update firmware in a plurality of peripheral devices and a computer using the method to reduce data transmission collisions and to reduce the time required to complete the update process. The process involves sending firmware update data from a computer that is connected to a communication network to printers or other peripheral devices that are also connected to the communication network. The computer 11 groups a plurality of peripheral devices (such as printers 13a1) connected to the communication network into separate transmission unit groups each containing up to a maximum number of peripheral devices with the maximum number determined by measuring the transmission speed of the network and thereafter deriving the maximum number by experimentation at the measured transmission speed. The update data for updating the firmware is transmitted to the peripheral devices of any one transmission unit group.

Abstract: A storage system that includes: a plurality of microprocessors; a plurality of storage areas to be formed to a drive group; an assignment section that assigns, to each of the microprocessors, an ownership of accessing any of the storage areas; a management section that manages, as an operating ratio, a proportion of a time to be taken for each of the microprocessors to execute a request issued to each of the storage areas; a search section that searches, for transferring the ownership assigned to an arbitrary one of the microprocessors to any of the another microprocessor determined based on the operating ratio, one or more of the storage areas under the ownership of the arbitrary microprocessor for a transfer-target storage area; and a transfer section that transfers, to the another microprocessor, the ownership of the transfer-target storage area that is assigned to the arbitrary microprocessor.

Abstract: A routing module applies a plurality of routing rules simultaneously to determine routing for a Fibre Channel frame. Each rule independently determines whether the rule applies to the frame as well as a routing result for the frame. The routing result includes a port address, a zoning indicator, and a priority designation that can be used to route the frame over a virtual channel in an interswitch link. A selector chooses between the results returned by the rules. A component receives routing results specifying an ISL group and selects a physical ISL for the frame. An in-band priority determined by the content of the frame header can also be used in place of the priority designation in the routing result.

Abstract: In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing.

Abstract: Systems and methods for providing efficient memory allocation, reduced processor intervention and power consumption, and increased memory access bandwidth. One embodiment comprises a system including a plurality of memory units which are accessible in parallel, a dynamic memory unit configured to dynamically allocate and deallocate storage space in the memory units, and a plurality of direct memory access (DMA) engines configured to access the memory units in parallel through the memory management subsystem. The system may be implemented in the MAC engine of a device that communicates with other devices via a wireless communication link. This embodiment may store packets in FIFOs within the memory units as elements of linked list data structures that can be joined together without having to move the previously stored data. DMA engines access a context table to obtain DMA channel information that enables them to move data through appropriate DMA channels.

Abstract: A system and method for managing multiple information handling systems using embedded control logic are disclosed. An information handling system includes a first port for receiving first analog video signals and embedded control logic operably coupled to the first port. The embedded control logic selects either the first analog video signals received by the first port or second analog video signals generated by the information handling system. A second port operably coupled to the embedded control logic transmits at least one of the first and second analog video signals to a master controller operably coupled to the information handling system.

Abstract: An image processing system includes: a receiving section that receives print information including at least a first control command indicating a first print setting and a second control command embedded in a document to be printed and indicating a second print setting; an interpreting section that interprets the first control command and the second control command; and a controller that performs a control so as to prohibit execution of processing based on one of the first control command and the second control command when the interpreting section determines that both of the first control command and the second control command cannot be concurrently executed.

Abstract: A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits to transfer data between different audio devices. Audio data is exchanged using a mapping overlay technique, in which the DMA circuits for two audio devices read and write to the same memory buffer. The computer system provides an audio manager API (application program interface) to enable applications running on the computer to control the various audio sources without knowing the hardware and implementation details of the underlying sound system. Different audio devices and their drivers control different functionality of the audio system, such as equalization, volume controls and surround sound decoding. The audio manager API transfers calls made by the applications to the appropriate device driver(s).

Abstract: The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.

Abstract: The invention describes combination I/O modules for automation. Various combinations of inputs and output with different electrical interfaces are offered providing greater flexibility in controller hardware selection.