Abstract: Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small.

Abstract: An apparatus including a first register, a second register, and a control logic. The first register may be configured to store requests from a plurality of clients for a current cycle. The second register may be configured to store an indicator value indicating which of the plurality of clients received a grant in a previous cycle. The control logic may be configured to determine which of the plurality of clients having a request in the current cycle receives a grant based upon (i) a pointer value and (ii) the indicator value.

Abstract: A method and apparatus for controlling access to a storage area network among a group of hosts in a distributed computing environment. A host requests access to the storage area network by issuing an input/output request, and the input/output request is intercepted at the dynamic multipath (DMP) layer. The DMP layer checks the input/output request against an access control list. The DMP layer can grant or deny the input/output request from the host system. If the input/output request is granted, then the DMP layer passes on the input/output request to the HBA driver layer and the host is allowed to access the storage area network. If the request to access the storage area network is denied, the DMP management layer can initiate an appropriate response, such as a security procedure or generation of an error message alerting a user the request has been denied.

Abstract: A processing system is provided including sharing a resource in a processor system for processing signals, the processor system having first and second conjoined-cores, and selecting the conjoined-core having control over the resource based on arbitration between the first and second conjoined-cores.

Abstract: The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the provision of a dedicated memory storing instructions for common processing The information processing apparatus comprises: a plurality of processor elements; an instruction memory storing a first program and a second program; and an arbiter interposed between the processor elements and the instruction memory, the arbiter receiving, from each of the processor elements, a request for an instruction, from among instructions included in the first program and the second program, and controlling access to the instruction memory by the processor elements, wherein the arbiter arbitrates requests made by the processor elements when the requests are (i) simultaneous requests for different instructions included in one of the first program and the second program or (ii) simultaneous requests for an instruction included in the first prog

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

Abstract: A computer-implement method, computerized apparatus and computer program product for formal verification of an arbiter design. The method comprising: performing formal verification of an arbiter design, wherein the arbiter design is based on an original arbiter design comprising a fairness logic and an arbitration logic, wherein the arbiter design comprising the arbitration logic and a portion of the fairness logic; and wherein the formal verification is performed with respect to a multi-dimensional Complete Random Sequence (CRS) having two or more dimensions.

Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holding unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: An integrated circuit device (100) comprising a first plurality of components (102-112), a second plurality of buses (114-124, 140, 142) for transmitting transaction requests from said components (102-112) to a resource (138) shared by said components (102-112) and a third plurality of arbiters (132-136) arranged in at least two levels of arbitration. Each transaction request has attached priority value that is used by the arbiters to determine which of the components should be granted access to the resource (138).

Abstract: Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.

Abstract: In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Abstract: A method and system for balancing loads of a plurality of bus lanes of a snooping-based bus. The system includes: a receiver for receiving snoop transactions from the bus lanes, each of the snoop transactions having a snoop request and at least one snoop response, an analyzer for analyzing respective actual and expected loads of each of the bus lanes dependent on the received snoop transactions, and a controller for providing a next snoop request from a number of outstanding snoop requests to a buffer allocated to the system, where the buffer is dependent on the analyzed loads of the bus lanes.

Abstract: A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states.

Abstract: Disclosed is a method of synchronizing a plurality of processors accesses to at least one shared resource. One of a plurality of processors requests an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target. The LBA is defined in a region map that associates LBAs to shared resources. The exclusive region lock request is inserted as a node in a region lock tree of the dummy target. Access to the shared resource is granted based on a determination whether there is an existing region lock in the region lock tree that is overlaps with the new exclusive region lock request.

Abstract: Described herein is a system having a multi-host low pin count (LPC) controller (100) configured to facilitate sharing of common peripheral devices by multiple hosts (115) of a multi-host computing system (110). In one implementation, the multi-host LPC controller (100) interfaces with the hosts (115) via an ON-chip bus or an LPC-IN-chip bus. Further, the multi-host LPC controller (100) includes a LPC-IN controller (160) and a microcontroller (155) to moderate among requests generated by the hosts (115). The requests can be target accesses, DMA accesses, and BM accesses. Also, the multi-host LPC controller (100) is configured to operate in a software mode and an auto mode. Based on the mode the multi-host LPC controller (100) is operating in, the requests generated by the various hosts are moderated.

Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op

Abstract: A storage system may include a set of storage devices; a controller; and a management device. The controller may arbitrate among operations for execution by the set of storage devices, where the operations are received from users that are associated with priority levels. The controller may maintain queues, corresponding to the users, to queue operations from the users. The controller may additionally include a scoring component and a scheduler. The scoring component may maintain a score for each queue. The scheduler may choose, from the queues and based on the score of each queue, one of the operations to service. The management device may receive usage updates, from the controller, reflecting usage of the set of storage devices; calculate a maximum allowed usage levels, based on the received usage updates, for each user; and transmit the calculated maximum usage levels to the controller.

Abstract: Two or more processors that each provides a specified thread to access a shared resource that can only be accessed by one thread at a given time. A locking mechanism enables one of the threads to access the shared resource while other threads are retained in a waiting queue. Responsive to an additional thread that is not one of the specified threads being provided access the shared resource during an identified time period, and responsive to a first criterion an a second criterion being met, the additional thread accesses the shared resource before the other threads in the waiting queue.

Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.

Abstract: Counter registers are shared among multiple threads executing on multiple processor cores. An event within the processor core is selected. A multiplexer in front of each of a number of counters is configured to route the event to a counter. A number of counters are assigned for the event to each of a plurality of threads running for a plurality of applications on a plurality of processor cores, wherein each of the counters includes a thread identifier in the interrupt thread identification field and a processor identifier in the processor identification field. The number of counters is configured to have a number of interrupt thread identification fields and a number of processor identification fields to identify a thread that will receive a number of interrupts.

Abstract: The information processing system includes: an information processor operating in an active state and a power saving state consuming less power than the active state, and recovering to the active state by receiving a signal in the power saving state and processing information in the signal; a signal transmitting device transmitting a signal to the information processor; and a communication line establishing communication between the information processor and the signal transmitting device. The signal transmitting device transmits the signal after appending, to a predetermined region inside the signal, the identification information for identifying a processing content of the signal.

Abstract: A disk drive is disclosed comprising a head actuated over a disk. The disk drive receives a plurality of access commands including a first access command out of a group G of access commands. The access commands are stored in a command queue. A completion status is received for a number of access commands out of the G access commands that are assigned to other disk drives, and the first access command is selected from the command queue based on the completion status.

Abstract: Apparatus includes a plurality of ports and arbitration circuitry. The plurality of ports is configured to connect a memory to a respective plurality of processing units that are configured to access the memory. The arbitration circuitry is configured to grant the processing units access to the memory via the ports in accordance with an arbitration scheme including multiple, alternating priority periods, such that in each priority period a respective processing unit is assigned an absolute priority over others of the processing units and the others of the processing units are assigned predefined relative priorities over one another.

Abstract: An asynchronous branching module (102) outputs transfer data received in accordance with a handshake protocol to any of branch destinations. An asynchronous arbitration module (101) merges transfer paths of the transfer data. A congestion detection module (111) receives an arbitration result signal from the asynchronous arbitration module (101) and outputs congestion information indicating presence/absence of congestion to a merge source. A congestion avoiding path calculation module (112) receives the congestion information and exclusively performs a process of storing the congestion information into a congestion information storage memory, and a process of making the asynchronous branching module (102) preferentially select, as a transfer branch destination, a branch destination generating no congestion information indicative of the presence of congestion from branch destinations leading to a destination, on the basis of the congestion information and the destination information of the transfer data.

Abstract: In a communication device with a graphics processor, a graphics asset can be shared with two or more applications. The graphics asset can include a bitmap of a digital image. An asset server can host a texture corresponding to the graphics asset and can share the texture with the graphics processor. The asset server can host multiple textures and can share those textures with the graphics processor for rendering. The graphics processor can use the shared texture to render an instance of the graphics asset for each of the two or more applications. The texture can be generated by copying information about the graphics asset into the asset server.

Abstract: In order to control sub-processors in parallel without losing extensibility, an execution control circuit (30), which forms a multi-processor system (1), issues a process command (CMD) to each of sub-processors (20—1 to 20—3) based on a process sequence (SEQ) designated by a main processor (10), and acquires a process status (STS) which indicates an execution result of processing executed by each of the sub-processors (20—1 to 20—3) in accordance with the process command (CMD). An arbiter circuit (40) arbitrates transfer of the process command (CMD) and the process status (STS) between the execution control circuit (30) and each of the sub-processors (20—1 to 20—3).

Abstract: A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., 14, 61) by executing a control instruction (47, 48) to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned device (14, 61) can determine if the access command can be performed based on local access control information.

Abstract: A wireless communication device that has one or more applications resident on a computer platform, a wireless communication interface, a display, and a user interface that, at least, appears on the display and through which a user of the wireless communication device interacts with the computer platform. The display is configured to be selectively controlled by the specific user interfaces of one or more applications resident on the computer platform, and the one or more applications and/or an arbiter that is resident on the computer platform will determine which user interface of the one or more applications resident on the computer platform controls the display based upon a predetermined criteria when the user interfaces compete for control of the display.

Abstract: A data processing apparatus and method for setting priority levels for transactions is provided. The data processing apparatus has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The at least one master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry is used to apply an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource, the arbitration policy using the priority level associated with each of the multiple transactions when performing the selection.

Abstract: A fieldbus system is provided, having a plurality of fieldbus devices and a controller. The controller is in communication with the plurality of fieldbus devices though a fieldbus. The controller transmits a plurality of high priority Receive Process Data Objects (RPDOs) and a plurality of low priority RPDOs to the plurality of fieldbus devices through the fieldbus. The controller includes a control logic for sending each of the plurality of fieldbus devices one of the plurality of high priority RPDOs during a frame. The frame is the fastest rate at which the high priority RPDOs are transmitted. The controller includes a control logic for sending at least one of the plurality of fieldbus devices at least one of the plurality of low priority RPDOs. The low priority RPDOs are grouped by a minimum wait time.

Abstract: An apparatus and method are disclosed for state sharing. A change module detects a change of a configuration state for at least one of a base and a detachable device. A connection module detects a connection between the base and the detachable device. The detachable device provides a display and a network connection for the base if the base and detachable device are connected. A synchronize module synchronizes the configuration state of the detachable device with the configuration state of the base in response to detecting the connection and detecting the change of configuration state.

Abstract: Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged.

Abstract: The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.

Abstract: It is an object to prevent a command-issuing interval from being fixed and then avoid a situation where a target always returns a retry by varying a timing of a command-issuing request (i.e., a request signal) from each initiator, even if a plurality of initiators simultaneously or alternately make a plurality of command-issuing requests (i.e., send request signals). Based on predetermined priorities, a bus control unit sends a grant signal to an initiator that has sent a request signal, thereby granting use of a bus to the initiator. A mask generating unit sends a mask signal to at least one initiator to have the initiator mask a request signal, thereby controlling a timing, at which the bus control unit grants use of the bus to the initiator, to be aperiodic.

Abstract: Embodiments relate to systems and methods for implementation on a mobile device to force the mobile device into a secure state upon detection or determination of a triggering event. Once it is determined that a triggering event has occurred, each application operating on the mobile device is caused to immediately unreference sensitive objects and a secure garbage collection operation is performed upon the unreferenced sensitive objects to render data associated therewith unreadable. The mobile device is then caused to enter a secure state, in which the mobile device cannot be accessed without authorization. A microprocessor within the mobile device is configured to determine the existence of the triggering event according to a configuration data structure and to perform the secure garbage collection.

Abstract: A system management bus (SM Bus) system includes an arbitrator; a slave device connected to the arbitrator via an SM Bus; a first master device connected to the arbitrator capable of sending a first start command for communicating with the slave device; and a second master device connected to the arbitrator capable of sending a second start command for communicating with the slave device. The arbitrator set the first master device to have a priority, and when the first start command is being executed and the arbitrator receives the second start command, the arbitrator confirms whether the SM Bus is busy or not after a second predetermined time, and if the SM Bus is not busy, the arbitrator transmits the second start command to the slave devices via the SM Bus.

Abstract: A system includes master modules, at least one multiport slave module, and a scheduler connected by a system bus. The scheduler is configured to provide scheduling information to the multiport slave module. The scheduling information includes master categorization information and anticipated burst information. The anticipated burst information is based on a scheduler determination for an anticipated bus access by an anticipated master module. The master categorization information categorizes the anticipated master.

Abstract: Sampled instruction address registers are shared among multiple threads executing on a plurality of processor cores. Each of a plurality of sampled instruction address registers are assigned to a particular thread running for an application on the plurality of processor cores. Each of the sampled instruction address registers are configured by storing in each of the sampled instruction address registers a thread identification of the particular thread in a thread identification field and a processor identification of a particular processor on which the particular thread is running in a processor identification field.

Abstract: A method for controlling access to data of a message memory, and a message handler of a communications module having a message memory, in which data are input or output in response to an access; the message memory being connected to a first buffer configuration and a second buffer configuration, and the data being accessed via the first or the second buffer configuration; in the message handler, at least one first finite state machine being provided which controls the access to the message memory via the first buffer configuration, and at least one second finite state machine being provided which controls the access via the second buffer configuration, the at least one first finite state machine and the second finite state machine making access requests; and a third finite state machine being provided which assigns access to the message memory to the at least one first and the second finite state machine as a function of their access requests.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: A method for issuing interrupts includes a receiving communication adapter receiving a first remote directed memory access (RDMA) write with immediate, identifying a completion queue descriptor corresponding to the first RDMA write with immediate and to a receiving entity, incrementing an interrupt counter in response to the first RDMA write with immediate. The method includes storing, by the receiving communication adapter, in response to determining that the interrupt counter value is less than the interrupt threshold value, data in the first RDMA write with immediate on the receiving device without triggering an interrupt to the receiving entity. The receiving communication adapter receives a second RDMA write with immediate, and increments the interrupt counter value corresponding to the completion queue descriptor in response to the second RDMA write with immediate.

Abstract: A mechanism for controlling data stream interruptions on a shared bus is provided. A first request is received to transfer data. High priority data components and low priority data components are determined for the first request. The high priority data components are transferred without interruptions. In response to receiving requests when transferring the high priority data components, the received requests are rejected.

Abstract: A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.

Abstract: An arbitration device includes an arbitration section, a counter, and a changing section. While write request signals and read request signals for a transfer path, are inputted from request sources, the arbitration section arbitrates an order that the write and read request signals use the transfer path, and when arbitration is settled, outputs use permission signals to the request sources. The changing section changes a time from outputting of the write request signals until inputting of the write request signals to the arbitration section, and/or a time from outputting of the use permission signals for the write request signals until inputting of the use permission signals to the request sources.

Abstract: A method that includes providing LRU selection logic which controllably pass requests for access to computer system resources to a shared resource via a first level and a second level, determining whether a request in a request group is active, presenting the request to LRU selection logic at the first level, when it is determined that the request is active, determining whether the request is a LRU request of the request group at the first level, forwarding the request to the second level when it is determined that the request is the LRU request of the request group, comparing the request to an LRU request from each of the request groups at the second level to determine whether the request is a LRU request of the plurality of request groups, and selecting the LRU request of the plurality of request groups to access the shared resource.

Abstract: Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are contemplated. Some embodiments may comprise a chipset that transmits the MSI to a processor to service the interrupt. The chipset may identify that a transaction is an extended MSI transaction by determining that the MSI has more than a four bytes. In several embodiments, the chipset may validate the MSI by determining that the MSI comprises at least six bytes and, in further embodiments, by determining that the extended MSI has a valid signature byte. Another embodiment comprises a processor to receive the extended MSI transaction and store the data to service the corresponding interrupt(s) in a low latency buffer. The processor may then service the interrupt(s) based upon the data when the processor becomes available.

Abstract: A centralised synchronizing device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system. A system synchronizing request is a request generated by one of the plurality of transaction generating devices and queries progress of a subset of the transaction requests. The synchronizing device includes: at least one port to and from the data processing system; a multicast circuitry configured to output a plurality of synchronizing requests for multicast to at least some of the devices within the data processing system where the requests query the progress of the subset of the transaction requests. Gather circuitry collects responses to the requests confirming that the queried progress has occurred at the respective devices. The gather circuitry determines when responses to all of the requests have been received and outputs a response to the system synchronizing request.

Abstract: A data processing apparatus and method are provided for arbitrating access to a shared resource. The data processing apparatus includes a plurality of requester elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests asserted by one or more of the requester elements for access to the shared resource, to perform a priority determination operation to select one of the asserted requests as a winning request. Each of the asserted requests has a priority level associated therewith, and the apparatus further comprises relative priority ordering circuitry for attributing relative priorities to the plurality of requester elements. The arbitration circuitry is responsive to the asserted requests to perform the priority determination operation in order to select as the winning request the request asserted by the requester element with the highest relative priority whose asserted request has a priority level not exceeded by any other asserted request.