Abstract: A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory device. A data word ordering designator is stored from each of the successive read operations and managed in a first-in first-out manner. The data word ordering designator configures ordering circuitry for the desired ordering of the plurality of data words simultaneously retrieved. Following the ordering of the plurality of data words, the properly ordered data words are latched in their desired order for subsequent delivery. Once the properly ordered data words are latched, the ordering circuitry is reconfigured according to the next oldest data word ordering designator. The data word ordering designator retains the pipelined ordering of the corresponding read operations to the corresponding memory banks of the memory device.

Abstract: A first queue receives transactions from a transaction source in first-in/first-out (FIFO) order regardless of priority. A second queue receives lower priority transactions from the first queue as compared to the higher priority transactions remaining in the first queue. A priority check module controls the forwarding schedule of transactions from the first and second queues in accordance with the associated priorities of the stored transactions. Should an address conflict arise between transactions in the first and second queues, the priority check module stalls forwarding from the first queue while promoting forwarding from the second queue during the conflict condition.

Abstract: A circuit for selecting one of N requestors in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the requestors is selected next. The first addend is an N-bit vector where each bit is false if the corresponding requester is requesting access to a shared resource. The second addend is a 1-hot vector indicating the last selected requester. A multithreading microprocessor dispatch scheduler employs the circuit for N concurrent threads each thread having one of P priorities. The dispatch scheduler generates P N-bit 1-hot round-robin bit vectors, and each thread's priority is used to select the appropriate round-robin bit from P vectors for combination with the thread's priority and an issuable bit to create a dispatch level used to select a thread for instruction dispatching.

Abstract: A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.

Abstract: Requestors issue access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a threshold, a free pass (FP) is granted to specified requesters. When issuing access requests, requesters request and acquire tokens before issuing the access requests if they have no FP granted. If the requesters have an FP, they simply issue the access requests.

Abstract: A data transfer system includes: a shared resource accessed from one or more devices; a plurality of request generation units each configured to generate a request for the device to access the shared resource, and output a remaining time value indicating how much time remains until the request is accepted before affecting an operation of an apparatus including the controller; and an arbitration unit configured to compare the remaining time values when the plurality of requests and the remaining time values are inputted from the plurality of request generation units, and give an access right to access the shared resource to a request with less remaining time.

Abstract: A bus system is provided, which includes a shared resource, a shared bus, a plurality of requesters, and a bus arbiter for arbitrating access requests made by the plurality of requesters to access the shared resource through the shared bus. At least one of the plurality of requesters outputs, according to an internal state in that requester, an internal state signal indicating that the priority of an access request made by that requester needs to be changed. The bus arbiter arbitrates the access requests in accordance with the internal state signal.

Abstract: Once accepting an interrupt, the control is such as to not accept any interrupt including that highest priority within the group to which the interrupt about to be processed belongs by referring to the interrupt management table. Then the vector number for the highest priority in the group from among the received interrupts is selected. Then the processing of a handler for the selected vector number is executed. The priority of the executed interrupt processing is reset to the lowest priority in the group.

Abstract: To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: Interoperable firmware for an information handling system supports embedded controller and chipset operations from a common SPI flash ROM. The embedded controller is disposed between the chipset and the flash ROM with a pass through port integrated in the embedded controller selectively providing primary access to firmware by the chipset or the embedded controller. The pass through port provides chipset access to firmware without inducing delays for normal system operations, yet provides an integrated switch for control and access of the firmware by the embedded controller for updating of firmware settings and firmware diagnostics. Application of power to the embedded controller allows access to chipset firmware even where the chipset lacks power, such as during manufacture of the information handling system.

Abstract: Methods and apparatus are disclosed for managing device reservation. In one embodiment, upon receiving a device command from a first host, a device targeted by the device command is reserved for the first host and a reservation time period for expiration of the reservation status is set.

Abstract: The embodiments provide an arbiter in a microprocessor that can handle requests to access a shared resource from function units with different priorities without starving the access opportunities of requests from function units with low priority. In one embodiment, a microprocessor is provided. The microprocessor includes a shared resource and a plurality of requesting entities accessing the shared resource. Each of the plurality of requesting entities has a priority value and requests from the each of the plurality of requesting entities are assigned the priority value. The plurality of requesting entities are function units of the microprocessor. The microprocessor also includes a priority-encode arbiter with an adjustable ring counter disposed between the shared resource and the plurality of requesting entities to control the access requests of the plurality of requesting entities to the shared resource.

Abstract: An arbitration device receives a plurality of requests from a plurality of circuits, and grants access to one of the plurality of circuits. The arbitration device includes a sorter and an arbitrator. The sorter receives position information of an image signal including a plurality of image layers and determines an access priority including a first group and a second group according to the position information. The arbitrator receives the access priority and at least one of the plurality of requests, and grants the access to one of the plurality of circuits according to the access priority and the at least one of the plurality of requests. In addition, each of the plurality of circuits generates data for each of the image layers correspondingly.

Abstract: A precedence determination system including a first type memory bank configured to receive a first search signal and to provide first search result indications, a second type memory bank configured to receive a second search signal and to provide second search result indications, a precedence number table coupled to the first and second type memory banks and configured to provide programmable precedence numbers, and a precedence determination circuit coupled to the first and second type memory banks and the precedence number table and configured to provide a third search result indication is disclosed. In one embodiment, the first type memory bank can be a static random access memory (SRAM) and the second type memory bank can be a ternary content addressable memory (TCAM).

Abstract: Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and setting a status bit to indicate that a bus transaction attempting to modify the shared resource is pending. The method further comprising retrying each subsequent nonmodifying bus transaction for the shared resource until the status bit is cleared.

Abstract: A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of multiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: Circuitry and methods enable masters without split capability to communicate with split capable slaves in a multilayer system. The output stage associated with each split capable slave, which usually comprises an arbiter, is augmented with a split filter. This split filter designates a channel on behalf of the master without split capability, filters the split and unsplit responses from the slave, and issues a second read request on behalf of the same master. Consequently, both the master without split capability and the split capable slave do not perceive any difference between this transaction and a normal one. The split filter implementation requires, at most, little change to the master and slave devices of the system.

Abstract: Methods and apparatus provide for: assigning each of a plurality of requesters to a respective one of a plurality of requester groups; receiving tokens from a plurality of resources, where each token is an exchange medium for permitting one of the requesters having the token to access an associated one of the resources for a period of time; receiving requests for the tokens from one or more of the requesters; allocating the tokens to at least one of the respective requester groups and the requesters thereof based on token allocation criteria; and dynamically re-assigning one or more of the requesters among the requester groups based on feedback information concerning at least some prior token allocations.

Abstract: The method and system for data transfer between the master device and the slave device through the bus are presented.

Abstract: A bus arbitration method for arbitrating a bus in a computer capable of executing a plurality of tasks by a plurality of devices connected to the bus is provided and includes: acquiring a task information at a timing, the information containing a priority of each of the tasks and a usage rate of each of the devices for executing each of the tasks; producing an information of a bus use condition of each of the devices on the basis of the priority and the usage rate so that that the bus is preferentially assigned to a device necessary to execute a task having high priority; and arbitrating the bus between the devices according to the information of the bus use condition.

Abstract: A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus masters. If two or more of the bus masters issue access requests at the same time, the bus arbitration section preferentially gives access permission to a bus master which gained access permission a number of times less than a set value in the bus arbitration information within the given period, out of the two or more access bus masters.

Abstract: A system and firewall for controlling access to resources within an information technology system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entity is identified. At least one required authority level of the requesting entity is determined for each command as a function of each command and a resource criticality classification of the resource associated with each command. The requesting entity is granted or denied the requested access to the resource associated with each command if a determination has been made that each condition of at least one specified condition has or has not been satisfied, respectively. The at least one specified condition is specific to each command and includes a condition of the assigned authority level matching or exceeding an authority level of the at least one required authority level of each command.

Abstract: A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processes to be executed on a plurality of processing units in an LSI are managed throughout the LSI in a unified manner. For each process to be managed, a priority is calculated based on the state of progress of the process, and the execution of the process is controlled according to the priority. A resource management unit IRM or program that collects information such as a process state from each of the processing units executing the processes and calculates a priority for each process is provided. Also, a programmable interconnect unit and storage means for controlling a process execution sequence according to the priority are provided.

Abstract: Collisions are resolved in a database replication system. The system includes a plurality of nodes arranged in either a master-slave or network configuration. Each node includes a database, wherein changes made at the databases of each node are replicated to the databases at one or more of the other nodes. When a collision is detected during data replication between multiple nodes, the collision is resolved by a rule that gives precedence to certain nodes over other nodes.

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract: A system includes at least one memory and at least one processor. The at least one memory is operable to store a resource object associated with a resource. The at least one memory is also operable to store a plurality of requester objects associated with at least a portion of one or more processes. The one or more processes are associated with production of one or more products using the resource. The at least one processor is operable to arbitrate between multiple arbitration requests from multiple ones of the requester objects. Each arbitration request indicates that one of the requester objects is attempting to acquire the resource object so that the associated resource is used to produce one of the products. The at least one processor is operable to use one or more user-defined strategies to arbitrate between the multiple arbitration requests.

Abstract: A resource management system including a plurality of requester elements competing to access a resource through an arbiter element that controls access to the resource by the requester elements. A requester element having a buffer unit and first and second counters, which are compared to determine if a request having an identified priority type is in the buffer unit.

Abstract: A method and a system of controlling access of data items to a shared resource, wherein the data items each is assigned to one of a plurality of priorities, and wherein, when a predetermined number of data items of a priority have been transmitted to the shared resource, that priority will be awaiting, i.e. no further data items are transmitted with that priority , until all lower, non-awaiting priorities have had one or more data items transmitted to the shared resource. In this manner, guarantees services may be obtained for all priorities.

Abstract: A method for implementing a spin lock in a system including a plurality of processing nodes, each node including at least one processor and a cache memory, the method including steps of: acquiring exclusivity to the cache memory; checking the availability of the spin lock; setting the spin lock to logical one if the spin lock is available; setting the spin lock to logical zero once processing is complete; and explicitly yielding the cache memory exclusivity. Yielding the cache memory exclusivity includes instructing the cache coherent hardware to mark the cache memory as non-exclusive. The cache memory is typically called level two cache.

Abstract: An apparatus and method for granting one or more requesting entities access to a resource in a predetermined time interval. The apparatus includes a first circuit receiving one or more request signals, and implementing logic for assigning a priority to the one or more request signals, and, generating a set of first_request signals based on the priorities assigned. One or more priority select circuits for receiving the set of first_request signals and generating corresponding one or more fixed grant signals representing one or more highest priority request signals when asserted during the predetermined time interval.

Abstract: A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: A display control circuit capable of performing arbitration with the use of a simple configuration. The display control circuit exchanges, with a plurality of masters, attribute information defining conditions for displaying video on a display, and includes a memory for storing the attribute information, a plurality of channels associated with the respective masters for accepting, from the masters, access requests to access the memory, and an arbitration controller configured by hardware. The arbitration controller arbitrates the access requests accepted via the respective channels and permits a selected one of the access requests to access the memory.

Abstract: Methods and devices utilizing operating system semaphores are described for managing access to limited-access resources by clients.

Abstract: A bus arbiter receives requests of initiators, and internally includes a page hit/miss determining unit with permissible determining function, a bank open/close determining unit with permissible determining function, and an LRU unit with permissible determining function. Regarding the priority of the request arbitration on the requests, the bank priority on the SDRAM is determined in the order of page hit, bank open, and LRU. Furthermore, each determining unit internally includes a permissible time determining unit, and processes, at top priority, the request of the initiator which the corresponding permissible time is below the count threshold value in the priority processing of the determining unit.

Abstract: The present invention is a rotating priority queue manager. A rotating priority queue manager in accordance with the present invention may include a plurality of source data channels, a corresponding plurality of processing resources, and an arbitrating interface directing the flow of data from the source channels to the processing resources where the data must flow over a shared data path. The plurality of processing resources may comprise any system of parallel processors where the servicing of input data must be carried out in a manner where there the maximum latency for processing a given data channel is determinable, the arbitration between channels is equal, no input channel may prevent another channel from being serviced, and lower priority processing resources are not prohibited from receiving input data if higher priority processing resources are not currently available or if higher priority data is not currently available.

Abstract: A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.

Abstract: A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset of the predictions is either issued to access a memory or filtered out as redundant. In another embodiment, an exemplary prefetcher predicts accesses to a memory. The prefetcher comprises a speculator for generating a number of predictions and a prediction inventory, which includes queues each configured to maintain a group of items. The group of items typically includes a triggering address that corresponds to the group. Each item of the group is of one type of prediction. Also, the prefetcher includes an inventory filter configured to compare the number of predictions against one of the queues having the either the same or different prediction type as the number of predictions.

Abstract: An aspect of the present invention provides an arbiter which grants a request (to access a resource) in the same clock cycle as in which the requests from requesters is received. In one embodiment, such a feature may be provided in case of arbitration policies requiring state information from previous grants. In another embodiment, such a feature may be provided when the arbitration policy is programmable such that the same arbiter can be used for different arbitration policies.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

Abstract: According to embodiments, the present invention comprises a method and system for managing support of quality of service requirements for various clients of a telecommunications network at a server level. Servers assigned to the various clients may include quality of service descriptors that identify relative priorities of the clients. In the event of a failure or reduced performance of a server, for example, an assignment of respective servers to respective clients may be changed based on the relative priorities of the respective clients.

Abstract: Apparatus, system, and method for arbitrating between memory requests are described. In one embodiment, a processing apparatus includes a memory request generator configured to generate memory requests specifying data for respective presentation elements. The memory request generator is configured to assign priorities to the memory requests based on a presentation order of the presentation elements. The processing apparatus also includes a memory request arbiter connected to the memory request generator. The memory request arbiter is configured to issue the memory requests based on the priorities assigned to the memory requests.

Abstract: A bus switch circuit having plural master side interface circuits inputting/outputting signals for plural bus masters respectively, and one or plural slave side interface circuit(s) inputting/outputting signals for one or plural bus slave(s), is provided. The master side interface circuit and the slave side interface circuit input an interrupt signal inputted at least to one bus master, and establish a signal path between the plural bus masters and the one or plural bus slave(s) in accordance with the interrupt signal.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may, for example, be indicated by a signal from, for example, a slot timer, a state machine may schedule the function that will be permitted to interrupt a processor. Only the scheduled function may interrupt the processor during the slot. Time dependent functions that may be waiting to be processed may have to wait until the start of a next slot. Background functions that are too large to be processed within the time available in a slot may, for example, be divided into segments, each of such segments capable of being processed within the time available in a slot.

Abstract: An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-prioritized exclusion right, which indicates a candidate for acquiring the contended resource, by a first process. The exclusion controller further includes a prioritized information processing unit acquiring the contended resource by a second process, which requires a shorter processing time than the first process, to the exclusion of the non-prioritized information processing unit having acquired the non-prioritized exclusion right.

Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.

Abstract: A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented in synchronization with a clock signal, and is incremented by a value equal to the first penalty every time the element is selected for an access cycle. When several elements are simultaneously waiting to access the shared resource, an element is selected to access the resource if its first counting value is lower than or equal to a determined threshold, and is lower than the first counting values of the other elements having sent an access request.