Abstract: A method for arbitration grants access to an ultra high priority device if the ultra high priority device requests access. This access is limited to a selectable number of accesses. Thereafter the ultra high priority device is masked from requesting access for a selectable interval of time during which access may be granted to other devices. The number of assess and the interval of masking are preferably controlled by memory mapped data registers loaded into dedicated counters.

Abstract: Resource requests are allocated by storing resource requests in a queue slots in a queue. A token is associated with one of the queue slots. During an arbitration cycle, the queue slot with the token is given the priority to the resource. If the queue slot with the token does not include a request, a different queue slot having the highest static priority and including a request is given access to the resource. The token is advanced to a different queue slot after one or more arbitration cycles. Requests are assigned to the highest priority queue slot, to random or arbitrarily selected queue slots, or based on the source and/or type of the request. One or more queue slots may be received for specific sources or types of requests. Resources include processor access, bus access, cache or system memory interface access, and internal or external interface access.

Abstract: Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bus arbitration logic uses a request vector and an arbitration vector to determine a grant vector. The grant vector indicates what primary component should be allowed bus access.

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract: An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2?P?N and 1?Q?N. In the event of a plurality of conflicting requests to access a common resource originating from a plurality of respective initiator modules, an arbitration unit grants an exclusive right of access to the resource to a defined one of these initiator modules. The arbitration unit is constructed either to apply a standard arbitration mechanism to these respective initiators, or to apply as a priority a specific arbitration mechanism only to the members of a subset of these initiator modules, for each of which it receives a linked privileged access signal.

Abstract: The present invention sets forth a method for content responding, a method for content requesting, a content responder and a content requester. A content responder receives a first request from a content requester via a network. Then, the content responder generates a first content based on the first request. Then the content responder receives a second request from the content requester via the network. Then, the content responder generates a second content based on the second request. Next, the content responder compares the second content with the first content. After that, the content responder transmits a second response with regard to the second request to the content requester via the network. The second response is generated based on the result of comparison.

Abstract: A system for executing applications designed to run on a single SMP computer on an easily scalable network of computers, while providing each application with computing resources, including processing power, memory and others that exceed the resources available on any single computer. A server agent program, a grid switch apparatus and a grid controller apparatus are included. Methods for creating processes and resources, and for accessing resources transparently across multiple servers are also provided.

Abstract: A method for arbitration among a plurality of requesting devices for a shared resource in which one device is an ultra high priority device grants access to one requesting device at a time. The ultra high priority device is granted access if it requests access interrupting access by another device. The ultra high priority device is limited to a selectable number of accesses and thereafter is masked for a selectable interval. This interval permits access may by other devices. Each of the other devices is also limited to a selectable number of accesses followed by re-arbitration. The other devices can have a normal priority or a time out priority if a request hasn't been granted in a selectable amount of time.

Abstract: Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from accessing the bus. An initiator transmits I/O requests on the bus to the I/O controller, wherein the I/O requests are queued in an I/O queue, wherein the I/O controller is inhibited by the reconnection inhibitor from draining the queue while the initiator transmits requests to the I/O controller.

Abstract: Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and allows the requests corresponding to a bank receiving the largest number of pending requests priorities; and write request information generated by masters is stored in a predetermined buffer to be output as additional master request information, and provides the corresponding master with an opportunity to generate new request information.

Abstract: A method, system, and firewall for controlling access to resources within an information technology (IT) system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entity is identified. At least one required authority level of the requesting entity is determined for each command as a function of each command and a resource criticality classification of the resource associated with each command. The requesting entity is granted or denied the requested access to the resource associated with each command if a determination has been made that each condition of at least one specified condition has or has not been satisfied, respectively. The at least one specified condition is specific to each command and includes a condition of the assigned authority level matching or exceeding an authority level of the at least one required authority level of each command.

Abstract: A computing system includes one or more buses, a plurality of bus agents, and a chip set. The plurality of bus agents are capable of accessing at least one of the buses. The chipset arbitrates access to a bus for at least two of the bus agents such that utilization of the bus for each agent is changeable.

Abstract: Bus transactions in a memory controller are scheduled by storing a set of configuration parameters that define a bus scheduling policy, generating values of a set of dynamic cost functions for each bus transaction, ordering the bus transactions in accordance with the bus scheduling policy to produce ordered bus transactions and generating a memory transaction that is derived from the ordered bus transactions. The memory controller includes one or more control registers for storing the set of configuration parameters, a bus interface operable to capture bus transactions from applications, a set of buffers operable to store the bus transactions and the set of dynamic cost functions and one or more registers operable to store the statistical data and a cost policy. The memory controller selects the order of the bus transactions based on an arbitration and selection policy and generates memory transactions to an external memory.

Abstract: A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transactions, or use to index storage locations that indicate priority values. The transaction identifiers can be selected to be associated with a transaction by the requesting device or other priority determination module based upon predefined criteria.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: An adaptive weighted arbitration algorithm that is user configurable is discussed. The arbitration logic and algorithm considers past arbitration history events and is dynamic to allow for losing bidders to increase their probability of being selected to access the resource based on an accumulator value and a weight value.

Abstract: A method for enhancing data rate of an advanced micro-controller bus architecture (AMBA) having an AHB system and an APB system includes simultaneously receiving control signals outputted from a plurality of master devices of the AHB system, and controlling a plurality of peripheral slave devices of the APB system according to the control signals outputted from the plurality of master devices.

Abstract: When four access request origins A, B, C, and D are present, a priority table (No. 1) having a priority order of A, B, C, and D, a priority table (No. 2) having a priority order of B, D, A, and C, a priority table (No. 3) having a priority order of C, A, D, and B, and a priority table (No. 4) having a priority order of D, C, B, and A are prepared. An order of employing these tables is determined in advance in this order. A priority table next in the order to the priority table employed in last arbitration or, when a priority table at the bottom in the order is employed in last arbitration, a priority table at the top in the order is employed. Based on the priority levels defined in the employed priority table, an access request to be accepted is selected.

Abstract: A data transfer apparatus includes a memory having first and second queues for storing data transfer information that includes information specifying a first memory area and information specifying a second memory area, a first processor which registers the data transfer information in the first or second queue, and a second processor performing a processing to transfer data stored in the first memory area to the second memory area. The second processor reads out the data transfer information registered in the first queue, transfers the data based on the read data transfer information, and decides if data transfer information succeeding to the read data transfer information is registered in the first queue. If the succeeding data transfer information is registered, the second processor reads out the succeeding data transfer information from the first queue, and performs the data transfer processing based on the read data transfer information.

Abstract: An information recording apparatus according to the present invention manages a priority value for each host that can log in, and allocates an immediate data buffer to each host based on the priority value. The priority value changes in accordance with data transfer amount, command importance degree, etc. The information recording apparatus recalculates the priority value regularly or arbitrary, and re-performs login negotiation by requesting re-login to the hosts. The amount of buffer allocated is dynamically changed by this login negotiation, and a buffer allocation state best suited to each occasion is built. Since the present invention can dynamically determine or change the allocation amount of the immediate data buffer in accordance with the condition of each occasion, the performance of an iSCSI apparatus can be improved.

Abstract: A method for providing mutual exclusion at a single data element level for use in embedded systems. Entries for tasks that are currently holding a resource are stored in a hold list. Entries for tasks that are not currently executing and are waiting to be freed are stored in a wait list. A single mutual exclusion semaphore flags any request to access a resource.

Abstract: A bus system is provided, which includes a shared resource, a shared bus, a plurality of requesters, and a bus arbiter for arbitrating access requests made by the plurality of requesters to access the shared resource through the shared bus. At least one of the plurality of requesters outputs, according to an internal state in that requester, an internal state signal indicating that the priority of an access request made by that requester needs to be changed. The bus arbiter arbitrates the access requests in accordance with the internal state signal.

Abstract: Data bus system and method are provided for controlling service engagements for bus users. At least one bus user provides services and other bus users use these services. A resource manager stores information about the available services and information about the service-providing bus users. The resource manager reserves a service from a providing bus user if the service can be used, and sends a response to a requesting bus user, allowing the requesting bus user to use the service from the providing bus user via the data bus. Information about the provided services is provided on the data bus via a standard interface by the bus users and a change in the provision of a service by a bus user is made available to the resource manager via the standard interface. The resource manager controls the service engagement on the basis of a priority information item.

Abstract: A method of serializing administrative operations on virtual volumes includes operating a storage system to maintain a plurality of virtual volumes that share a pool of block storage, where each of the virtual volumes containing data stored on one or more physical storage devices. Administrative access to each of the virtual volumes is controlled individually by imposing serialization on administrative operations directed to each virtual volume.

Abstract: An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates in response a critical rank vector comprising at least first and second components. An arbitrator receives the critical rank vectors generated by rival the agents and applies a maximum or minimum extracting mechanism to at least one of the two components of the critical rank vectors to uniquely identify the block accessing the resource. Thus, functional blocks can be separated from arbitration control, the agents implementing the arbitration control and being solely responsible for it.

Abstract: A system includes at least one memory and at least one processor. The at least one memory is operable to store a resource object associated with a resource. The at least one memory is also operable to store a plurality of requester objects associated with at least a portion of one or more processes. The one or more processes are associated with production of one or more products using the resource. The at least one processor is operable to arbitrate between multiple arbitration requests from multiple ones of the requester objects. Each arbitration request indicates that one of the requester objects is attempting to acquire the resource object so that the associated resource is used to produce one of the products. The at least one processor is operable to use one or more user-defined strategies to arbitrate between the multiple arbitration requests.

Abstract: The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.

Abstract: A task management system that inherit priority and that can reduce the queue operation required for transition to/return from a mutual exclusion awaiting state The task management system can execute a task without considering its priority, start or stop a server task and inherit priority without operating the dispatch queue. The task management system includes activity retaining information, context retaining information, and a dispatch queue used to select the highest priority task. Information on a task is divided and managed by the activity and the context, where each activity is inserted into/deleted from the dispatch queue. When the priority of a task is inherited by another task, only the correspondence between activity and context is changed.

Abstract: A system and method for arbitrating for access to a resource group between agents according to a respective programmable weight for each agent. For each agent, a programmable mapping module selectively couples a respective arbitration handshake signal of the agent to one or more arbitration ports, and the number of the coupled arbitration ports for the agent is the respective programmable weight. A selection module selects one of the arbitration ports in response to a priority ranking of the arbitration ports, and access to the resource group is granted to the agent that has the respective arbitration handshake signal that is selectively coupled by the programmable mapping module to the selected arbitration port. A ranking module provides the priority ranking of the arbitration ports and updates the priority ranking in response to the selection module selecting the selected arbitration port.

Abstract: The invention relates to management of I/O in data storage systems. In an embodiment, the invention provides a data storage subsystem processing I/O requests each having a priority, comprising a processor, a memory coupled to the processor, a disk array, an array controller coupled to the processor and the disk array, a network interface, coupled to the processor, to receive an I/O request with a priority, and a program in the memory for managing the I/O request based on the priority, a clip level of the priority, the total workload in the data storage subsystem, and processing I/O requests based on priority, workload clip levels, and fairness levels. The invention also contemplates the use of static and dynamic adjusted clip levels.

Abstract: A method, system and computer program product for creating and dynamically selecting an arbiter design within a data processing system on the basis of command history is disclosed. The method includes selecting a first arbiter for current use in arbitrating between requestors for a resource. During operation of said data processing system, an arbiter selection unit detects requests for the resource and selects a second arbiter in response to the detected requests for the resource.

Abstract: The invention provides a system and method for memory bus assignment for a plurality of functional devices. According to a preferred embodiment, the invention provides a system comprising a plurality of functional devices accessing a memory bus wherein the memory bus allows access by one of the functional devices for one cycle of period of time, a plurality of request agents corresponding to the functional devices, a control register respectively storing access priority grades for the request agents, a plurality of counter timers respectively loading the access priority grades; and a bus elector coupled with the counter timers wherein the bus elector respectively compares the loaded access priority grades and elects one out of the request agents according to the compared access priority grades. The memory bus accordingly allows access by one of the functional devices corresponding to the elected request agent for one cycle of period of time.

Abstract: An arbitration structure, a method, and a computer program are provided for an arbitration scheme that can handle a plurality of memory commands in an operating system. Typically, in a memory system there are three types of memory commands: periodic, read, and write. An arbitration scheme determines the order of priority in which these commands are executed. This arbitration scheme is flexible because it contains a read/write priority module, which can be programmed to execute any order of priority combination of read and write commands. This enables an arbitration scheme for any memory system to be easily programmed for maximum efficiency.

Abstract: A method and apparatus for controlling a device by a serial link from a dual processor system. The configuration of the circuit is simplified and efficiency is enhanced by using independent internal buses and serial link control hardware for each processor and by selecting the active control hardware through arbitration. An MCU and a DSP can operate asynchronously and use their respective internal bus at the same time.

Abstract: Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.

Abstract: A priority determining unit determines a priority of a status of a device connected to a second bus that is connected, via a bridge, to a first bus to which a central processing unit and a storage unit are connected. A bus-status determining unit determines a use status of the second bus. A status writing unit writes the status to the storage unit based on a result of determination by the priority determining unit and a result of determination by the bus-status determining unit.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.

Abstract: A processor is used to evaluate information regarding the number, size, and priority level of data transfer requests sent to a plurality of communication ports. Additional information regarding the number, size, and priority level of data requests received by the communication ports from this and other processors is evaluated as well. This information is applied to a control algorithm that, in turn, determines which of the communication ports will receive subsequent data transfer requests. The behavior of the control algorithm varies based on the current utilization rate of communication port bandwidths, the size of data transfer requests, and the priority level of the these transfer requests.

Abstract: A method, computer program product, and a data processing system for transferring request prioritizations in a data processing system network is provided. A first data processing system receives a transaction request and identifies a priority of the transaction request. The first data processing system processes and conveys the transaction request to a second data processing system according to the priority, and the second data processing system processes the transaction request according to the priority.

Abstract: Methods, systems, and computer program products for transmitting first-priority data and second-priority data. The first-priority data and second-priority data are stored in separate data buffers, and the first-priority data is transmitted preferentially over the second-priority data.

Abstract: A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be assigned ownership of the bus. The target uses delayed transactions to complete a read access targeted to it. The target also integrates a buffer management scheme, in one embodiment an input/output cache, for buffer management. The present invention optimizes the performance and utilization of the PCI bus.

Abstract: A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requestors and pointer. The banks of requestors and pointers operate on sequential AND-OR-Inverter/OR-AND-Inverter (AOI/OAI) logic to advance the pointer and efficiently select those requestors with pending requests. The use of the AOI/OAI logic circuitry in the banks of requestors and pointers allows for efficient selection and minimization of complex circuitry reducing the overall circuit area.

Abstract: A scheduler may be configured to schedule a plurality of blocks of concurrent code for multi-threaded execution. The scheduler may be configured to initiate multi-threaded execution of the blocks of concurrent code in an order determined by block-level performance criteria for the blocks of concurrent code to reduce overall execution time of the concurrent code. In one embodiment, the scheduler may be configured to schedule code blocks having a longer run time ahead of blocks having a shorter run time. The scheduler may be configured to schedule a group of said blocks based on a goal of each of the blocks of the group completing execution at approximately the same time. The scheduler may also be configured to initiate multi-threaded execution of each block of the group at different times according to the block-level performance criteria to the goal.

Abstract: The invention relates to management of I/O in data storage systems. In an embodiment, the invention provides a data storage subsystem processing I/O requests each having a priority, comprising a processor, a memory coupled to the processor, a disk array, an array controller coupled to the processor and the disk array, a network interface, coupled to the processor, to receive an I/O request with a priority, and a program in the memory for managing the I/O request based on the priority, a clip level of the priority, the total workload in the data storage subsystem, and processing I/O requests based on priority, workload clip levels, and fairness levels. The invention also contemplates the use of static and dynamic adjusted clip levels.

Abstract: For use in a data storage system, a method of dynamically controlling accesses to and from the storage device array.

Abstract: In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.

Abstract: A precedence determination system including a first type memory bank configured to receive a first search signal and to provide first search result indications, a second type memory bank configured to receive a second search signal and to provide second search result indications, a precedence number table coupled to the first and second type memory banks and configured to provide programmable precedence numbers, and a precedence determination circuit coupled to the first and second type memory banks and the precedence number table and configured to provide a third search result indication is disclosed. In one embodiment, the first type memory bank can be a static random access memory (SRAM) and the second type memory bank can be a ternary content addressable memory (TCAM).

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.