Abstract: The hardware semaphore generates an interrupt signal upon a change in ownership status of a shared resource. In particular, the semaphore apparatus generates an interrupt signal when a requesting device or process relinquishes control of a shared resource. By generating a hardware interrupt when a shared resource becomes available, devices or processes that require access to the resource need not repeatedly poll the hardware semaphore to determine if the resource associated with the semaphore is available. In a preferred embodiment, the hardware semaphore apparatus employs a pair of cross-coupled NOR gates for arbitrating between two requesting devices. A pair of rising edge detectors and flip-flops are connected to outputs of the NOR gates for generating the interrupt signal. Other exemplary and illustrative embodiments are described as well.

Abstract: An apparatus for a distributed system having a plurality of nodes and a switch network for passing messages between nodes, each message being sent from a source node to a target node. Each node is connected to the switch network by an adapter having a count register for adding the value of the packets in messages received by the adapter to the value in the count register and a threshold register for containing a desired threshold value. An interrupt generator generates interrupts when the value in the count register is equal to or greater than the value in the threshold register. The value in the threshold register may be changed under program control to enable or disable interrupts.

Abstract: A method and apparatus for processing interrupts for a plurality of components connected to and sharing an interrupt line in a data processing system in which interrupts are level sensitive interrupts. The components are connected to the interrupt line by interrupt connections, such as a pin. An interrupt is detected when the interrupt line is in a first state, while an interrupt is absent when the interrupt line is in a second state. Other interrupts cannot be processed while the interrupt line is in a first state. In response to detecting one or more interrupts, the connection associated with the component, for which one or more interrupts are generated, is disabled until all of the interrupts are processed. Disabling the interrupt connection allows the interrupt line to return to the first state and for additional interrupts for other components connected to the interrupt line to be detected and processed.

Abstract: A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt signals. This protection circuit comprises a controllable interrupt signal passage circuit which, depending on an output signal of a control signal source, can be controlled to a state permitting the passage of the non-maskable interrupt signal or to a state blocking said signal. The control signal source comprises a clock counter with overflow resetting function, by means of which program step clock pulses can be counted starting from a predetermined initial counting value until a predetermined overflow counting value is reached. The control signal source comprises furthermore an interrupt signal counter the counting value of which can be increased by each non-maskable interrupt event and decreased each time the overflow counting value of the clock counter is reached.

Abstract: A general purpose computer operating system is run using a real time operating system. A real time operating system is provided for running real time tasks. A general purpose operating system is provided as one of the real time tasks. The general purpose operating system is preempted as needed for the real time tasks and is prevented from blocking preemption of the non-real time tasks.

Abstract: An interrupt scheme for a data processor includes an enable field for a non-maskable interrupt (NMI). The field is automatically cleared by the data processor when it services the highest priority interrupt, a RESET. The user can set the field to enable a subsequent NMI but cannot himself clear the NMI. This strategy prevents an NMI from interrupting a RESET service routine.

Abstract: A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data coder forces the output signals to be other than complementary. The output stage normally generates a data output signal corresponding to the complementary data input signals. However, when the data input signals are other than complementary, the output of the output stage assumes a high impedance condition. Since the timing of the high impedance condition is determined from the data signals themselves, the timing of the mask operation is inherently properly timed to the output of the data from the data output buffer.

Abstract: A microcomputer capable of solving a problem in that the load of software is heavy for setting a watchdog timer in a conventional microcomputer. It includes a switching circuit which supplies a central processing unit with the output of the watchdog timer as an interrupt signal unless a memory data write mode for writing data to a memory is not designated from the outside of the microcomputer, and which inhibits an overflow signal of the watchdog timer from being supplied to the central processing unit when the memory data write mode is designated from the outside of the microcomputer.

Abstract: In an interrupt-driven data frame stream receiver, an interrupt to a host processor is applied by an interrupt system that comprises a timer logic circuit, an address match circuit, a data frame counter, a cyclic redundancy check (CRC) logic circuit, a frame length logic circuit, and a frame content detector. Each of these circuits is coupled to an OR gate. A Start Frame Delimiter (SFD) detector is connected to the inputs of the other circuits.

Abstract: A method and apparatus for operating a computer system at the interrupt level. Rather than having a primary task list that is interrupted to service interrupts, all tasks derive from interrupts. To this end, interrupt-time data structures and representations are precomputed and represented. The taxonomy of real time data types is organized. It is preferable to include isochronous media, together with supporting algorithms and heuristics.

Abstract: Apparatus for arbitrating the selection of an interrupt for servicing from a plurality of interrupts in which a priority level for each of the plurality of interrupts is programmed in a first register and each of the interrupts which is to be evaluated for selection for servicing is set as pending in a second register. Only a pending interrupt having a priority level above a pre-set current interrupt priority level is selected for servicing and where multiple pending interrupts of the same priority level occur, the one with the highest order bit position in the second register is used.

Abstract: A method and data processing system for emulating a program are disclosed. According to the present invention, the data processing system runs under a first operating system and emulates the execution of a program under a second operating system within a second data processing system. The data processing system includes a memory which stores at least a portion of the first operating system and an emulator comprising a plurality of routines which each emulate an instruction utilized by the first operating system. The memory further includes a simulated mass storage data area which stores at least a portion of the program and a simulated main memory data area. The data processing system further includes a processor which executes instructions within the program under the first operating system by emulation. According to the present invention, the emulator accesses instructions of the program directly from the simulated mass storage data area to minimize emulation overhead.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract: An interrupt circuit on a first integrated circuit receives a plurality of interrupt request signals, at least one of which is provided over a bus. A interrupt synchronization control circuit receives an update synchronization signal, indicating when a value of one of the interrupt requests provided to the interrupt circuit has been updated. The interrupt synchronization control circuit also receives an end of interrupt from a processor. The interrupt synchronization control circuit prevents the interrupt circuit from reevaluating its interrupt request signals based on the end of interrupt until after a next update synchronization signal is received, thus synchronizing the reevaluating of interrupt requests to receipt of updated interrupt request information.

Abstract: A central processing unit (CPU) (162) furnishes an interrupt request acknowledge signal (107) to an interrupt control unit (ICU) (101) in response to an interrupt request signal (106) from the ICU (101). Then the CPU (102) reads the address specifying the origin of a program to process the interrupt request. After that, the CPU (102) causes the interrupt request acknowledge signal (107) to make a transition to its deactivated state. In response to the transition in the interrupt request acknowledge signal, the ICU (101) causes the interrupt request signal (106) to make a transition to its deactivated state and then clears an interrupt priority level signal (108) showing the priority level of the interrupt request (106).

Abstract: The invention provides a method for interrupting processing by a processor. The method includes the step of requesting an analysis interrupt by setting a bit in a register in the processor (119), the bit associated with an analysis interrupt, the analysis interrupt having a configurable priority. The method also includes the step of detecting the analysis interrupt request. The method further comprises assigning an assigned priority level (114) to the analysis interrupt from a range of priority levels and processing the analysis interrupt (124) based on the assigned priority level.The invention also provides a processor having a memory unit (14, 16) and a central processing unit (12) operable to access the memory unit. The central processing unit (12) includes an interrupt priority parameter storage system (80) for storing an interrupt priority parameter.