Abstract: The present invention provides storage system controllers and methods of controlling storage systems therewith. The controller (10) includes a main processor (12), a memory (14), a device interface (18) adapted to interface a peripheral component (28-32), such as a RAID storage device, with the storage system controller, and an operations sequencer (24). The main processor sequences a plurality of tasks to be executed to complete an operation. The operations sequencer coordinates an execution of the plurality of tasks. Methods of the invention include receiving a task status for each of the plurality of tasks that is executed, and issuing an interrupt to the main processor after all of the plurality of tasks of the operation are finished executing. In this manner, the operations sequencer offloads at least some of the main processor overhead to improve processor efficiency.

Abstract: A system for automatically resetting an interrupt output is provided in a network controller having an interrupt management block that asserts the interrupt output in response to interrupt events. The interrupt output may be asserted in a real time mode or in a batch mode. An interrupt register contains bits that represent various interrupt events. An interrupt control register has enable bits for enabling or disabling an interrupt in response to certain interrupt events represented in the interrupt register. Also, the interrupt control register contains an interrupt pin enable bit for enabling or disabling the interrupt output of the controller. In response to an interrupt enable command from a CPU, the interrupt pin enable bit is set to 1 to enable the activation of the interrupt output of the controller. In response to the activation of the interrupt output, the CPU performs read access to the interrupt register to read an interrupt event that caused the interrupt.

Abstract: In one embodiment, the present invention provides a storage system controller (10) having a main processor (12), a memory (14) and a device interface (18) adapted to interface with a peripheral component (28-32). The controller further includes an interrupt management scoreboard (24) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.

Abstract: A method for managing interrupts in a microprocessor includes interrupts having a two-fold order of priority, i.e., a software priority and a hardware priority, wherein the microprocessor operates in two modes. During a first mode, the execution of an interrupt routine cannot be interrupted by the arrival of a new interrupt, even if it is a priority interrupt, unless this new interrupt is non-maskable. During a second mode, the execution of an interrupt routine is interrupted by the arrival of a priority interrupt. At the time of the execution of an interrupt, its software priority level is loaded into the state register of the microprocessor.

Abstract: An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to be provided, and hardware logic operates to control how that data is provided. An interrupt vector register is included in the computer CPU. The interrupt vector register does not act like the typical register. It is not a physical register, and cannot be written to. A read to this register by the programmable software, triggers the hardware logic. Once triggered, this logic performs certain control tasks, the end result of which is returning to the programmable software, a vector corresponding to the interrupt having highest priority. The programmable software can implement various software policies, in addition to the hardware policy implemented by the hardware logic.

Abstract: A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.

Abstract: An operating system provides a common name space for both long filenames and short filenames. In this common namespace, a long filename and a short filename are provided for each file. Each file has a short filename directory entry and may have at least one long filename directory entry associated with it. The number of long filename directory entries that are associated with a file depends on the number of characters in the long filename of the file. The long filename directory entries are configured to minimize compatibility problems with existing installed program bases.

Abstract: A compiler comprises a using register control table by function, a using register extracting unit by function for extracting a using register and a call function name, in every function, based on the intermediate code generated from a source program, and registering the same into the using register control table by function, a using register totaling unit by function for totaling the registers used by a call function called by an interruption function, and newly registering the totaled registers in the using register control table by function as the using registers of the interruption function, and an output unit for adding saving/return codes of a using register of the interruption function to the intermediate code, with reference to the using register control table by function so to generate and supply an assembly program file.

Abstract: A method and apparatus for detecting an interrupt request in a video graphics or other system are accomplished by reading or polling a shared interrupt request flag stored in one of multiple potentially interrupting devices and determining whether a pending interrupt request exists based on a status of the shared interrupt request flag. In the event that a pending interrupt request exists, a notification of the pending interrupt request is provided to an interrupt service routine. In the event that a pending interrupt request does not exist the circuitry that is reading or polling the shared interrupt request flag delays for a polling interval and then repeats reading or polling the shared interrupt request flag and determining whether a pending interrupt request exists.

Abstract: In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.

Abstract: A method and an apparatus for handling interrupt requests generated by a plurality of interrupt sources (2A, 2N) for a processor. The method includes steps of scanning interrupt registering means (8) for determining a current interrupt request to be sent to the processor among interrupt requests having respective interrupt flags inputted in said interrupt registering means, and steps involving the processor for execution of an interrupt processing program according to the result of a comparison of a scanned interrupt flag with a predetermined flag value, characterised in that it includes a step of latching a flag corresponding to a first occurring interrupt request from a source in a group of sources into interrupt latch registering means (7) for further processing and for blocking further interrupt requests from at least the same source in the same group from having a flag latched before processor controlled resetting.

Abstract: An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.

Abstract: A ring computer network system having a communication controller for controller the receipt and sending of packets or messages at each client computer. The interface associated with each client computer includes a send message buffer and a receive message buffer. The send message buffer has a send message buffer counter which increments upwardly in response to messages being received from the client computer for sending on the ring network. The communication controller sends messages from the send buffer until the send message buffer counter reaches the address or a value associated with the last received message. Similarly, the receive message buffer includes a receive message buffer counter which increments as each message is received to a receive message buffer counter value. The receive message buffer is emptied until the receive message buffer counter value is reached. The receive buffer can also have a foreground portion and a background portion.

Abstract: A method and apparatus for managing interrupt requests from devices on a subordinate bus is disclosed. An interrupt request storage area is provided on the bridge device to allow the bridge device to log and track interrupt requests. Once an interrupt request from an interrupting device is logged, all previous transactions from the interrupting device is allowed to complete while no further transactions from the interrupting device is allowed. All other devices operates normally during this time. Once the interrupt request is serviced, the interrupting device is allowed to resume normal operation. By providing a storage area to store the interrupt requests from devices on a subordinate bus, the unprocessed transactions in the bridge device and transactions from all other devices can be processed in an orderly manner.

Abstract: In a preferred embodiment of the present invention an a method whereby a pipelined data processor with an embedded microinstruction sequencer can give special consideration to the interrupt of the microinstructions translated from a macroinstruction using two control bit data, accelerate the reaction time to interrupts, and expand the time frame within which to process interrupts while maintaining a precise interrupt. When a macroinstruction is decoded into microinstructions at the decoder stage in a pipelined data processor, a control bit called the atomic bit provides the system with the information about the boundary of the precise interrupt, and another control bit called the LOCK bit decides when an external interrupt can be processed and masks an interrupt when the system state does not allow any interrupt to be processed.

Abstract: Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.

Abstract: An interrupt masker for use in an interrupt handler which receives interrupt request signals in the form of edge detection or level assertion is disclosed. The interrupt masker comprises interrupt detection means for detecting edge transitions of interrupt request signals. The interrupt masker also comprises a polarity detection means for detecting edge transitions of a polarity control signal which is inverted for each inversion polarity request. A filtering means which is coupled to the interrupt detection means and to the polarity detection means generates an interrupt request pulse according to the assertion of the polarity control signal. The interrupt request pulse is generated in response of either rising or falling edge transitions of the interrupt request signal.

Abstract: In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data representative of a task priority designation of a processor of the computer system, and to provide a signal responsive thereto. The apparatus also includes remote priority capture logic to receive the signal responsive to the task priority update transaction and update contents of the remote priority capture logic in response thereto. In another embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus an end-of-interrupt (EOI) transactions and to provide an EOI signal responsive thereto.

Abstract: A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that can transmit a chained series of buffers without processor intervention. The buffers, however, include an interrupt on end-of-buffer flag that allows for an interrupt to be generated at the end of each buffer on a buffer-by-buffer basis.

Abstract: A command queuing engine in a target controller ASIC automatically detects sequential commands received from an initiator and generates a linked list of data transfer descriptors for the sequential commands. The data transfer descriptors are automatically processed by the command queuing engine to reduce command overhead from interrupt processing by a microprocessor in the target controller, thereby improving the performance of the target controller.

Abstract: A system generates interrupts in response to events and dynamically accommodates for changing rates of event generation. A number of events may be bundled together to generate one or more interrupts instead of generating an interrupt for each event. For example, in connection with network controllers, each time a frame is received, it may be stored and bundled with a predetermined number of other frame receipt events to decrease the number of interrupts which must be handled. If a timer times out before all of the predetermined events have occurred, the ensuing bundle size may be decreased. Conversely, if all of the events occur before the timer times out, the ensuing bundle may be increased in size. In this way, the system dynamically accommodates for increased or decreased event activity, optimizing the number of interrupts that may be necessary.

Abstract: This device controls the interrupts of a microprocessor based on events occurring in at least one entity associated with this microprocessor. The device organizes the storage of words representative of at least an origin and a type of the interrupt issued by the entity. The interrupts from the entity are stored in an area of a memory. When there is more than one entity, each entity has an area of memory allocated to it. The microprocessor can access these memory areas and process the interrupts. An indicator is also provided so that the device can tell when a memory area has become full.

Abstract: A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the second register is checked to determine whether the second register contained exception information. If the second register contains exception information, then an exception routine is initiated. If, however, a second register does not contain exception information, then the instruction is executed and data within the second register is used in the execution.

Abstract: A circuit arrangement having a microprocessor whose reset terminal is adapted to receive a reset signal from a driving circuit. A simple reset wiring of the microprocessor is implemented in that the reset terminal is additionally connected to a further terminal of the microprocessor which, after the reset terminal has received the reset signal, holds the reset terminal to a defined suppressing level that deviates from the reset level.

Abstract: A programmable controller includes memory for storing a ladder logic control program having a plurality of ladder logic instruction rungs. Each rung begins with a start of rung (SOR) instruction. A processor is coupled to the memory for executing the ladder logic control program. User interrupts are disabled during execution of the rungs. During execution of the SOR instruction, a predetermined register, such as a MCR register, is read causing simultaneous enabling of user interrupts which overrides the previously disabled user interrupts to allow the processor to receive an interrupt request signal. The interrupt request signal is received before the read function of the predetermined register has completed.

Abstract: The present invention relates to a method and apparatus for directing causes of non-maskable interrupts. The apparatus determines whether a computer system is designed to handle an alternative interrupt such as a SCI interrupt. If the system is capable of handling alternative interrupts, forwarding circuitry forwards the causes of non-maskable interrupts to an alternative interrupt handler. If the system is not capable of handling alternative interrupts, the apparatus forwards the cause of non-maskable interrupts to a NMI handler.

Abstract: A method and system for dynamic creation of APIC tables under the ACPI specification using existing APIC tables under the MP specification in a multi-processor computer. The method of the present invention provides for the dynamic creation of APIC entries in a computer memory, and includes the steps of: scanning the memory for an MP APIC header, reading MP APIC entries from a location in the memory indicated by the MP APIC header, building ACPI APIC entries in the memory from at least a portion of the MP APIC entries read, and updating an ACPI APIC header in the memory after the ACPI APIC entries have been built.

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods.

Abstract: A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that high priority system management interrupts can be serviced without waiting for lower priority system management interrupts to be serviced completely. In particular, the method includes executing a first SMI handler routine in response to receiving a first SMI from a first SM requester. In response to receiving a second SMI asserted by a second SM requester, the method determines whether the second SMI request has been assigned a higher priority than the first SMI request. If so, then the method interrupts executing the first SMI handler routine and executes a second SMI handler routine corresponding to the second SMI request. Otherwise, the method completes executing the first SMI handler routine and then executes the second SMI handler routine.

Abstract: A method and apparatus for reducing interrupt density in a computer system. One or more interrupt events received at a first device are stored in a memory and an interrupt is issued from the first device to a second device attached to the first device upon an occurrence of a first predefined event, wherein the second device retrieves the stored interrupt events from the memory and processes the retrieved interrupt events in response to the issued interrupt. Thereafter, an interrupt is issued for every interrupt event from the first device to the second device after the occurrence of the first predefined event until an occurrence of a second predefined event. After the occurrence of the second predefined event, the interrupt events received at a first device are again stored in the memory without issuing an interrupt from the first device to the second device. Finally, an interrupt is issued from the first device to the second device upon another occurrence of the first predefined event.

Abstract: An interrupt management system that enables a user to handle interrupt events either in a real time mode of operation, or in a batch mode of operation. In the real time mode, an interrupt request signal is asserted in response to each interrupt event. In the batch mode, an interrupt request signal is delayed until a predetermined number of interrupt events is detected, or until a predetermined time interval has elapsed since the last interrupt event is captured. In response to an interrupt event, the corresponding bit in an interrupt register is set to an active state. A control interrupt bit is provided in an interrupt control register for each interrupt to enable the activation of an interrupt request pin in response to the interrupt event. A batch enable bit is provided in a batch register for each interrupt event to enable the batching of the interrupt event.

Abstract: A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Abstract: A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates interrupts after a delay determined by an interrupt deferral mechanism, which includes one or more timers and/or one or more counters. Interrupts are generated, for example, after a predetermined time has elapsed after a DMA completion or after a certain number of packets are counted.

Abstract: A method, system, and associated program code and data structures are provided for a message processing system in which messages are passed from source nodes to destination nodes. Notification of the arrival of the messages at the destination nodes can be effected by programmable source initiated interrupts or destination initiated interrupts. The source initiated interrupts are implemented as set fields embedded in the message packets sent from a source node to a destination node and trigger the requisite interrupt at the destination node upon message arrival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers which are allocated at the destination node for incoming messages from the source node. Standard incoming message queue polling, as well as interrupt enabling and disabling functions are also provided, which together allow the system to selectively invoke interrupt or alternative strategies to notify destination nodes of arriving messages.

Abstract: A method, system, and associated program code and data structures are provided for a message processing system in which messages are passed from source nodes to destination nodes. Notification of the arrival of the messages at the destination nodes can be effected by programmable source initiated interrupts or destination initiated interrupts. The source initiated interrupts are implemented as set fields embedded in the message packets sent from a source node to a destination node and trigger the requisite interrupt at the destination node upon message arrival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers which are allocated at the destination node for incoming messages from the source node. Standard incoming message queue polling, as well as interrupt enabling and disabling functions are also provided, which together allow the system to selectively invoke interrupt or alternative strategies to notify destination nodes of arriving messages.

Abstract: A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers map each of a plurality of interrupts to an appropriate one of a second plurality of registers and indicate which interrupts are masked. The second plurality of registers are arranged in a predetermined priority and each contains the starting address of an appropriate interrupt service routine for the corresponding interrupt. The interrupt signals are mapped to the outputs of a plurality of logical "OR" gates according to the contents of the first plurality of registers by a plurality of de-multiplexers coupled to the inputs of the plurality of logical "OR" gates. Each logical "OR" gate corresponds to one of the second plurality of registers.

Abstract: A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.

Abstract: A method, apparatus, and article of manufacture for generating signals using a Universal Serial Bus (USB) host controller and USB keyboard. Data generated by the keyboard is marked as being used with an operating system which responds to keyboard generated interrupts and which reads keyboard data stored in a register. The marked data is detected after it is received from the keyboard and is transferred to a register. An interrupt to a central processing unit (CPU) is then generated in response to the marked data being transferred to the register.

Abstract: An interrupt program selection system which is provided with a central processing unit executing various types of control programs stored in a storage unit and which accepts an interrupt processing request from an external unit and selects from the storage unit an interrupt program corresponding to the accepted request comprises an interrupt request controller, a conversion table, and a jump code generating module. The interrupt request controller selects a highest-priority processing request from a plurality of interrupt processing requests. The conversion table contains start addresses of a plurality of interrupt programs corresponding to a plurality of interrupt processing requests. The jump code generating module generates a jump code which may be executed directly by the central processing unit as an instruction based on the start address of the interrupt program corresponding to the accepted interrupt processing request, and places the generated code in a memory space in the storage unit.

Abstract: A system and an associated method which provides a dual interrupt mechanism to designate the occurrence and termination of an event. In a computer system employing redundant components, upon removal of a defective redundant unit within the computer system, a first interrupt is generated to signal the absence of the unit. Polling or other system monitoring of the status of the absent unit is masked or disabled, thereby eliminating unnecessary polling for the missing unit. Upon replacement of the unit, a second interrupt alerts the computer system of the event termination and cancels the polling mask.

Abstract: In executing indivisible operations to be executed without being interrupted, pseudo-store instructions PST which do not perform data writing are used to perform a check for the presence or absence in a memory of pages necessary for execution of the indivisible operations. In the event of absence of the necessary pages, the necessary pages are pre-stored in the memory. This prevents the generation of page fault interruptions during the execution of an indivisible operation, thereby enabling the indivisible operation to be implemented on a software basis. A disable interrupt instruction is executed prior to the execution of the indivisible operation as required, and data indicating an address of the disable interrupt instruction is preserved in order to return to the disable interrupt instruction.

Abstract: Each of microcodes 1 has an interrupt prohibit bit 10 that specifies acceptance or nonacceptance of an interrupt request. Upon occurrence of an interrupt request, a processor refers to a value set in the interrupt prohibit bit 10 of the microcode 1 being currently executed. When "0" is set to the interrupt prohibit bit 10, the processor accepts the interrupt request, and when "1" is set to the interrupt prohibit bit 10, the processor rejects the interrupt request and starts executing a succeeding microcode. This allows the processor to safely execute certain instructions without interruption, as indicated by the interrupt prohibit bit 10 contained in the microcode 1 being currently executed.

Abstract: To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.

Abstract: A multiprocessor system and method for minimizing perturbations while monitoring parallel applications. Perturbations due to monitoring the application are minimized by synchronizing all the nodes within the system to a very accurate global time clock such that all the nodes running the application stop and restart running the application at the same time. Within the time period bounded by the stop and restart time, all the performance monitoring data is transferred from performance monitoring data buffers to a secondary memory.

Abstract: The hardware semaphore generates an interrupt signal upon a change in ownership status of a shared resource. In particular, the semaphore apparatus generates an interrupt signal when a requesting device or process relinquishes control of a shared resource. By generating a hardware interrupt when a shared resource becomes available, devices or processes that require access to the resource need not repeatedly poll the hardware semaphore to determine if the resource associated with the semaphore is available. In a preferred embodiment, the hardware semaphore apparatus employs a pair of cross-coupled NOR gates for arbitrating between two requesting devices. A pair of rising edge detectors and flip-flops are connected to outputs of the NOR gates for generating the interrupt signal. Other exemplary and illustrative embodiments are described as well.

Abstract: An apparatus for a distributed system having a plurality of nodes and a switch network for passing messages between nodes, each message being sent from a source node to a target node. Each node is connected to the switch network by an adapter having a count register for adding the value of the packets in messages received by the adapter to the value in the count register and a threshold register for containing a desired threshold value. An interrupt generator generates interrupts when the value in the count register is equal to or greater than the value in the threshold register. The value in the threshold register may be changed under program control to enable or disable interrupts.

Abstract: A method and apparatus for processing interrupts for a plurality of components connected to and sharing an interrupt line in a data processing system in which interrupts are level sensitive interrupts. The components are connected to the interrupt line by interrupt connections, such as a pin. An interrupt is detected when the interrupt line is in a first state, while an interrupt is absent when the interrupt line is in a second state. Other interrupts cannot be processed while the interrupt line is in a first state. In response to detecting one or more interrupts, the connection associated with the component, for which one or more interrupts are generated, is disabled until all of the interrupts are processed. Disabling the interrupt connection allows the interrupt line to return to the first state and for additional interrupts for other components connected to the interrupt line to be detected and processed.

Abstract: A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt signals. This protection circuit comprises a controllable interrupt signal passage circuit which, depending on an output signal of a control signal source, can be controlled to a state permitting the passage of the non-maskable interrupt signal or to a state blocking said signal. The control signal source comprises a clock counter with overflow resetting function, by means of which program step clock pulses can be counted starting from a predetermined initial counting value until a predetermined overflow counting value is reached. The control signal source comprises furthermore an interrupt signal counter the counting value of which can be increased by each non-maskable interrupt event and decreased each time the overflow counting value of the clock counter is reached.

Abstract: A general purpose computer operating system is run using a real time operating system. A real time operating system is provided for running real time tasks. A general purpose operating system is provided as one of the real time tasks. The general purpose operating system is preempted as needed for the real time tasks and is prevented from blocking preemption of the non-real time tasks.

Abstract: An interrupt scheme for a data processor includes an enable field for a non-maskable interrupt (NMI). The field is automatically cleared by the data processor when it services the highest priority interrupt, a RESET. The user can set the field to enable a subsequent NMI but cannot himself clear the NMI. This strategy prevents an NMI from interrupting a RESET service routine.