Abstract: In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is configured to initiate the virtual interrupt responsive to the interrupt state. In another embodiment, a method comprises storing an interrupt state describing a virtual interrupt in a storage area allocated to a guest. A processor initiates the virtual interrupt subsequent to initiating execution of the guest, responsive to the interrupt state. In still another embodiment, a computer accessible medium stores a plurality of instructions comprising instructions which, when executed on a processor in response to a physical interrupt: determine a guest into which a virtual interrupt corresponding to the physical interrupt is to be injected; and store an interrupt state describing the virtual interrupt in a storage area allocated to the guest.

Abstract: A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.

Abstract: A system-event core for monitoring system events in a cellular computer system within a parent computer system is provided. The system-event core comprises: a control register block for each cell computer system configured to mask one or more system events and configurable to be masked by a system-event manager, an input/output block operable to communicate with a computer bus, a register block operable to store data about system events, and interrupt generation logic operable to control interrupts for the cellular computer system.

Abstract: A task management method is provided for preventing a task that can cause a failure in a system from being aborted during a manipulation of the task. A program execution means transmits information on an attribute of a function under execution, and queries about the execution of an abort for a task to which the function belongs. The task execution determination means determines whether the abort should be executed based on the attribute of the function under execution. A task attribute recognition means stores the attribute of the function under execution in a task attribute information storage means, and returns the stored attribute of the function in response to a query about the attribute of the function from the task execution determination means.

Abstract: A method is provided of managing hardware triggered hotplug operations of one or more input/output (I/O) cards of a computer system. The method comprises receiving hardware triggers, each of which relates to a hotplug operation to be carried out on an I/O card associated with a card slot, placing the hardware triggers in a queue, and processing the queue of hardware triggers. The method further comprises processing one or more of said hardware triggers. This comprises analysing a hardware trigger to determine the card slot to which said hardware trigger relates, and consulting a hotplug operation policy to determine whether hotplug operations are enabled for said card slot. If hotplug operations are not enabled for said card slot, this further comprises ignoring said hardware trigger, and if hotplug operations are enabled for said card slot, this further comprise querying said slot to determine whether it contains a card.

Abstract: An apparatus and method for dynamic suppression of spurious interrupts in a computer system. More specifically, there is provided a method that comprises providing a look-up table comprising source IDs and corresponding time delays for each of a plurality of interrupt lines, monitoring each of the plurality of interrupt lines, and updating the time delays in the look-up table based on the monitoring of the interrupt lines, and a system for implementing the method.

Abstract: Tools and methods are described herein for discovering race condition errors in a software program. The errors are discovered by deliberately causing a processor executing the test program to switch threads at intervals other than normally scheduled by an operating system. The thread switching is caused upon occurrence of selected events. The intervals may be selected automatically or with user input. Furthermore, thread switching may be caused during conditions more likely to cause race condition errors. For example, thread switches may be caused between threads that share control of a memory device or while the processor is executing instructions related to synchronization tools (e.g. locks, mutex, etc.).

Abstract: A method is disclosed. The method includes receiving real-time data at a personal computer implementing a general purpose operating system, generating a real-time event at the personal computer and determining whether the real-time event has a higher priority than a first event being processed at the personal computer. If the real-time event has a higher priority than the first event being processed, the real-time event is processed.

Abstract: An interrupt controller enables multiple CPUs to control access to an increased number of interrupts. Each of a plurality of CPUs is able to block interrupts written to the interrupt controller at multiple levels. First, each CPU is able to block interrupts at the interrupt level. In other words, a CPU is able to block one or more individual interrupt requests from I/O devices from being sent to that CPU. Second, each CPU is able to block interrupts from one or more entire MSI interrupt registers from being sent to that CPU. The interrupt controller is fully programmable by the CPUs in software and thus is very flexible, as the priority of interrupts can be controlled by the CPUs according to the requirements of the CPUs based on the various operational demands of the CPUs. Any of 512 possible interrupt requests are capable of being routed to any particular one CPU, any combination of the CPUs or to all of the CPUs.

Abstract: An interrupt controlling method is provided that is capable of executing an interrupt process while avoiding slowing-down in execution speed of a task process. When an interrupt request occurs while a task processing program is being executed, the task processing program is suspended and execution of an interrupt handler is started. By the interrupt handler, a plurality of breakpoints are set in an interrupt process-enabled area (R2). Execution of the resumed task processing program soon reaches one of the plurality of breakpoints. Then, the microprocessor (1) suspends the execution of the task processing program and starts execution of a breakpoint handler. By the breakpoint handler, the interrupt process is executed, and thereafter, the settings of the breakpoints are cleared.

Abstract: A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Abstract: A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor automatically diverts the exception to the dedicated exception registers using a dedicated vector. The dedicated vector and exception registers may be reserved for high priority, i.e., critical, exceptions. Because the exception registers are automatically activated for fast exceptions, there is no need to determine the priority of the exception. Further, high priority interrupts and high priority operating system calls (traps) may have different dedicated vectors and the set of exception registers may have a portion allocated for servicing interrupts and another portion allocated for servicing operating system calls. With the use of a dedicated vector or dedicated vectors, there is no need for software to decode the fast exception.

Abstract: A method of controlling a secure execution mode-capable processor includes allowing a plurality of interrupts to interrupt the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a non-secure execution mode. The method also includes disabling the plurality of interrupts from interrupting the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a secure execution mode.

Abstract: Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

Abstract: An apparatus and method for detecting and controlling interrupt storms in a computer system. More specifically, there is provided a method that comprises detecting whether or not a device is producing an interrupt storm, and if the device is producing an interrupt storm, disabling the interrupt being generated by the device, and a system for implementing the method.

Abstract: A method for generating an interrupt signal for a media access controller (MAC) in communication with a computer host and an external network is disclosed. The method includes steps of asserting an interrupt signal to the computer host when at least one data packet is to be transferred from a memory, performing a corresponding interrupt service of the computer host in response to the interrupt signal for freeing a memory space occupied by the data packet being transferred from the memory, and deasserting the interrupt signal until the corresponding interrupt service is finished and a predetermined delay period is up. In addition, a media access controller (MAC) is also disclosed. The MAC includes a timer for counting a predetermined delay period after the interrupt service has been finished.

Abstract: A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is halted. The standby mode is exited by input of an interrupt. The microcontroller also has a control circuit that, by storing the next few program instructions internally before placing the memory in standby, or by delaying the interrupt signal, provides extra time for memory operation to stabilize on exit from the standby mode. Malfunctions on recovery from standby are thereby prevented, and the microcontroller can conserve power by placing the memory in a deep standby mode with a comparatively long recovery time.

Abstract: A method for processing an interrupt message in a system having a plurality of processors arranged into at least two partitions. The interrupt message is decoded to identify an interrupt source. If the interrupt source is not in an interrupt set, the interrupt is dropped. If the interrupt source is in a local partition, the interrupt is delivered. If the interrupt source is in the interrupt set and not in the local partition, the interrupt is processed in accordance with at least one of a target enable register and a vector enable register.

Abstract: In the present invention, a computer in which a plurality of programs are executed under a management of an Operation System having a memory management mechanism includes a unit for ensuring atomicity of a first user process without requiring a dedicated CPU instruction. The unit for ensuring atomicity includes a unit for detecting an interrupt by a second user process, a unit for canceling the first user process by utilizing a memory protection function possessed by said Operating System, and a unit for executing an operation of the first user process again.

Abstract: Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform).

Abstract: A system and method for implementing hardware event driven soft real-time interrupts on a serial bus. In one embodiment, the serial bus comprises a universal serial bus. One embodiment of the presently described system includes a client device coupled to a host device. In one embodiment, the host places the client device in an interrupt mode by causing the client device to enter a suspend state. While in the interrupt mode, the client device sends an interrupt request signal to indicate it has interrupt data. In one embodiment, the host device indicates to the client device to enter the interrupt mode by sending a set interrupt mode signal. In response, the client device enters the interrupt mode and sends an interrupt request signal to the host to indicate it has interrupt data.

Abstract: An interrupt generating register within an interrupt control circuit is mapped in a memory space of the node. By issuing a store command to the memory space, the node transmits the store command to an address of the interrupt generating register via a network. An interrupt control circuit receives the store command, generates an interrupt command, and transmits the generated interrupt command to a CPU module.

Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.

Abstract: An apparatus is described which is distinguished by the fact that the apparatus does not output an interrupt request until after a plurality of interrupt requests have been received. The apparatus outputs a plurality of interrupt requests in response to an interrupt request being received, and/or the apparatus waits to output an interrupt request until it can be assumed that the operation to be initiated by a previously output interrupt request has been executed. As a result, it can be used extremely flexibly.

Abstract: The invention relates to the processing of state information such as interrupt status in a hierarchical network of nodes having a tree configuration. There is a root node at the top of the hierarchy, one or more intermediate nodes, and a plurality of leaf nodes at the bottom of the hierarchy. Each leaf node is linked to the root node by zero, one or more intermediate nodes. Each leaf node maintains information about one or more interrupt states, and each intermediate node maintains information derived from the interrupt states of leaf nodes below it in the hierarchy. This interrupt information is then processed by navigating from the root node to a first leaf node having at least one set interrupt state which is then masked out. The status of any intermediate nodes between this first leaf node and the root node is then updated if appropriate to reflect the fact that the particular interrupt state at the first leaf node is now masked out.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value. The Latency value may be increased as the processor's workload increases.

Abstract: A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.

Abstract: The present invention provides for a method and system for allowing non-trusted partitions in large scale computer system to safely interrupt a processor without the risk of corruption or loss of interconnect bandwidth, and without the need for inefficient hardwiring. In operation code preferably located outside of the central processor, interrupts coming from outside the partition into specific addresses for determination of allowability into the partition.

Abstract: A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.

Abstract: A method for operating automation control equipment applications ensures uninterrupted execution of a control application, at least during specific time periods, but such that the control application does not have the access privileges of a device driver. The operating system is configured for preventing calling of the processor commands from the control application, the processor communicating with the controlled automation equipment via a programmable bus interface. An embodiment of the method comprises the steps of performing read and write access of the control application to the bus interface directly and without routines of the operating system or device driver, and suspending processing of hardware interrupt calls of the processor during a preselected time period.

Abstract: A method and system for selectively enabling wake events in software of a computer system to overcome problems arising when hardware devices fail to clear a wake signal. The operating system manages wake events, and also distinguishes between events that are exclusively wake events, exclusively run-time events, and shared wake and run-time events. At boot time, the ACPI driver examines system tables provided by firmware to determine which GPEs are associated with wake-up events, either exclusively or shared with run-time events. These wake event associations are tracked and managed differently from events received on other hardware register pins. When the operating system receives events in a GPE Status hardware register that is enabled in a counterpart Enable register, the operating system runs an associated GPE method. When the GPE method has completed, the operating system selectively determines whether the event needs to be re-enabled.

Abstract: A method and apparatus are described by which interrupts from a source may be processed at a dynamically selectable level of priority. A system that has at least two different interrupt request connections, and that responds to interrupts asserted on the different connections by processing interrupts at associated and corresponding different priority levels, is configured so that an interrupt asserted by a particular interrupt source is coupled to a particular one of the plurality of request connections that has been selected under software control. Selective coupling of interrupt source to interrupt request connection may be effected by providing a set of control bits associated with each particular interrupt source, the set consisting, for example, of one interrupt mask bit for each of the different selectable priorities. Control may optionally be provided to preclude simultaneous coupling of an interrupt source to incompatible interrupt request connections.

Abstract: An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction.

Abstract: An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing section (3). This signal is input as an interruption request signal to a CPU (1). Consequently, the CPU (1) can execute an interruption processing in a cycle which is plural times as great as the cycle of the output pulse. By the interruption processing, the number of pulses to be output is controlled.

Abstract: Disclosed herein is a method and apparatus for handling an asynchronous interrupt while emulating software so that the system is in a known state when the interrupt is handled. The method includes suspending the asynchronous interrupt so that it remains pending without interrupting software execution when it arrives, then synchronizing delivery of the interrupt to an instruction by issuing an exception. The instructions which trigger exceptions are inserted in the native code at locations corresponding to original instruction boundaries.

Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface to suit the workload of the interface. An interrupt handler adjusts dynamic Packet and/or Latency values of the interface to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the interface's Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value.

Abstract: A data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined into a single interrupt signal by an interrupt controller. One of the data receiver-transmitters has an interrupt status register with bits indicating the logic levels of the interrupt signals from each of the data receiver-transmitters. A host device that receives the interrupt signal from the interrupt controller can read the interrupt status register to determine which data receiver-transmitter caused the interrupt, then read the interrupt identification register of that data receiver-transmitter to identify the interrupt source, without having to search through the interrupt identification registers of other data receiver-transmitters.

Abstract: A unified interrupt handling system and method is provided for an embeddable processor having multiple interrupt types. An instruction is inserted into the first vector address that disables the second interrupt mode. At the second vector address, an other instruction is inserted that branches to a common interrupt dispatcher. The common interrupt dispatcher is provided with an interrupt routine that processes the interrupt, and then re-enables the second interrupt modes. Interrupt requests are then processed by the common interrupt dispatcher without interruption.

Abstract: A method is disclosed for handling interruptions, such as asynchronous interrupts, of a process using a system resource. The method determines whether a process is currently using a system resource. If a resource is being used and the system receives an interruption, then the method logs the interruption and delays accepting the interruption until after the process currently using the resource is completed. The method may be implemented in a system that controls access of processes to resources using semaphores that lock the resources while in use. The method determines whether a resource is currently in use by detecting a load and clear operation, indicating that a semaphore has locked the resource. The method delays acceptance of the interruption until either a branch command is executed, a store command is executed, a specified number of instructions are retired, or a specified number of clock cycles pass.

Abstract: Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, are stored by the interruption handler in a storage accessible by the operating system. The interruption handler calls the operating system at a predetermined interruption handling point thereof, for the operating system to handle the interruption. The handler then determines whether the operating system handled the interruption according to the recommendation.

Abstract: A flexible interrupt controller (28) that includes an interrupt force register (120) is presented. Hardware interrupts (102) that are presently asserted by their respective hardware sources are stored in an interrupt source register (110) included in the interrupt controller (28). An independent interrupt force register (120) stores currently pending software interrupts (104) which may be asserted through the execution of software routines by the central processing unit (CPU) (12) within the data processing system (10). In one embodiment, each bit location in the interrupt source register (110) has a corresponding bit location in the interrupt force register (120), and each bit in the interrupt force register (120) is logically OR-ed with the corresponding bit in the interrupt source register (110).

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debuts monitor mechanism.

Abstract: In one embodiment, a processor is arranged to handle events. The events handled by the processor have an assigned priority. When a first event is serviced, a first priority mask is generated based on the assigned priority of the first event. The priority mask indicates a set of serviceable events and a set of non-serviceable events and may be written to a priority register. When a second event is received, the priority mask is used to determine whether the second event should preempt the first event and be immediately serviced.

Abstract: There is disclosed an interface device which can prevent the freezing of an information processing system caused occupation of a system bus even when a wait signal outputted from the PC card is kept asserted. When the wait signal outputted from the PC card, is asserted, a timer portion 201 is activated. When the timer portion 201 detects that the wait signal is kept asserted for more than a predetermined period of time, it asserts a wait mask signal. Upon assertion of the wait mask signal, a mask portion 202 masks the wait signal from the PC card so that the wait signal to the CPU is negated even when the wait signal is kept asserted. Further, when the timer portion 201 asserts the wait mask signal, an interrupt control block/card status register 210 asserts an interrupt signal to the CPU.

Abstract: An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, optimize interrupt-handling by combining the activities of acknowledging and disabling the interrupt. In one embodiment, the apparatus may include an interrupt cause register coupled to an interrupt disabling register and an interrupt mask register. The system may include a processor coupled to an interrupt cause register using a bus, along with an interrupt disabling register coupled to an interrupt mask register and the interrupt disabling register. The method may include reading an interrupt cause register in response to receiving an interrupt, and transferring a mask value stored in an interrupt disabling register directly to an interrupt mask register so as to disable receiving further interrupts from the interrupt source.

Abstract: An interrupt management section 103 for holding interrupt acceptance possibility states prepared for each of interrupt sources 121 to 122, and an interrupt mask cancellation section 104 for controlling interrupt enabling in interrupt processing tasks 127, are provided, and a multiple interruption control section 109 is provided for performing interrupt mask update control using sections 103 and 104 within an interrupt handler 101.

Abstract: A system operable to perform scaleable arbitration and prioritization of multiple interrupts. The present invention presents a solution that is theoretically indefinitely scaleable to accommodate any number of interrupt sources. The invention provides for orthogonal scalability of interrupt sources—a feature absolutely non-existent in the prior art. The propagation time of an interrupt within the system is predictable and nearly independent of the number of priority levels or the number of interrupt sources. In addition, the invention presents a novel solution to support multiple interrupt sources having a common priority level. The solution is scaleable in two dimensions, namely, modularity in the number of interrupt sources that can be supported and scaleable in the number of priority levels that can be supported. The solution significantly reduces the deleterious effects of hardware latency in slowing interrupt processing.

Abstract: A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.