Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: A method for achieving low overhead for operating system (“OS”) interrupts is described. In a preferred embodiment, when an interrupt occurs, a lightweight interrupt handler is used to acknowledge that the interrupt occurred, prevent the CPU and the OS from fully servicing the interrupt until a designated future time, set a CPU flag indicating that the interrupt has been received, and return from the lightweight interrupt handler. In this manner, the interrupt is partially acknowledged by the CPU and the OS, but the driver that caused the interrupt is still awaiting service. To achieve low latency, a heavyweight (“non-deferrable”) time-based interrupt that flushes all deferred interrupts is scheduled to occur within a specified time. At a later time, when drivers would normally be polled for work, the CPU flag is checked to see if there is interrupt work.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt if no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: A service request system for a subsystem of a computer including a processor, a driver, and inhibit logic. The inhibit logic detects requests for service by the subsystem and asserts an interrupt unless the driver is executing and servicing the subsystem. The driver is executed by the processor in response to the interrupt to service the subsystem, where the driver controls the inhibit logic to prevent interrupts associated with the subsystem from being asserted while the driver is being executed by the processor. In this manner, redundant interrupts or service requests initiated by the subsystem are eliminated. The service request system may include an activity indicator that indicates whether the driver is being executed. Th inhibit logic asserts an interrupt in response to a service request from the subsystem unless the activity indicator indicates that the driver is in control of the processor.

Abstract: An interrupt controller and an interrupt handling method thereof are described. When there is an interrupt, a priority level of an interrupt source is determined and a corresponding branch instruction is generated and inputted to a CPU. The CPU then directly branches off to a position containing an interrupt service routine addressed by the inputted branch instruction instead of a general CPU instruction, similar to interrupt handling in CISCs with vectored interrupts. Therefore, interrupt handling time is reduced.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: An interrupt request controller for processing a plurality of interrupt logic signals. The controller includes: a programmable bit masking section fed by the interrupt logic signals, adapted to mask selected ones of the interrupt signals; a interrupt priority section fed by the programmable mask section for coupling unmasked ones of the interrupt signals to a plurality of outputs selectively in accordance with a predetermined priority criteria. The request controller includes: a programmable section fed by the interrupt signals, for selecting assertion sense and/or assertion type of each one of the interrupt signals. The programmable section stores a bit for each one of the interrupt logic signals representative of whether the logic state of the interrupt logic signal should be, or should not be, inverted and for producing a corresponding output logic interrupt signal in accordance therewith.

Abstract: A system and method is disclosed for debugging of a hardware board that includes a processor with only a single level of interrupts that are either all enabled or all disabled. The processor does not implement nonmaskable interrupts. The processor on the board contains a machine check exception (MCP) input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the hardware board. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the interrupt processor are disabled. A processor-to-bus bridge connected to the processor on the hardware board contains a critical interrupt register. Test equipment connected to the processor-to-bus bridge sets a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo interrupt debug request has occurred.

Abstract: A computer executable digital video rendering restoration method is disclosed. Through setting a saving interval, data of states during the rendering process of digital videos are recorded periodically. When the rendering process is abnormally interrupted, the state data in the record file can be immediately used to restore the digital video before the last recording so that the user can continue the digital video rendering.

Abstract: Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus.

Abstract: A memory rewriting apparatus is provided which does not require ROMs other than a flash ROM while enabling use of interrupts, and in which a program for switching between a normal operation and a program rewriting operation is not complicated. In the memory rewriting apparatus of the present invention, a CPU 10 includes a port output terminal PT and selection output terminals CS0, CS1 and CS2. A memory map switching circuit 20 is provided which is connected with those output terminals, a flash ROM and a RAM. The CPU sets the port output terminal to an “L” level in a normal operation, and to an “H” level at the time of rewriting a flash ROM program, so that a memory map takes a condition as shown in FIG. 2(a) in the normal operation, whereas it takes another condition as shown in FIG. 2(c) in the program rewriting operation.

Abstract: A system-event core for monitoring system events in a cellular computer system within a parent computer system is provided. The system-event core comprises: a control register block for each cell computer system configured to mask one or more system events and configurable to be masked by a system-event manager, an input/output block operable to communicate with a computer bus, a register block operable to store data about system events, and interrupt generation logic operable to control interrupts for the cellular computer system.

Abstract: Disclosed is a Software Sanity Monitor for automatically detecting and remedying software lock-up conditions without user intervention. Users often refer to these conditions as “hangs” or “forever loops”. Although the Software Sanity Monitor uses the operating software's information, it is designed to execute independent of the operating system software; thereby, eliminating reliance on a “sane” operating system. If a “hang” condition is detected, the Software Sanity Monitor will automatically restart the system after logging the failure and, optionally, notify the user or host system.

Abstract: A snapshot arbiter system for servicing multiple interrupt requests for a central processing unit (CPU) in a digital processor system, and for providing interrupts to the CPU corresponding to the interrupt requests. The system includes a synchronizer adapted to synchronize interrupt requests to a clock as they are received, and an interrupt masker adapted to receive a set of indicators identifying interrupt requests to be masked and to output active indicators that are a set of active interrupt request values corresponding to received interrupt requests that are not masked. Also included is a priority encoder block adapted to receive a set of priority values for respective interrupt requests and to provide as an output priority indicators that are a set of codes representing the priority values. A snapshot enable block is included, adapted to store enable indictors that are a set of bits representing currently enabled interrupt requests, and output those bits as enable bits.

Abstract: The microcomputer comprises: a CPU, a DRAM installed within the microcomputer, a non-volatile memory storing a program data therein, an interface commonly used among various circuits within the microcomputer, a system clock generating circuit, which generates clock signals, and is also capable of suspending and regenerating the clock signals, respectively in response to a system clock stop signal and a system clock generation signal, a peripheral circuit which is capable of outputting an interrupt signal requesting the system clock generation to the CPU, and a control circuit which re-transmits the program data from the non-volatile memory to the DRAM in response to a re-initialize request signal output from the CPU, and also outputs an access prohibition, signal for prohibiting the access to the data stored in the DRAM and an access prohibition release signal for releasing the prohibition of access.

Abstract: An interrupt handler is provided for a real-time control system that prevents interrupts which occur asynchronously with respect to control tasks from upsetting guarantees of timely execution of the control tasks. For interrupts associated with the communication of messages between portions of a control task over the distributed system, the interrupts are converted to proxy tasks that may be scheduled like any task in a multitasked-operated system. More generally, interrupts may be assigned to a predetermined interrupt window being a portion of the total processing bandwidth of the processor. In pre-allocating the processor bandwidth to the control tasks, this interrupt window may be subtracted out thereby guaranteeing adequate bandwidth for both interrupt processing and user tasks.

Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.

Abstract: The invention relates to a method of executing a real-time task by a digital signal processor using a cache memory, an overall duration being allocated for executing said task and any interrupts coming from peripherals associated with the processor, wherein the overall duration is subdivided into a plurality of time intervals comprising at least one masked period during which said task is executed and interrupts are made to wait and are grouped together, and at least one non-masked period during which said task is suspended and the group of interrupts is executed. The masked periods and the non-masked periods are defined by a hardware mechanism including a timer.

Abstract: A method and apparatus are described which allow for greater control of interrupt generation to a processor or the like. In one embodiment, a priority selection device is provided which allows a processor or other devices to set the relative priorities among different interrupt requests. The priority information may be dynamic in that it can be modified at other times (e.g., based on the needs of the computer system). A priority resolution device and mask logic device determine which of the generated interrupt requests is of the highest priority and generates an interrupt to the processor to service that high-priority interrupt. In one embodiment, when a processor is servicing an interrupt and a higher priority interrupt is generated, the processor nests the servicing of the higher-priority interrupt in the servicing of the current interrupt.

Abstract: An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, optimize interrupt-handling by combining the activities of acknowledging and disabling the interrupt. In one embodiment, the apparatus may include an interrupt cause register coupled to an interrupt disabling register and an interrupt mask register. The system may include a processor coupled to an interrupt cause register using a bus, along with an interrupt disabling register coupled to an interrupt mask register and the interrupt disabling register. The method may include reading an interrupt cause register in response to receiving an interrupt, and transferring a mask value stored in an interrupt disabling register directly to an interrupt mask register so as to disable receiving further interrupts from the interrupt source.

Abstract: An apparatus and method for controlling the number of interrupts a data transfer unit generates to a CPU is disclosed. A pacing unit is used to register attempted data transfers (events) from a data transfer unit to a CPU and compares this value to a user defined threshold limit. When the number of events reaches the threshold limit, an interrupt is generated to the CPU.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. The node controller also implements an interrupt arbitration scheme designed to choose among multiple eligible interrupt distribution units without using dedicated sideband signals on the bus.

Abstract: A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its scheme may be used for expanding the number of interrupts to be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The present invention can be used for optimizing the management of data within a shared bus with multiple masters, wherein a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. The architecture utilizes the high speed interrupt controller device having a circuitry which has a plurality of interrupt lines and may have one output line and a control code, located in the device interrupt handler.

Abstract: Translation of PCI level interrupts into packet based messages for edge event drive microprocessors includes, a bridge device receiving interrupts via an interrupt line from one or more PCI devices. The bridge device further sends an interrupt write packet to a CPU to launch the interrupt routine. The interrupt routine services the interrupt and the PCI device negates the interrupt line. At this point, the CPU generates a non-blocking write. This write causes the bridge to check the level of the PCI interrupt line. If the line is active with the interrupt, another write packet is sent, otherwise the interrupt line is negated and the blocking write is ignored. As a result, the present invention prevents an interrupt from a PCI device from being overlooked, from being missed, or from repeating the interrupt by a microprocessor.

Abstract: A technique for enhancing performance for code transitions of floating point and packed data modes, in which a tag incorrect (TINC) bit is used to indicate a potential fault condition when transitioning between the modes. When tags of a floating point/packed data registers are not at the expected value for the mode transition, the TINC bit is used to a substitute condition which prevents the generation of the fault condition.

Abstract: To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU. At the same time, the CPU sends a stack signal “STK” to the interrupt controller. In response to the stack signal “STK”, the interrupt controller temporarily transfers the interrupt mask level stored in the register into the RAM. When the CPU restarts the suspended interrupt processing, the CPU reads the PSR value and the PC value from the RAM while the CPU produces a return signal “RTN.” In response to the return signal “RTN”, the interrupt mask level is returned from the RAM to the register.

Abstract: An interrupt controller can execute a faster interrupt service routine after an occurrence of the interrupt by writing branch instructions upon initialization of the computer environment in advance of the actual interrupt. The interrupt controller includes an interrupt mask register that receives, and stores an interrupt on/off instruction from a CPU. An interrupt priority register receives and stores an interrupt priority instruction from the CPU. An interrupt mask circuit unit selectively receives and forwards an interrupt generating signal from peripheral devices in response to an interrupt on/off instruction from the interrupt mask register. A priority determining circuit unit receives the interrupt generating signals from the interrupt mask circuit unit, determines priorities of the interrupt signals in response to the interrupt priority instruction from the interrupt priority register, and forwards an interrupt priority signal to an interrupt terminal of the CPU.

Abstract: High-speed data streams are exchanged between two digital computing devices one or both of which lacks DMA. Data transfers are performed by the devices using High-Level Datalink Control (HDLC) frames. An initiating device indicates that it wishes to exchange data with the other device by sending an HDLC frame with data stream indentification and other information. The initial HDLC-frame is sufficiently short that at least an essential portion of the frame can be stored in a receive buffer of the interface circuitry. Although the receiving device may not receive the entire HDLC frame correctly because of the possibility of an overrun condition, enough information is preserved in the interface circuitry to complete the transaction. The responding device then proceeds to read or write data at high speed using a series of exchanges with the initiating device.

Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a masking circuit that masks the prefix mask data or CAM data provided to the comparison circuit, or masks the comparison result from the match line of a CAM cell. The mask override circuit effectively overrides the prefix mask data stored in the local mask cell. The mask override circuit performs the override function by negating the operation of the mask circuit such that no masking operation occurs when an exact match compare or invalidate function is performed by the ternary CAM device. For example, during an exact match operation, the CAM cells compare comparand data with unmasked CAM data and provide the compare results to CAM match lines.

Abstract: An asynchronous bus interface apparatus includes an external register, arbitrating section, internal register, and state management control section. The external register temporarily stores write data for a microprocessor in accordance with a write request signal sent from the microprocessor via an asynchronous bus. The arbitrating section generates an internal register write signal in synchronism with an operation clock from a macro circuit upon reception of the write request signal from the microprocessor. The internal register reads data output from the external register when the internal register write signal is input from the arbitrating section, temporarily stores the data, and outputs the stored data in synchronism with the operation clock from the macro circuit.

Abstract: An interrupt management system includes a first down-counter which decrements in value in response to a clock signal to zero. When the value of the down-counter is equal to zero the down-counter is reset to a predetermined value X and an interrupt request signal is produced. The interrupt management system also includes a second down-counter which decrements in value from a predetermined value Y, where Y>X, in response to the clock signal. The interrupt request signal is received by a processor which services the interrupt and generates an interrupt serviced signal. The interrupt serviced signal is received by a controller which also receive the value of the second down-counter. Using the received value from the second down-counter, the controller can determine if an interrupt request has been missed and also determine the latency period for servicing an interrupt request.

Abstract: When a request for reception of radio signals is delivered by wireless communication section 3, subordinate processing portion 12 fetches programs necessary for reception of radio data from external memory 2 and stores them into command cache memory 13. At this instant, to prevent data stored in command cache memory 13 from being altered by other interrupt requests, the system instructs interrupt controller 16 to mask all interrupt requests except urgent ones. Through this arrangement it is possible to reduce noise during execution of a specific processing, particularly during reception of data.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: A write register access circuit 201 comprises data input terminals 1e01˜1e32, 32 pieces of first-stage flip-flops 1a01˜1a32, 16 pieces of second-stage flip-flops 1b01˜1b16 connected to the first-stage flip-flops 1a01˜1a16, an OR gate 1g, a flip-flop 1h, a NAND gate 11, 16 pieces of data selector circuits 1c01˜1c16, 32 pieces of gate circuits 1d01˜1d32, and 32 pieces of data output terminals 1f01˜1f32, and the write register access circuit 201 is connected to a CPU circuit 215 through an interruption request circuit Z. Therefore, when the write register access circuit 201 is included in an LSI, the write register access circuit 201 enables parallel processing between the CPU and the LSI without necessity of matching the instruction word length of the CPU and the bus width of the LSI, providing an internal bus width changing switch, and dealing with the problem at the software end of the CPU. Further, data transfer rate is increased.

Abstract: A hardware-implemented interrupt handler external to a processor handles interrupts destined for the processor. The interrupt handler has a programmable prioritized interrupt array with programmable registers that identify priority levels and handling processes for handling one or more interrupts. The interrupt handler also has an interrupt scanning state machine that scans the prioritized interrupt following receipt of an interrupt to extract the priority level and handling process associated with the interrupt. The interrupt handler is designed to handle interrupts in significantly less time than software implementations, thereby making the handler favorable for real time systems.

Abstract: Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.

Abstract: A method includes detecting a first event occurrence for a first thread being processed within a multithreaded processor. Responsive to the detection of this first event occurrence, a second thread being processed within the multithreaded processor is monitored to detect a clearing point for this second thread. Responsive to the detection of a clearing point for the second thread, a functional unit within the multithreaded processor is cleared of data for both the first and the second threads.

Abstract: In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.

Abstract: A method of securing a boot process for a computer system enables a processor to boot from a location identified by a boot vector. The method includes the step of disabling masking of a maskable address line in response to a processor initialization event. In one embodiment, an apparatus includes a processor coupled to a memory by at least one maskable address line wherein the memory is storing a first initialization instruction. The apparatus includes a mask control wherein the mask control disables masking of the maskable address line before the processor attempts to access the first initialization instruction in response to an initialization event. In one embodiment a processor chipset gates a first address mask control with an inhibit bit to generate a second address mask control. The second address mask control is independent of the first address mask control when the inhibit bit is set to a first value.

Abstract: An interrupt routing mechanism implemented in a host chipset to eliminate the need for the general purpose I/O pins, special software and external logic devices to steer particular interrupts from a non-legacy Peripheral Component Interconnect (PCI) bus to an external interrupt controller. Such an interrupt routing mechanism may be implemented by a series of logic gates such as OR gates and AND gates for combining all interrupts from a non-legacy PCI bus to produce an output boot interrupt to an external interrupt controller, and alternatively, implemented by a series of AND gates for combining all interrupts from a non-legacy PCI bus and a switch for forwarding an output boot interrupt to an external interrupt controller in accordance with a disable bit used for the steering function.

Abstract: A method and apparatus for controlling power management state transitions between two devices, e.g., a processor and a bus bridge, that are connected through a clock forwarded interface bus in a computer system. The bus bridge is configured to coordinate disconnection of the processor from the interface. Particularly, the bus bridge may use a fist signal to indicate whether or not the processor is to be disconnected from the interface (e.g. a CONNECT signal) and the processor may use a second signal to indicate whether or not the processor is to be disconnected from the interface (e.g. a PROCREADY signal). The processor is disconnected from the interface responsive to both the first signal and the second signal indicating that the processor is to be disconnected. The signals may also be used to reconnect the processor to the interface.

Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

Abstract: The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN).

Abstract: The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified. The external event is asserted when there is a match between the target instruction address and a pipeline instruction pointer corresponding to a second pipeline stage. The second pipeline stage is earlier than the first pipeline stage in the pipeline chain. The external event is unmasked via a delivery path between a signal representing the asserted external event and the first pipeline stage.