Abstract: An information handling system includes a processor operable to provide a branch trace message, and an embedded controller coupled to the processor via a primary interface and via a management interface. The embedded controller receives a management transaction from the processor via the primary interface. In response to receiving the management transaction, the embedded controller requests the branch trace message via the management interface and determines if the processor is operating in a system management mode based upon the branch trace message.

Abstract: A management server includes a user management database in which mobile terminal identification information on the mobile terminal and working machine identification information on a sold working machine are registered in association with each other, a user registration determination unit adapted to determine whether or not the mobile terminal and the working machine are registered in association with each other on the basis of the mobile terminal identification information and the working machine identification information outputted from the mobile terminal and the mobile terminal identification information and the working machine identification information stored in the user management database, and an authorization information output unit adapted to output an authorization key necessary for wireless communication between the mobile terminal and the working machine in the case where the user registration determination unit determines that the mobile terminal and the working machine are registered in associa

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract: Systems and methods for intelligent language models that can be used across multiple devices are provided. Some embodiments provide for a client-server system for integrating change events from each device running a local language processing system into a master language model. The change events can be integrated, not only into the master model, but also into each of the other local language models. As a result, some embodiments enable restoration to new devices as well as synchronization of usage across multiple devices. In addition, real-time messaging can be used on selected messages to ensure that high priority change events are updated quickly across all active devices. Using a subscription model driven by a server infrastructure, utilization logic on the client side can also drive selective language model updates.

Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

Abstract: A PCI-based interfacing device with mappable port addresses to legacy I/O port addresses has an addressing circuit, a PCI controller connected to the addressing circuit and a PCI port, and an equipment controller connected to the PCI controller and an equipment port. The addressing circuit sets up a legacy I/O port address. The PCI controller transmit and receive data packets having data and one of the set of legacy I/O port addresses encapsulated therein to be processed to and from the PCI port, and output the received data packets to the equipment controller. The equipment controller converts the data packets into equipment data corresponding to the equipment port, and transmits the equipment data to the equipment port. Accordingly, the PCI-based interfacing device can perform data communication with legacy I/O port addresses.

Abstract: A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.

Abstract: For a host that executes one or more guest virtual machines (GVMs), some embodiments provide a novel virtualization architecture for utilizing a firewall service virtual machine (SVM) on the host to check the packets sent by and/or received for the GVMs. In some embodiments, the GVMs connect to a software forwarding element (e.g., a software switch) that executes on the host to connect to each other and to other devices operating outside of the host. Instead of connecting the firewall SVM to the host's software forwarding element that connects its GVMs, the virtualization architecture of some embodiments provides an SVM interface (SVMI) through which the firewall SVM can be accessed to check the packets sent by and/or received for the GVMs.

Abstract: A apparatus for monitoring a downhole component is disclosed. The apparatus includes: an optical fiber sensor including a plurality of sensing locations distributed along a length of the optical fiber sensor; an interrogation assembly configured to transmit an electromagnetic interrogation signal into the optical fiber sensor and receive reflected signals from each of the plurality of sensing locations; and a processing unit configured to receive the reflected signals, select a measurement location along the optical fiber sensor, select a first reflected signal associated with a first sensing location in the optical fiber sensor, the first sensing location corresponding with the measurement location, select a second reflected signal associated with a second sensing location in the optical fiber sensor, estimate a phase difference between the first signal and the second signal, and estimate a parameter of the downhole component at the measurement location based on the phase difference.

Abstract: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.

Abstract: A memory data protection apparatus including a storage device, a cipher, and a validator is provided. The storage device is embedded in a chip electrically coupled to an external memory for storing an offset value, a signature and a key. The cipher electrically coupled to the storage device and the external memory to receive the key includes an encrypter and a decrypter. The encrypter is capable of executing an encryption to output an encrypted data and an encrypted certified data. The decrypter is capable of executing a decryption to output a decrypted data. The validator electrically coupled to the storage device receives the signature, the offset value and the certified data and determines an access limit of the external memory by validating the certified data with the signature and the offset value. The memory data protection apparatus accesses an original data in the external memory according to the access limit.

Abstract: A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.

Abstract: Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system.

Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Abstract: A process for creates a virtual address for a software entity called a “daughter” belonging to the context of a software entity called the “mother.” This virtual address includes a series of fields allowing retrieval of the series of fields of the virtual address of the mother software entity and a field unique in the context of the mother software entity. Each series of fields is associated with a single software entity which it defines completely.

Abstract: An example method includes (i) creating, by a first serial attached SCSI (SAS) switch, a first topology map describing a portion of a SAS fabric associated with the first SAS switch; (ii) receiving, at the first SAS switch and from a second SAS switch, a second topology map describing a portion of the SAS fabric associated with the second SAS switch; and (iii) merging, by the first SAS switch, the first topology map and the second topology map to produce a consolidated topology map of the SAS fabric.

Abstract: A memory device includes: a storage unit that stores public key information of a certificate authority for verifying a certificate and includes a secret area storing data of which secrecy is assured; and a control unit that controls access to the storage unit depending on reception information, wherein the reception information includes information where access control information is added to certificate information authenticated by the certificate authority, and the control unit verifies the certificate using the public key, identifies the access control information, and limits the accessible secret area in the storage unit.

Abstract: Provided are an apparatus and method for adapting an input/output interface. According to the exemplary method, a host system adapts an input/output interface of the guestsystem a to an input/output unit capability of a host system so as to support a service supported by an input/output unit supporting the input/output unit capability of the guest system using the at least one input/output unit of the host system.

Abstract: A server and an identifier synchronization method are provided, and the server includes a network card, hardware peripherals and a basic input output system. The network card stores at least one identifier. The basic input output system starts operating to acquire the at least one identifier of the network card and write the at least one identifier into each hardware peripheral after the server is booted.

Abstract: Embodiments of the present invention relate to a method and an apparatus for obtaining equipment identification information, where the method includes: detecting, by using a first GPIO port, a first discharging duration for a capacitor to discharge through a resistor to be tested; detecting, by using a second GPIO port, a second discharging duration for the capacitor to discharge through a fixed value resistor; and obtaining a resistance of the resistor to be tested according to the first discharging duration, the second discharging duration, and a resistance of the fixed value resistor. The embodiments of the present invention are capable of increasing identification efficiency of the GPIO port.

Abstract: A method includes configuring a processing circuit to perform: receiving a control word for an I/O operation, forwarding a transport command control block (TCCB) from the channel subsystem to a control unit, gathering data associated with the I/O operation, and transmitting the gathered data to the control unit in the I/O processing system. Gathering the data includes accessing entries of a list of storage addresses that collectively specifying the data. Based on an entry of the list comprising a not-set first flag and a corresponding first storage address, gathering data from a corresponding storage location, and based on an entry of the list comprising a set first flag and a corresponding second storage address, obtaining a next entry of the list from a second storage location.

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract: A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. The method comprises, at a first control element receiving a data packet transmitted by one of said one or more computing devices, and determining whether said data packet comprises a command including a first logical identifier identifying one of said resources. If it is determined that said data packet comprises a command including a first logical identifier a second logical identifier is obtained, the second logical identifier being associated with said first logical identifier and identifying said one of said resources. A request including said second logical identifier is transmitted to a second control element, the second control element being arranged to identify a physical device associated with said second logical identifier and to forward said request to the identified physical device.

Abstract: A method for providing access to hardware devices by a processor without causing conflicts with other processors included in a computer system. The method includes receiving a first address map from a first processor and a second address map from a second processor, where each address map includes memory-mapped input/output (I/O) apertures for a set of hardware devices that the processor is configured to access. The method further includes generating a global address map by combining the first address map and the second address map, receiving a first access request from the first processor and routing the first access request to a hardware device based on an address mapping included in the global address map. Advantageously, heterogeneous processors included in multi-processor system can access any hardware device included in the computer system, without modifying the processors, one or more operating systems executed by each processor, or the hardware devices.

Abstract: An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.

Abstract: Atomic operations within an I/O device are supported by processor architectures that are not required to include specific atomic instructions, by issuing the atomic operations from an I/O hub. A descriptor that specifies the atomic operation and a target address is retrieved by, or sent to, the hub. A trigger event, which may be a programmed I/O write to the hub with an address of the descriptor, or the contents of the descriptor itself, causes the I/O hub to issue the atomic operation. When the atomic operation is complete on the I/O device interconnect, the result is returned to the hub and a host is notified. The host then retrieves the results of the atomic operation from the hub. The host notification can be performed by interrupt or by polling the hub until a status change is detected.

Abstract: A system is disclosed for mapping operating-system-identified addresses for substantially-identical hardware modules into performance-parameter-based addresses for the hardware modules. The mapping is accomplished by configuring a flexible I/O interface responsive to a characterization of at least one performance parameter for each hardware module.

Abstract: An asymmetrical processing multi-core system used in a network device is provided. A sub processing core within the asymmetrical processing multi-core system facilitates a main processing core of the asymmetrical processing multi-core system in processing tasks, thereby improving an overall performance of the entire network device and causing the network device to operate more facilely. Different from a conventional processing method, the asymmetrical processing multi-core system does not require moving or copying a large amount of processed packet data, and thus a large amount of memory bandwidth is saved and the power consumption is reduced.

Abstract: In a microcomputer, by virtue of the function of one input signal judgment module in the application layer, with respect to whether the situation is such that operation is to be requested to a controlled object from each of a plurality of applications, judgment processing onto input signals representing status information of controlled objects or detection information from sensors or the like is made common. The object-oriented architecture is introduced into an embedded computer program so that the memory is saved and the apparatus is simplified.

Abstract: Apparatus having corresponding methods and computer-readable media comprise: an interface to receive a first address in a first address space for one of a plurality of resources, wherein each resource is associated with a respective first aperture in the first address space, and a respective second aperture in a second address space; and a translation module to translate the first address to a second address in the second address space; wherein the translation module includes address translation logic to swap a first sequence of bits in the first address with a second sequence of the bits in the first address; wherein a number of the bits in the second sequence is determined according to a number of the resources; and wherein a number of the bits in the first sequence is determined according to a difference between a size of the first aperture and a size of the second aperture.

Abstract: A method implemented by a non-volatile memory (NVM) controller comprising obtaining a NVM express (NVMe) command comprising a namespace identifier (NSID) from a host memory via a peripheral component interconnect express (PCIe) function, determining a mapping between the PCIe function and a namespace identified by the NSID based on a data structure stored in a PCIe memory address space, and accessing the namespace based on the mapping between the PCIe function and the namespace.

Abstract: According to an embodiment of the present invention, there is provided an input processing system including: an information storage device; and an information processing device, in which the information storage device includes: an input information storage unit configured to store information for performing input processing and identification information so that both of the information corresponds to each other; an identification information receiving unit configured to receive the identification information from the information processing device; an information transmitting unit configured to transmit, to the information processing device, the information for performing input processing stored to correspond to the identification information received by the identification information receiving unit; an identification information storage unit configured to store the identification information; an identification information transmitting unit configured to transmit the identification information to the informati

Abstract: A method for read pointer maintenance of a buffering apparatus, which is arranged to buffer data of a multi-tile encoded picture having a plurality of tiles included therein, includes the following steps: judging if decoding of a first tile of the multi-tile encoded picture encounters a tile boundary of the first tile; and when it is judged that the tile boundary of the first tile is encountered, storing a currently used read pointer into a pointer buffer, and loading a selected read pointer from the pointer buffer to act as the currently used read pointer.

Abstract: In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.

Abstract: A data storage device and a FLASH memory control method with a cache space. The FLASH memory control method includes the following steps: using a plurality of channels to access a FLASH memory, wherein the FLASH memory has a plurality of blocks each with a plurality of pages, and the blocks are grouped to be accessed by the different channels; allocating a random access memory to provide a cache space, the cache space having a plurality of cache areas caching write data for the different channels, respectively; distributing the data issued from a host to correspond to the different channels; and reusing a latest-updated cache area of the cache space to cache write data when a logical address requested to be written with data is identical to a logical address that the latest-updated cache area corresponds to.

Abstract: Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: A system is disclosed for mapping operating-system-identified addresses for substantially-identical hardware modules into performance-parameter-based addresses for the hardware modules. The mapping is accomplished by configuring a flexible I/O interface responsive to a characterization of at least one performance parameter for each hardware module.

Abstract: A system on a chip (SOC) includes a master module, a first swapping module, and a switch module. The master module is configured to generate a transaction request, the transaction request including an address field including an address, the address corresponding to a first slave module associated with the transaction request, and a plurality of interface select bits corresponding to a desired one of a plurality of ports of the first slave module. The first swapping module is configured to swap, in the transaction request, the plurality of interface select bits with selected bits of the address in the address field. The switch module is configured to route the transaction request to the desired one of the plurality of ports based on the address.

Abstract: Techniques for distinguishing between symmetrically-connected integrated circuit devices so that each device may be individually selected are disclosed in reference to various embodiments. In one embodiment, a bi-directional data path provided for ongoing data transfer between a master device and multiple nominally identical slave devices is used to receive a merged set of randomly generated values from the slave devices, and then used to return one or more device-select values that enable assignment of a unique chip-identifier (ID) within each slave device. After chip-IDs have been assigned to the slave devices, the master device may issue one or more chip-select signals corresponding to the unique chip ID assigned to a given slave and thereby enable that slave device, exclusively of the others, to participate in a data transfer operation over the bi-directional data path.

Abstract: A method of operating HDMI ports. An HDMI port controller assigns virtual addresses when the maximum number of HDMI CEC addresses is exceeded and CEC logical addresses are duplicated with only one HDMI port corresponding to device having a CEC logical address having its port enabled at any given time. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: Systems, methods, and computer-readable storage media are provided for brokering access to peripheral devices and/or device models associated with a computing system. An access broker evaluates requests for access to peripheral devices/models on behalf of a plurality of applications. The access broker evaluates requests for access to peripheral devices including scanners, point-of-sale devices, and devices using ubiquitous device protocols (e.g., USB, HID, Bluetooth, and Bluetooth LE) utilizing application declarations and user consents based upon device model identifiers and/or device-specific identifiers associated with the various devices. Applications may be notified of consent changes at runtime and/or application firmware updates for peripheral devices may be conducted upon receipt of user consent, for instance, to ensure adequate battery power before performing a peripheral device firmware update.

Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.

Abstract: Two or more ports of a same type are identified in a computer. A separate device driver process is initiated for each of the identified ports. A one-to-one correspondence between each of the ports and each of the device driver processes is established.

Abstract: A system and method of connecting a computer to a peripheral of another computer. An example system includes a processor connected to a network and to the one and the other computers through the network. The processor executes web service software which establishes a discovery service for receiving a peripheral connection request from application software of the one computer and peripheral management software which receives information from the other computer through the web service software about the peripherals of the other computer.

Abstract: A management method is provided, suitable for an electronic system having electronic devices connected in a daisy-chain configuration. The management method comprises the steps of: the electronic devices are sequentially connected with a host, thereby obtaining universal unique identifiers corresponding to the electronic devices; serial numbers corresponding to the electronic devices are generated according to a first order of obtainment of the universal unique identifiers of the electronic devices; and the host communicates with the electronic devices according to the serial numbers.

Abstract: In a method for allocating SAS addresses to SAS expander devices in an SAS expander system, the SAS expander system includes a master SAS expander device, a slave SAS expander device and an EEPROM. The method defines an address parameter for specifying a master SAS address for the master SAS expander device and specifying a slave SAS address for the slave SAS expander device, and obtains an original SAS address from the EEPROM when the original SAS address is identical to either the master SAS address or the slave SAS address. The method adds the address parameter to the original SAS address to generate a first SAS address and allocates the first SAS address to the master SAS expander device. The method adds the address parameter to the first SAS address to generate a second SAS address, and allocates the second SAS address to the slave SAS expander device.

Abstract: A method of generating length parameters, comprising the steps of reading a data stream from a host, detecting a particular field of the data stream, and calculating a variable based on a length parameter of a first list to be transferred. The data stream may comprise a plurality of definitions. The method may also comprise the step of selecting one of the list definitions. One of the list definitions may be used to generate a length parameter used in a second list in response to (i) the particular field of the data stream and (ii) the length parameter of the first list.

Abstract: A method of extending a standard primitive in a data storage fabric is disclosed. A group of primitives are combined into a sequence including the standard primitive and a variable information primitive. The variable information primitive includes data particular to a broadcast of the sequence. The sequence is broadcast through the data storage fabric.

Abstract: A device comprises circuitry configured for being communicatively coupled to a transceiver. In operation, the device is configured to receive a first message from another device to support at least one aspect of attachment of the device and the another device and to send, to the another device, a second message after the first message and prior to attachment. In operation, the device is further configured to receive, from the another device, a third message that is sent after the second message and prior to attachment and send, directly to the another device, data utilizing at least one channel for data transfer utilizing a second one of the addresses for identification in association with the device on the shared wireless communication medium, for data transfer after attachment in connection with a group that is controlled by the another device.