Abstract: An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.

Abstract: A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a processor core, local memory and DMA module. The local memory of the idling SPE stores data stored in the global memory and used by the processor core of the running SPE, before the data is used by the processor core of the running SPE. The DMA module of the running SPE reads the data from the local memory of the idling SPE, and transfers the data to the processor core of the running SPE.

Abstract: A CPU 5 is provided with both the functionality of issuing an external bus access request directly to an external memory interface 3 and the functionality of issuing a DMA transfer request to a DMAC 4. Accordingly, in the case where data is randomly accessed at discrete addresses, an external bus access request is issued directly to the external memory interface 3, and in the case of data block transfer or page swapping as requested by a virtual memory management unit or the like, a DMA transfer request is issued to the DMAC 4, so that it is possible to effectively access the external memory 50.

Abstract: A method for sharing a memory through a plurality of routes and a device thereof are disclosed. The digital processing apparatus in accordance with an embodiment of the present invention comprises a main processor, an application processor controlled by the main processor and coupled to the main processor through one connection bus and a memory having a plurality of ports, each of which is coupled to the application processor through an independent memory bus. With the present invention, the process time for processing a high-performance, high-resolution image can be minimized, and the loss in process efficiency of the application processor can be minimized.

Abstract: A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.

Abstract: Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and submitting the DMA request to an arbitration module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from plural buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.

Abstract: A bus device is used with a computer system. In the bus device, a bus-interfaced host performs data transmission in a first mode in response to a first command resulting from certain software execution of the computer system. A bridge device is coupled to and communicable with the bus-interfaced host via a first interface according to a first transmission protocol, and coupled to and communicable with the bus-interfaced device via a second interface according to a second transmission protocol. A bus-interfaced device performs data transmission in a second mode different from the first mode in response to a second command resulting from certain modification of the first command.

Abstract: A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.

Abstract: A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A data processing apparatus includes: a system bus; a processor connected to the system bus in slave connection, the processor having a command register configured to retain a DMA request command corresponding to a resource on the system bus and be accessed through the system bus; and a DMA controller connected to the system bus in bus-mastering connection, the DMA controller being configured to read out the DMA request command retained in the command register and control DMA transfer between the resource on the system bus and the processor based on the DMA request command.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A bridge circuit includes a bus, a memory interface module, a memory control module, and an external storage control module. The memory interface module receives a memory address from a processor via a memory interface and outputs the memory address to the bus. The memory address corresponds to one of a plurality of address regions of an address space of the processor. The memory control module receives the memory address via the bus and communicates with a memory when the memory address corresponds to a first one of the plurality of address regions. The external storage control module receives the memory address via the bus and communicates with an external storage device when the memory address corresponds to a second one of the plurality of address regions.

Abstract: A method for transmitting audio streams includes providing a USB bus, and transmitting an audio stream through the USB bus by utilizing a bulk transfer mode. The method further includes providing a buffering module, buffering the audio stream in the buffering module to generate a buffered audio stream, performing a digital-to-analog conversion on the buffered audio stream to generate an analog playback signal, and performing an analog-to-digital conversion on an analog recording signal to generate the audio stream.

Abstract: A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.

Abstract: A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.

Abstract: A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost.

Abstract: Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access.

Abstract: A Direct Memory Access (DMA) system is provided for simplified communication between a processor and IP cores in an FPGA. The DMA system includes use of dual-port BRAM as a buffer and a decoder as a DMA control signal identification mechanism. The DMA control signals are stored in an area of the BRAM memory recognized by the decoder using chip enable (CE), write enable (WE), and address (ADR) signals. The decoder, upon recognizing a DMA control signal, will generate an event vector. The event vector triggers a READ operation by the receiving device at the associated BRAM control data memory address. DMA control codes can be detected as sent from either the processor or the IP core or both, depending upon whether the system employs a MASTER/SLAVE, SLAVE/MASTER, or PEER/PEER control model.

Abstract: A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information processing system includes the first storage section for storing the information, and a control section. The information transfer system includes: the second storage section for storing descriptor information indicating the location at which the information is stored in the first storage section and the size of the information; and a DMA transfer section for DMA transferring the information between the first storage section and the second storage section based on the descriptor information. The DMA transfer section DMA transfers the descriptor information concerning the DMA transferred information from the second storage section to the first storage section. The control section loads the descriptor information from the first storage section.

Abstract: A method, system and computer program product that allows a System Image within a multiple System Image Virtual Server to maintain isolation from the other system images while directly exposing a portion, or all, of its associated System Memory to a shared PCI Adapter without the need for each I/O operation to be analyzed and verified by a component trusted by the LPAR manager.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

Abstract: The key limiter in a multi-drop system, such as a multi-drop memory system, is the super-positioning of reflection noise from multiple modules or pluggable units, such as DIMMs. Using the noise cancellation approach of the present invention, the noise is distributed across the width of the pulse thus significantly reducing the impact of noise super-positioning. Use of the system of the present invention provides improved noise margins and is a key enabler of high performance, high speed bus, particularly at higher bit rates, as well as an enabler for higher capacity modules, such as DIMMs. The system provides for electrical traces from each of the modules of varying lengths thereby distributing the noise reflections.

Abstract: A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.

Abstract: A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.

Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability.

Abstract: In a portable FireWire compatible device, a direct memory access (DMA) bus switch coupled by way of a DMA bus to a central processing unit (CPU), a local hard drive (HDD), and a FireWire port, provides a direct connection between the FireWire port and the HDD bypassing a main bus and the CPU when a data transfer request is received and processed by the CPU. Otherwise, until the data transfer request is received and processed, the CPU is directly connected to the HDD. In this way, a high speed data transfer between the FireWire port and the HDD is provided only when an appropriate data transfer request is received and processed.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.

Abstract: A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC includes a DMA command queue (DMAQ) coupled to the local storage and configured to receive the list DMA command from the local storage and to enqueue the list DMA command. An issue logic is coupled to the DMAQ and configured to issue an issue request to the DMAQ. A request interface logic (RIL) is coupled to the DMAQ and configured to read the list DMA command based on the issue request. The RIL is further coupled to the local storage and configured to send a fetch request to the local storage to initiate a fetch of a list element of the list DMA command from the local storage to the DMAQ.

Abstract: A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packing criteria and analysing the data pattern and determining the impact of offset direction on data packing. If the packing criteria are met, the data is compacted and fetched in four bytes or two half-words in one transaction by performing a full-word transfer instead of a partial transfer. If the packing criteria are not met, a single byte or a single half word is fetched. This invention provides a system for reducing data transfer overheads. The system comprises of an external address generation unit for generating external memory addresses and corresponding byte enables and a read local address generation unit for generating internal memory addresses and corresponding byte enables.

Abstract: The apparatus for a test and measurement instrument consists of multiple integrated circuits with each integrated circuit being connected to its own memory controller. At least one of the integrated circuits is a specialized integrated circuit, which may be a graphics processing unit, a digital signal processor, or a field-programmable gate array. Each memory controller is connected to its own memory. The integrated circuits are connected in a circular arrangement by multiple high-speed interconnects. A bridge is connected to at least the first and last integrated circuits. A system bus connects the bridge to an acquisition module. The acquisition module has a signal bus interface with the system bus being connected to the acquisition module and having its own acquisition hardware. The acquisition hardware is a direct memory access machine that can transfer data to any portion of the memory. There is a signal source connected to the signal bus interface.

Abstract: A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, a SATA I/F connected to a SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register that is a pseudo register provided to implement a PATA/SATA bus bridge, and the SATA I/F includes a shadow task file register, a register value being transferred between the shadow task file register and the task file register.

Abstract: Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.

Abstract: Provided is a method and an apparatus for processing data at a high speed by a UE for data communication. In the method, received data is divided into a header and payload information, which are then stored in different memories. In the method, header processing and payload data processing can be performed in parallel, and two memory devices can perform parallel processing without sharing a bus.

Abstract: Systems and methods are disclosed for detecting a first device on a first bus issuing a read request for an amount of data to a second device on a second bus. The systems and methods further include detecting a bridge requesting a first portion of the data from the second device on behalf of the first device in response to the bridge receiving the read request, where the bridge couples the first bus to the second bus. In addition, the systems and methods include triggering the bridge to request an additional portion of the data on behalf of the first device.

Abstract: A direct memory access controller may comprise a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled with the data register and the pattern register, and a control unit coupled with the comparator operable to stop a data transfer if the comparator detects a match of the data register and the pattern register.

Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO (210) can also be allocated to a single channel if there is only one logical channel active. The FIFO (210) increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.

Abstract: In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later time; (3) notifying second logic of the controller of the request; (4) determining at least one of whether the request is valid and enough buffers are available to complete the request; (5) programming a filtering pipe; and (6) responding to the first logic based on at least one of whether the request is valid and enough buffers are available to complete the request such that the first logic may employ the filtering pipe to complete the request. The first logic operates in a first clock domain and second logic operates in a second clock domain. Numerous other aspects are provided.

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target data from a cache coupled to the network adapter to respond to a read command packaged in a packet sent by an initiator over a network. If the network adapter cache does not have the target data addressed by the read command, the read command is forwarded to a target controller coupled to a storage unit to process the read command.

Abstract: A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it has connections for connecting at least two data buses and can output data received by a first data bus either onto the same data bus or onto another data bus immediately or later. Therefore, the data transmission device can be used selectively, alternately or simultaneously as a DMA controller and a bus bridge. It also has additional functions unrelated to DMA controllers and bus bridges.

Abstract: In one embodiment, the present invention includes a method for sending a connection request from a requestor endpoint to a target endpoint based on route information stored in the requestor endpoint, and receiving a connection confirmation from the target endpoint to confirm establishment of a peer-to-peer connection between the endpoints. The endpoints may be part of an Advanced Switching (AS) for Peripheral Component Interconnect (PCI) Express™ architecture, and in one embodiment a simple load store (SLS) protocol may be used for peer-to-peer communications in the AS environment. Other embodiments are described and claimed.

Abstract: A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.