Abstract: Apparatus and method for providing DMA transfers between an adapter card with or with out DMA capabilities and a system CPU with DMA capabilities. An adapter DMA controller circuit resides between the system CPU and the adapter card. This adapter DMA controller allows the system to run in immediate mode which allows the system CPU to talk to the adapter card as if the adapter DMA controller was not there. The system can also run in DMA mode. In this mode the system CPU sets up the system DMA controller and the adapter DMA controller. The adapter DMA controller takes over sending or receiving data to the adapter card and then requesting a DMA transfer with the system DMA controller. The transfer of data between the adapter DMA controller and the adapter does not use any system CPU resources such as the data and address busses. The system CPU is free to use the system resources to continue operation.

Abstract: A system is provided that includes a bus master, a bus slave and a fly-by slave interface, all coupled to a peripheral bus. A peripheral device is coupled to the fly-by slave interface. The bus master is configured to control fly-by transfer of data between the bus slave and the peripheral device without buffering the data. The fly-by slave interface is configured to isolate the peripheral device from the peripheral bus during fly-by transfer of data between the bus slave and the peripheral device. In addiction, the bus slave is configured to provide a set of control signals on the peripheral bus, wherein the control signals regulate the flow of data on the peripheral bus during fly-by transfer of data between the bus slave and the peripheral device. Fly-by transfers can be fully synchronous, and burst operation at the rate of one data value per clock cycle is supported.

Abstract: Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.

Abstract: A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized.

Abstract: An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware description 10 are input into the extracting portion 101, the extracting portion 101 extracts from the data whether the memory element is a memory device or an FF. The extracting portion 101 reads the top address and the address size of the memory element when the memory is the memory element and reads address when the memory is an FF, and the thus read data are output to the address competition detecting portion 103. The address competition detecting portion 103 detects competition of the addresses by determining whether the address information stored in the bit data memory portion 102 includes 1. The output portion 104 converts the data concerning address of the memory into a description language of the hardware of the bus interface circuit.

Abstract: In a bridged, pipelined network (FIG. 1), a network-to-host bridge (140) identifies the address space of a host computer (FIG. 2) as not being contained within the host computer memory space (120). During the removal of the host computer (100) and its replacement by a new host computer, the network-to-host bridge (140) momentarily locks out traffic (FIG. 3, step 320) in order to disable peripheral components (FIG. 1, 160, 180) from initiating bus transactions. When the new host computer is installed (FIG. 3, step 320) and the bus lockout is removed (step 340), the new host memory area is protected from direct memory access transactions which were stored in the bus hierarchy during the host computer swap.

Abstract: A DMA transfer device transfers data from a first region to a second region in a memory allowing high-speed page access. The DMA transfer device includes: a first detecting unit for detecting a plurality of read areas that form the first region, each read area being located between page boundaries; a second detecting unit for detecting a plurality of write areas that form the second region, each write area being located between page boundaries; and an access unit for performing high-speed page access to each of the read areas and each of the write areas.

Abstract: A method for use in a CAN device (e.g., a CAN microcontroller) that includes a processor core and hardware external to the processor core (e.g., a DMA engine) that writes message data into a designated message buffer for ensuring integrity of the message data stored in the designated message buffer. The method includes providing a three-state semaphore to indicate a current access status of the designated message buffer, the three-state semaphore having a first state indicative of the hardware external to the processor core starting to write new message data into the designated message buffer, a second state indicative of the hardware external to the processor core having finished writing the new message data into the designated message buffer, and, a third state indicative of the processor core starting to read message data from the designated message buffer. The processor core determines whether the designated message buffer is ready to be accessed based on the current state of the semaphore.

Abstract: Disclosed is an MPEG portable sound reproducing system and a method for reproducing sound data compressed using the MPEG method.

Abstract: A bridge device for use in computer systems has a first interface to a first interconnect apparatus such as a processor bus. It also has a second interface to second interconnect apparatus such as an I/O bus. The second interconnect apparatus is of a type capable of connection to a DMA-capable peripheral device. The bridge device has address translation hardware to translate I/O virtual addresses received from the second interface into physical memory addresses for transmission onto the first interface. The address translation hardware has an associated coherency maintenance apparatus. In a particular embodiment, the address translation hardware has a translation lookaside buffer and the coherency maintenance apparatus is apparatus for snooping through the first interface, invalidating TLB entries when a page table in memory is updated.

Abstract: Peripheral Component Interconnect (PCI) device contains Host Messaging Unit (HMU) which is operative to off load host processor and PCI device processor from PCI bus transfer overhead. HMU is configurable to asynchronously retrieve host processor commands from circular buffer, either by using polling or interrupt service techniques. Both host command retrieval methods are operable to remove host processor and PCI device processor from direct PCI bus command transactions, thereby increasing the efficiency of both processors. Interrupt service control of HMU is operative to buffer multiple service requests from PCI device processor, so that a more efficient use of the host processor interrupt service routine is implemented, providing for multiple service requests to be serviced in a single interrupt service request.

Abstract: A processor may include a processor core, which interprets and executes instructions, and a system bus interface, which enables the processor to communicate with a system. The system bus interface may include a fill bus and a DMA bus. The system bus interface may include a bridge between the fill bus and the DMA bus which enables the system bus interface to re-route information placed on the fill bus onto the DMA bus and back into the core.

Abstract: When the data bus is cut off from the CPU (1) and the transmission ready signal (TXRDY) is activated, the DMA control circuit (10) reads 32 bits of data at once according to the lead address of the destined area for storage in the DRAM (2) and the address width that are set by the CPU (1), and stores the data in the transmission buffer (16). The selector (17) selects 8 bits of data at a time from the transmission buffer (16), the data is written to the communication circuit (14) and thus output, the bus release request is cancelled, 8 bits of data is read at a time from transmission buffer (16), and the data is written into the communication circuit (14). When the transmission ready signal is provided once again, the above-described processing is repeated.

Abstract: A duplex memory control apparatus having a first control unit containing a first memory and a second control unit containing second memory, a first control unit and a second control unit connected to each other through a bus.

Abstract: An information handling system having an integrated internal scalable switching storage system is disclosed. The information handling system includes a housing, a processor disposed in the housing and a memory device for storing a program of instructions executable by the processor. A bus of the information handling system is disposed in the housing, and the processor and the memory are coupled to the bus. A host bus adapter is coupled to the bus and is disposed in the housing. An information storage system is in turn coupled to the host bus adapter and is also disposed in the housing. The information storage system includes a backplane for coupling at least one information storage device to the host bus adapter. The information storage system and host bus adapter are preferably compliant with a scalable, switching, mass storage system standard such as Fiber Channel.

Abstract: The present invention provides methods and a system for transporting A/V data over a serial bus. A memory space is allocated for a set of buffers to store a plurality of CIPs. Each of the CIPs includes a header field and a data field with the header field having a SYT field for storing a presentation time. Initial CIP header values are generated including initial SYT field values for each of the CIP header fields in the set of buffers. A circular DMA script program is generated and configured to describe a set of full and empty CIPs for each of the buffers. The circular DMA script program is configured to transmit the CIPs from the buffers. The generated DMA script program is executed to sequentially transmit the CIPs from the buffers by traversing the buffers in a circular manner so that the transmitted CIPs are presented at the associated presentation time.

Abstract: A mechanism for initiating and completing one or more I/O transactions using channel and memory semantic messages is disclosed. Channel semantic messages are messages that are simply packetized and transmitted. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.

Abstract: A system is provided for transferring data from a first network, which is packet based, to a second network. The system includes a physical layer input device, an input FIFO, a DMA controller for transferring data between addresses, an output FIFO, and a physical layer output device. The physical layer input device places beginning and end markers around packets in the input FIFO, and the DMA controller monitors the data which it transfers, and transfers data between said beginning and end markers, and ceases a transfer when an end of packet marker is reached.

Abstract: A bridge manager (bridge management equipment) is automatically determined. In a network, bridges 51 to 54 are configured by connecting portals 41 to 48 respectively connected to buses 11 to 15 and the different buses 11 to 15 are connected via the bridges 51 to 54. A value denoting the function of the bridge manager managing the portals 41 to 48 and equipment ID are stored in registers in each portal 41 to 48. One bridge manager is selected out of candidates 31 and 34 for a bridge manager based upon a value in the registers.

Abstract: A system and method for detecting block(s)of data transferred to a disk array from a host processor system, in which the block(s) have unique, identifiable values or patterns, is provided. A direct memory access (DMA) engine is resident on the bus structure between the host and the disk array, which can be configured as a redundant array of independent disks (RAID). A cache memory is also resident on the bus and is adapted to cache write data from the host under control of a cache manager prior to storage thereof in the disk array. The DMA engine is adapted to detect predetermined patterns of data as such data is transferred over the bus therethrough. Such data can include a series of consecutive zeroes or another repetitive pattern.

Abstract: The efficiency of an overall computer communications system is greatly improved by a new method to transfer data on a data communications bus. The method allows one or more small command structures of a smaller size to have priority in bus arbitration; and then allow normal bus arbitration to permit large data transfers, such as DMA read operations. Thus, the method balances the need to keep I/O devices utilized, which devices would otherwise experience latency because they are waiting for the larger DMA read operations to conclude. But by allowing a configurable number of these smaller operations to proceed and then permitting larger data transfers to occur, both the host bus and the I/O bus are efficiently utilized.

Abstract: The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

Abstract: A method of transferring data from a source device to a destination device via a source-control device connected to the source device and a destination-control device connected to the destination device includes the steps of transmitting a data-transfer-request signal from the source device to the source-control device, transmitting a data-transfer-acknowledge signal from the source-control device to the source device in response to the data-transfer-request signal, and transmitting a data-transfer-request signal from the source-control device to the destination-control device concurrently with the transmission of the data-transfer-acknowledge signal.

Abstract: A data transfer control apparatus is disclosed for controlling conflict of data transfer on a data bus connected to a microprocessor through a bridge circuit. The bridge circuit includes a monitoring unit. When an execution instruction for MPC transfer is issued during DMA transfer, the monitoring unit measures a time period over which the data bus is to be occupied with the MPC transfer. When the PCI bus is to be occupied with the MPC transfer for a predetermined time period, the monitoring unit does not suspend the DMA transfer but performs the MPC transfer after the completion of the DMA transfer.

Abstract: The present invention generally relates to a digital scanner for scanning images. More specifically, the present invention is directed to a method and apparatus for quickly processing and storing digital data in memory.

Abstract: A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The system also includes a device bus, which may or may not be coupled to the PCI bus by a south bridge. A device bus interface bypasses the north and south bridges, to provide a single-step interface to the device bus. This reduces the latency.

Abstract: An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc., onto a bus together with a data transfer request without involving use of the CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as a data transfer request source desires to perform data transfer without regard to the state of processing by the microcomputer, it can perform data transfer processing with its own timing and the data transfer with the input/output device as a principal base is allowed.

Abstract: A first bus 11 and a second bus 12 are connected through a bus repeater 13 having a buffer memory, and DMA (Direct Memory Access) controllers 22, 27 are respectively connected to the buses 11 and 12. The bus repeater 13 can issue DMA request to the respective DMA controllers 22, 27, and these DMA requests can be masked by respective CPUs 22, 27. The DMA controller 22 carries out DMA transfer of data on the bus 11 between the DMA controller 22 and the buffer memory within the bus repeater 13, and the DMA controller 27 carries out DMA transfer between the buffer memory and the bus 12. The CPU 22 masks DMA request of the bus repeater 13 to directly access the buffer, thereby making it possible to check DMA function. Thus, debugging of the system for carrying out DMA transfer through buffer between different buses is easily carried out.

Abstract: In a method of reducing direct memory access in a machine employing a data segmenting scheme, transfer of a repetitive block of data is detected. The repetitive block of data repeats a data word of a predetermined value. A first invalid address is assigned to a current address pointer. The first invalid address indicates that the repetitive block of data is to be generated. A second invalid address is assigned to an end segment pointer. The second invalid address corresponds to the first invalid address plus a value indicating a number of repetitive data words that is included in the block of repetitive data. While the current address pointer has a value assigned thereto that is not equal to the second invalid address, a data word of the predetermined value is generated and the value assigned to the current address pointer is stepped.

Abstract: A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing. A storage device stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing. A counter updates a count value thereof every sampling period and generates the updated count value as a basic address.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: A USB-based data acquisition system including virtual DMA software which increases USB data transfer rates with minimal changes to DAQ driver level software. The virtual DMA software operates to receive or intercept DMA instructions provided by the DAQ driver level software to program a DMA controller to acquire data from the device. The virtual DMA software intercepts the DMA instructions and emulates operation of the DMA controller in software. The virtual DMA software operates to request the data in bulk packets from the device. The virtual DMA software then stores the received packets of data in the addresses specified in the DMA instructions. The virtual DMA software thus emulates operation of a DMA device, thus “fooling” the DAQ driver level software into thinking the data is being acquired using real DMA transfers. Thus, the present invention allows for much faster data transfers, while requiring minimal or no changes to the existing DAQ driver level software.

Abstract: The present invention generally relates to a loopback direct memory access control system for a digital scanner for processing images. More specifically, the present invention is directed to a method and apparatus for quickly reading digital data from memory, processing the digital data and writing the processed digital data to memory.

Abstract: A framework with multiple selections for a south bridge and a north bridge connecting is provided. The up/down controller and PCI response of the south bridge applies the enable or disable and mutual communication theories of the bus arbiter to design various required connections. The labor and cost consumption for redesign under different modes that the peripherals cannot comply with is saved. In addition, the efficiency of internal material flow in manufacture is improved by the chip unification.