Abstract: This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting the multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

Abstract: An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and block length are sent to the DMA controller, and the DMA controller is adapted such that, on receipt of a starting address and block length sent from the host controller, it retrieves the indicated data from the associated system memory. This has the advantage that the embedded host controller can be used with different host microprocessors, without assuming that PCI functionality is available.

Abstract: A data processing apparatus contains a first bus connected to a first memory, a first central processing unit (CPU) being accessible to the first memory via the first bus, a first Direct Memory Access (DMA) controller being accessible to the first memory via the first bus, and a monitor circuit connected to the first bus and monitoring addresses transferred on the first bus. The addresses transferred on the first bus are transmitted from the first DMA controller to the first memory via the first bus. The monitor circuit compares the address transferred on the first bus with a preset monitor target address. The CPU acquires the comparison results by the monitor circuit. If the comparison results show an address match, then the CPU accesses the first memory. The CPU can in this way access the first memory at a correct timing.

Abstract: Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.

Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.

Abstract: A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a processor core, local memory and DMA module. The local memory of the idling SPE stores data stored in the global memory and used by the processor core of the running SPE, before the data is used by the processor core of the running SPE. The DMA module of the running SPE reads the data from the local memory of the idling SPE, and transfers the data to the processor core of the running SPE.

Abstract: There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first and second bus. The transfer apparatus controls a transfer sequence of transaction transfers by the bridge and data transfers by the data transfer unit, in which transaction transfers by the bridge are based on bus sequencing rules and data transfers by the data transfer unit are based on a data transfer activation condition.

Abstract: A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).

Abstract: A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.

Abstract: A pattern may be written to an allocated section of host memory to track how much data has been received in the host memory from a direct memory access controller coupled to a First In, First Out memory. A driver may send the most recently written sample of data from the host memory to an application requesting sampled data. The driver may determine the amount of data written to the host memory by reading the allocated section of host memory and determining the size of a portion of memory, that previously had the pattern, that has been written over with data. The driver may determine if more data than a predetermined amount of data has been written to the host memory or is available to be written to the host memory, and if necessary, send an indication to the application.

Abstract: An improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while transferring data between computer peripherals.

Abstract: A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access (DMA) controller, an instruction memory and a plurality of memories. The instruction memory contains processor instructions and DMA instructions. The DMA controller fetches DMA instructions from the instruction memory. The DMA controller executes the fetched DMA instructions and thus populates the plurality of memories with data from the external device. The processor then operates on the data found in the populated memories.

Abstract: A processing system and method for transferring data in a processing system. The processing system includes a bus mastering device, a plurality of slave devices, and a bus interconnect configured to switch the bus mastering device between the slave devices. Each of the slave devices has a plurality of addresses. The bus interconnect includes a DMA controller configured to transfer data from a first one of the addresses to a second one of the addresses in response to a single bus command from the bus mastering device.

Abstract: In response to a direct memory access (DMA) request, a direct memory access controller (DMAC) performs reading at a host side at which a high-speed bus master is arranged. A bus bridge sends a dummy data to the DMAC, and performs reading at an input/output (I/O) side at which a low-speed slave device is arranged. In response to a following DMA request, the DMAC performs reading at the host side. The bus bridge sends a data read for a previous DMA request at the I/O side to the DMAC, and performs reading at the I/O side. Data that is read in response to a final DMA request at the I/O side is stored in a buffer inside the bus bridge. A central processing unit (CPU) reads a last read data from the buffer.

Abstract: It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

Abstract: An apparatus communicates with an advanced switching (AS) fabric. The apparatus includes a transmit engine that generates a request packet for transmission to the AS fabric. The transmit engine associates a first transaction identifier with the request packet. A receive engine receives a reply packet in response to the request packet. The reply packet contains a second transaction identifier. The receive engine compares the first transaction identifier to the second transaction identifier. If the first transaction identifier matches the second transaction identifier, the receive engine decides to store data from the reply packet at an address associated with the first transaction identifier.

Abstract: A network processor exchanges data of various descriptions via a plurality of network nodes with external network devices, such as other processors, controllers, transducers, or sensors. The network processor includes a master processor for control tasks of the processor, and a network coprocessor for supporting network tasks. A first and a second bus system, associated with the master processor and the network coprocessor with its associated functional units, particularly Data Link Layer memory devices, respectively, serves to separate the two fields of tasks from each other. This permits both a support of gateway functions and a support of Higher Layer functions. Higher Layer memory devices, whose messages are ultimately sent or received by the master processor, are accessible from the master processor or the network coprocessor directly or indirectly via the first and/or second bus systems.

Abstract: An electrical device is connected to at least one memory accessing unit and to a memory including at least one physical memory module. The device includes at least one access channel circuit connected to the least one memory accessing unit via at least one system bus and to the at least one physical memory module. The access channel circuit provides memory access for the at least one memory accessing unit to at least a part of the memory.

Abstract: Method and apparatus for controlling direct access to memory circuitry by a device is described. In one example, a streaming interface is configured to transmit and receive a communication sequence to and from the device. Control logic is configured to implement a plurality of direct memory access (DMA) engines. The DMA engines are configured to read and write data to and from the memory circuitry. A set of registers is configured to store control data for the plurality of DMA engines.

Abstract: It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Abstract: A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.

Abstract: A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus. The peripherals include at least one memory. An arbiter circuit is coupled to the high speed primary bus for managing access requests to the high speed primary bus by any one of the master devices. The microprocessor system further includes a secondary bus, and a bridge interface circuit coupled between the high speed primary bus and the secondary bus. The bridge interface circuit includes a direct memory access controller so that during each data transfer routine between a peripheral connected to the secondary bus and one of the peripherals reduces to a single transfer phase engagement of the high speed primary bus.

Abstract: A generic, parallel, n-bit wide data path communication bus allows a number of major slave devices (such as DSPs, Microprocessors, ASICs, FPGAs, etc) to be used with PVDMs and other devices. A higher level protocol allows a DMA engine to interface multiple Master devices directly with multiple slave modules through the DMA engine.

Abstract: The integrated circuit comprises, in addition to a first bus and a first DMA controller, a second bus and a second DMA controller that mutually connects the first bus and the second bus. A main memory is connected to the first bus, and a frame memory is connected to the second bus. By the construction, a possible conflict in data transfer as “urgent processing” and as “normal processing” can be avoided. The data transfer as “urgent processing” includes transferring image data between the frame memory and an image input device or an image display device; while the data transfer as “normal processing” includes transferring image data between the main memory and the frame memory.

Abstract: In a storage system directly connected to a network, if conventional interfaces and protocols are used when an I/O command issued from a file server is transmitted to the storage system, the command/data is serially transferred via a single transfer path so that the performance is lowered. Conventional interfaces do not provide the means to notify the storage system of the failure at the file server. The file server and a channel adapter of the storage system are mounted on the same board and connection paths therebetween are controlled so that a plurality of protocols can be operated independently. A path independent from a command/data path is provided between the file server and channel adapter, and the received failure information is stored in a shared memory of the storage system and used for the fail-over.

Abstract: An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width being different from the read bus width. A memory system including the asymmetric memory interface, memory controller and memory device is disclosed. The asymmetric nature of inputs and outputs reduces pin count by avoiding symmetric replication of bus widths for inputs and outputs. A method of accessing data in a memory device is also disclosed.

Abstract: Peripheral Component Interconnect (PCI) device contains Host Messaging Unit (HMU) which is operative to off load host processor and PCI device processor from PCI bus transfer overhead. HMU is configurable to asynchronously retrieve host processor commands from circular buffer, either by using polling or interrupt service techniques. Both host command retrieval methods are operable to remove host processor and PCI device processor from direct PCI bus command transactions, thereby increasing the efficiency of both processors. Interrupt service control of HMU is operative to buffer multiple service requests from PCI device processor, so that a more efficient use of the host processor interrupt service routine is implemented, providing for multiple service requests to be serviced in a single interrupt service request.

Abstract: A storage device host controller such as an SATA (Serial ATA) host controller and a corresponding method are provided for performing host-to-device and device-to-host communications in a PIO (Programmed I/O) data transfer mode and a DMA (Direct Memory Access) data transfer mode. The host controller comprises a buffer unit for buffering data and a data stream selection unit for selecting a data stream for submission to the buffer unit. The data stream selection unit is connected to receive at any one time at least one of a host-to-device data stream in the PIO data transfer mode, a host-to-device data stream in the DMA data transfer mode, a device-to-host data stream in the PIO data transfer mode, and a device-to-host data stream in the DMA data transfer mode, and select from the received data streams the data stream to be submitted to the buffer unit.

Abstract: A network interface between an internal bus and an external bus architecture having one or more external buses includes an external interface engine and an internal interface. The external interface engine (EIE) is coupled to the external bus architecture, where the external interface engine communicates over the external bus architecture in accordance with one or more bus protocols. The internal interface is coupled to the external interface engine and the internal bus, where the internal interface buffers network data between the internal bus and the external bus architecture. In one embodiment, the internal interface includes an internal interface (IIE) coupled to the internal bus, where the IIE defines a plurality of queues for the network data. An intermediate memory module is coupled to the IIE and the EIE, where the intermediate memory module aggregates the network data in accordance with the plurality of queues.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communications fabric. A first functional block communicates a single request fully describing attributes of a two-dimensional data block across the communication fabric to a second functional block capable of decoding the single request to obtain the attributes of the two-dimensional data block. At least one of the functional blocks transmits data associated with the single request across the communication fabric.

Abstract: A network interface device couples a host computer to a network. The network interface device includes a processor and a DMA controller. The processor causes the DMA controller to perform multiple DMA commands before the processor takes a particular software branch. The processor issues the DMA commands by placing the DMA commands in a memory and then pushing values indicative of the DMA commands onto a DMA command queue. The values are popped off the DMA command queue and are executed by the DMA controller one at a time. The DMA commands are executed in the same order that they were issued by the processor. The processor need not monitor multiple DMA commands to make sure they have all been completed before the software branch is taken, but rather the processor pops a DMA command complete queue to make sure that the last of the DMA commands has been completed.

Abstract: A parallel processing system includes a plurality of stages operatively coupled in parallel and operating simultaneously. Each stage including a process unit generating a predetermined function and a buffer coupled via a slow output and a slow input ports to the process unit. The buffer also includes a fast input port and a fast output port. A controller drives the buffer to operate in a Slow Read Phase when data is written from the buffer into the process unit, a Slow Write Phase when data is written into the buffer from the process unit, a Fast Write Phase when data is written at a fast rate into the buffer and a Fast Read Phase when data is read from the buffer.

Abstract: Apparatus and method for carrying out a DMA transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the parameters for a transfer of a block of data are provided or the status of the transfer of a block of data is to be written by the DMA controller.

Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Abstract: A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a second set of signal lines to receive a grant associated with the data transfer request. A bus master unit (BMU) is coupled with the CSL through the first set of signal lines and the second set of signal lines. The BMU is connected to the CSI bus. The BMU arbitrates to take control of the CSI bus on behalf of the CSL enabling the CSL to perform data transfer to or from the CSI bus bypassing the processor.

Abstract: It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

Abstract: A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

Abstract: A system balances bandwidth used by a data stream. The system receives data in the data stream and partitions the data into bursts. The system then identifies whether a size of a current one of the bursts is less than a size of a maximum burst associated with the data stream and schedules an additional burst in the data stream when the current burst size is less than the maximum burst size. The system transmits the current burst and the additional burst to balance bandwidth used by the data stream.

Abstract: Transition signal control for creating asynchronous timing is provided using a transition signal control circuit, which includes Muller C elements each with an inverter. The control device is constituted by a machine ring including n-stages of transition signal control circuits, a state ring including k-stages of transition signal control circuits, and a synchronous circuit for synchronizing with the machine ring by receiving a vector which is output from the state ring. When the output vector of the state ring is received, the synchronous circuit outputs a vector to the machine ring. The output vector of the machine ring and the output vector of the state ring create timings for controlling the processor, for example, asynchronously, and these timings are input to the instruction decoder, for example.

Abstract: A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a streaming interface. The I/O interface includes a streaming interface for transferring streamed data from the streaming data bus to the core-processing engine, a DMA interface for transferring DMA data from the DMA data bus to the core-processing engine, and an arbiter for coordinating data transfer with the core-processing engine between the streaming interface and DMA interface. The arbiter may operate in a split-bus-mode wherein the arbiter performs the address phase for more than one channel prior to entering into the data phase. The flexible I/O interface may include a common address bus and data bus between the processing engine and the interfaces. Alternatively, a switching fabric may couple separate address and data buss of the interfaces with the processing engine.

Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.

Abstract: Disclosed is a programmable buffer circuit (16) for interfacing a CPU (12) to a plurality of channel interfaces (14). The buffer circuit includes a dual port memory (18) having a first port coupled to a CPU data bus and a second port coupled to a channel data bus that serves the plurality of channel interfaces. The buffer circuit further includes an arbitrator (24) for arbitrating access to the dual port memory by individual ones of the channel interfaces over the channel data bus; an address generator (26) for generating dual port memory addresses for reading and writing data using the CPU data bus and the channel data bus; and a control unit (20) and allocator (22) that are programmable by the CPU for specifying individual ones of buffer locations and sizes within the dual port memory for individual ones of the channel interfaces, and for enabling and disabling individual ones of the buffers.

Abstract: A processor may include a processor core, which interprets and executes instructions, and a system bus interface, which enables the processor to communicate with a system. The system bus interface may include a fill bus and a DMA bus. The system bus interface may include a bridge between the fill bus and the DMA bus which enables the system bus interface to re-route information placed on the fill bus onto the DMA bus and back into the core.

Abstract: The present invention is a high speed serial memory interface system and method that facilitates efficient communication of information between a system controller operating at a relatively high speed serial communication rate and a memory array operating at a relatively slow speed serial communication rate. In one embodiment the present invention is a high speed serial memory interface system with an information configuration core for coordinating proper alignment of information communication signals, a system interface for communicating with a system controller, and a memory array interface for communicating with a memory array. A memory module array for storing information and a high speed serial memory interface system for providing interface configuration management are integrated on a single substrate.

Abstract: A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.

Abstract: Peer-to-peer Direct Memory Access (DMA) permits the efficient transfer of data from one DMA capable Application Specific Integrated Circuit (ASIC) block to another without accessing memory. The peer-to-peer transfer can be done over a standard AMBA AHB bus architecture without side band signals and without violating the AHB specification.

Abstract: A method, apparatus, and computer instructions for managing direct memory access transfers. Monitoring is performed for an event to pass ownership of a direct memory access resource to a new thread. A buffer of the new thread is added by an operating system component to the end of a direct memory access chain of requests from the current thread. The addition of this buffer to the end of a direct memory access chain provides an anchor point for the new thread to add additional requests for the direct memory access resource.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Abstract: A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.