Abstract: An electronic device includes: a memory configured to a program; and one or more processors configured to execute the program stored in the memory. The one or more processors are connected to a first circuit and a second circuit, the first circuit being configured to execute a first operation cyclically and output an interrupt signal corresponding to the first operation, the second circuit being configured to execute a second operation in response to an operation instruction. In response to receiving the interrupt signal, the one or more processors output the operation instruction to the second circuit such that the second operation is not executed in a period in which the first operation affects the second operation.

Abstract: In an embodiment a system on chip includes at least one master device, at least one slave device, a connection interface configured to route signals between the at least one master device and the at least one slave device, the connection interface configured to operate according to configuration parameters, and a configuration bus connected to the connection interface, wherein the configuration bus is configured to deliver new configuration parameters to the connection interface so as to adapt operation of the connection interface.

Abstract: A sensor module includes a first sensor device that outputs first measurement data from a first measurement circuit receiving a signal from a first sensor element and performing a measurement process, a second sensor device that outputs a second measurement circuit receiving a signal from a second sensor element and performing a measurement process, and a microcontroller that receives the first measurement data and the second measurement data, in which the first sensor device includes a first terminal that is used for input of an external synchronization signal or a synchronization signal which is a signal based on the external synchronization signal, and input or output of a communication signal, and the second sensor device includes a second terminal that is used for input of the synchronization signal, and input or output of the communication signal.

Abstract: An integrated circuit (IC) includes circuitry configured to, drive a flash unit comprising at least one light-emitting device, by providing a supply voltage to the flash unit based on an external input power source or a battery, the supply voltage being provided along one of a plurality of different current paths corresponding to a plurality of operation states, no voltage being received from the external input power source in a first operation state among the plurality of operation states, a first voltage level being received from the external input power source in a second operation state among the plurality of operation states, and a second voltage level being received from the external input power source in a third operation state among the plurality of operation states, and charge the battery based on an charging voltage received from the external input power source.

Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

Abstract: A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.

Abstract: A system component, including an interface for a data bus, a defined communication protocol being used on the data bus which determines the data sequence of access requests for sending and receiving data. The data of an access request includes pieces of information about the access direction. The system component includes a register unit including data registers. The system component includes a processing unit for the data of an access request. The interface is optionally operable in a first or a second operating mode. In the first operating mode, the data of an access request is supplied to the register unit to identify a register address, so that the corresponding read or write access takes place on the identified data register. In the second mode, the data of an access request is supplied to the processing unit and the corresponding read or write access is handled by the processing unit.

Abstract: An electronic device configured to communicate with a host includes: a detecting logic configured to receive an initial command signal and a first completion signal according to the initial command signal after a connection of the host to the electronic device is established, and transmit a detection signal based on a signal transmission policy of the host that has been detected based on the initial command signal and the first completion signal; and a transmitting logic configured to transmit a second completion signal to the host based on the detection signal, wherein the signal transmission policy is different depending on whether the first completion signal is received in response to the second completion signal.

Abstract: A request to read data stored at a memory sub-system can be received. A determination can be made of whether the data is stored at a cache of the memory sub-system. Responsive to determining that the data is not stored at the cache of the memory sub-system, the data can be obtained from a memory component of the memory sub-system. A first priority indicator can be assigned to a fill operation associated with the data that is obtained from the memory component. A second priority indicator can be assigned to the request to read the data. A schedule of executing the fill operation and the request to read the data can be determined based on the first priority indicator and the second priority indicator.

Abstract: A method, computer program product, and computing system for establishing a connection between a virtualization device and a virtual machine infrastructure. The virtualization device may be configured to be communicatively coupled to one or more PCIe devices. A virtual machine may be executed on the virtual machine infrastructure. Control of the virtualization device may be passed through the virtual machine infrastructure to the virtual machine.

Abstract: Within a memory system, architecture and operations for processing commands in a parity cache scheme support more open blocks taking into account cost and performance. Dynamic random access memory space holds parity buffers of all open blocks and communicates with a cache and cache controller. An open block queue (OBQ) accumulates commands in separate queues for each open block to increase cache hit rate. Open block counters keep track of the number of commands for each OBQ to facilitate arbitration. A unique identification (ID) is given for each open block.

Abstract: A computing device, method and system to implement an adaptive compression scheme in a network fabric. The computing device may include a memory device and a fabric controller coupled to the memory device. The fabric controller may include processing circuitry having logic to communicate with a plurality of peer computing devices in the network fabric. The logic may be configured to implement the adaptive compression scheme to select, based on static information and on dynamic information relating to a peer computing device of the plurality of peer computing devices, a compression algorithm to compress a data payload destined for the peer computing device, and to compress the data payload based on the compression algorithm. The static information may include information on data payload decompression supported methods of the peer computing device, and the dynamic information may include information on link load at the peer computing device.

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract: The invention relates to an apparatus, a device and a method. The apparatus is configured for providing an address to a device attachable with the apparatus. The apparatus comprises at least one connector capable of receiving the device, an address composer for producing an address signal, and an address line in the connector for providing the address signal to the device, the address signal being indicative of an address to be used by the device when attached with the apparatus. The address composer is configured to generate the address signal as an analogue address signal.

Abstract: In accordance with embodiments of the present disclosure, an adapter for different types of devices that are defined by a full set of capabilities for a communication protocol may include one or more ports, wherein each of the one or more ports is configured to receive one of the different types of devices, and a device controller communicatively coupled to the one or more ports. The device controller may be configured to, when one of the different types of devices is received by the one or more ports obtain information related to a detection of the one of the different types of devices and, based on the information related to the detection, expose a subset of capabilities from the full set of capabilities to a bus of the communication protocol, wherein the subset of capabilities is defined by the one of the different types of devices for the communication protocol.

Abstract: An apparatus and method of adding thin client functionality are disclosed. One example method provides generating a call function directed to an electronic device and at least one peripheral device. The method also includes redirecting the call function to an auxiliary device, extracting payload data from information sent to the at least one peripheral device, discarding values outside a previously negotiated range from the extracted payload data, performing at least one of incrementing and decrementing the remaining values of the payload data to create a data subset, and redirecting the data subset to at least one other peripheral device resulting in output information being sent to the at least one other peripheral device.

Abstract: A method of reading data from a first memory device includes generating a first read command based on a first request which requests to generate the first read command for first data stored in a first address region of the first memory device, generating a second read command for second data stored in a second address region of the first memory device, generating a third read command based on a second request which requests to generate the third read command for third data stored in a third address region of the first memory device, executing the first read command and the third read command to read the first data and the third data, respectively, from the first memory device, and after the executing the first read command and the third read command, executing the second read command to read the second data from the first memory device.

Abstract: A processing system having a multilevel cache hierarchy employs techniques for repurposing dead cache blocks so as to use otherwise wasted space in a cache hierarchy employing a write-back scheme. For a cache line containing invalid data with a valid tag, the valid tag is maintained for cache coherence purposes or otherwise, resulting in a valid tag for a dead cache block. A cache controller repurposes the dead cache block by storing any of a variety of new data at the dead cache block, while storing the new tag in a tag entry of a dead block tag way with an identifier indicating the location of the new data.

Abstract: An apparatus and method of adding thin client functionality are disclosed. One example method provides generating a call function directed to an electronic device and at least one peripheral device. The method also includes redirecting the call function to an auxiliary device, extracting payload data from information sent to the at least one peripheral device, discarding values outside a previously negotiated range from the extracted payload data, performing at least one of incrementing and decrementing the remaining values of the payload data to create a data subset, and redirecting the data subset to at least one other peripheral device resulting in output information being sent to the at least one other peripheral device.

Abstract: In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.

Abstract: A system for delivering a voltage to at least one power domain has at least one component. Each power domain functions according to at least two operating points, each operating point requiring a distinct supply voltage. The system includes at least two power supply units, alternatively delivering controllable supply voltages. The system also includes a control unit that selects one of the power supply units to be connected to a power domain, based on a current operating point of the power domain. The control unit also controls the supply voltage delivered by the selected power supply unit, to deliver the required voltage level associated with the current operating point of the power domain.

Abstract: A bus control device includes a plurality of bus masters classified into a plurality of groups according to a priority level, a plurality of group buses each group bus being connected to a corresponding group of bus masters and assigned with a priority level determined according to the priority levels of the corresponding group of bus masters, an upper priority bus that arbitrates a plurality of bus obtaining requests received from the plurality of bus maters via the plurality of group buses, a plurality of masks respectively provided for the plurality of bus masters to mask the bus obtaining request addressed to the corresponding group bus from the corresponding bus master, and a plurality of mask controllers respectively provided for the plurality of group buses to output at least one mask signal that controls operation of at least one corresponding mask connected to the corresponding group bus.

Abstract: Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.

Abstract: Techniques are described for controlling power consumption in a peer-to-peer communication system. In accordance with various examples, the techniques include determining a power save mode of a first node, determining a power save mode of a second node, determining a category of data connection between the first node and the second node, and adjusting a power save parameter of the first node based at least in part on the power save mode of the first node, the power save mode of the second node, and the category of data connection.

Abstract: A method, system and computer program product are provided for implementing shared adapter configuration updates concurrent with maintenance actions for a Single Root Input/Output Virtualization (SRIOV) adapter in a computer system. A configuration of the adapter is decoupled from the state of the adapter during a recovery period. When a configuration request is received, the configuration request is validated. Responsive to a valid configuration request, the saved configuration state of the adapter is updated. Once the adapter completes recovery, the adapter is restored to the new configuration instead of the configuration prior to failure.

Abstract: An apparatus and method of adding thin client functionality are disclosed. One example method provides generating a call function directed to an electronic device and at least one peripheral device. The method also includes redirecting the call function to an auxiliary device, extracting payload data from information sent to the at least one peripheral device, discarding values outside a previously negotiated range from the extracted payload data, performing at least one of incrementing and decrementing the remaining values of the payload data to create a data subset, and redirecting the data subset to at least one other peripheral device resulting in output information being sent to the at least one other peripheral device.

Abstract: This disclosure provides an architecture for sharing information between network security administrators. Events converted to a normalized data format (CCF) are stored in a manner that can be queried by a third party (e.g., an administrator of another, trusted network). Optionally made available as a service, stored event records can be sanitized for third party queries (e.g., by clients of a service maintaining such a repository). In one embodiment, each contributing network encrypts or signs its (sanitized) records using a symmetric key architecture, the key being unique to the contributing network. This key is used (e.g., by the repository) to index a set of permissions or conditions of the contributing network in servicing any query, e.g., by matching a stored hash of the event record or by decrypting the record. The information sharing service can optionally be provided by a hosted information security service or on a peer-to-peer basis.

Abstract: Techniques are disclosed to implement a scheduling scheme for a crossbar scheduler that provides distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a distributed switch. Input and output ports are grouped and assigned a respective arbiter. The input group arbiters communicate requests indicating a count of respective ports having data packets to be transmitted via one of the output ports. The output group arbiter attempts to accommodate the requests for each member of an input group before proceeding to a next input group.

Abstract: A backplane controller to couple to a carrier interface and a plurality of host controllers of different types. The backplane controller is to identify a host controller corresponding to a type of a storage device of a storage device carrier. The storage device carrier is to interface with the carrier interface. The backplane controller is to arbitrate multiplexing of communication between the carrier interface and the identified host controller.

Abstract: An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.

Abstract: A data processing device includes a master arbitrating unit assigning information to a command sent from a selected bus master, a data buffer, a write command buffer, a read command buffer, a write data reception completion notification control unit issuing a signal indicating that storing of write data is complete, and a command order determining unit selecting whichever of a first command and a second command coming earlier in an order identified with the information, the first information being information for which the completion is indicated by the signal and a second command being a read command.

Abstract: This disclosure provides a network security architecture that permits installation of different software security products as virtual machines (VMs). By relying on a standardized data format and communication structure, a general architecture can be created and used to dynamically build and reconfigure interaction between both similar and dissimilar security products. Use of an integration scheme having defined message types and specified query response framework provides for real-time response and easy adaptation for cross-vendor communication. Examples are provided where an intrusion detection system (IDS) can be used to detect network threats based on distributed threat analytics, passing detected threats to other security products (e.g., products with different capabilities from different vendors) to trigger automatic, dynamically configured communication and reaction.

Abstract: A method includes receiving feedback information indicative of an overload condition from an arbiter. The method further includes deprioritizing a routing bus based on the received feedback information and selecting a routing bus to use to send a transaction across a system-on-chip (SOC).

Abstract: Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.

Abstract: Method, system, bus arbitration device for accessing a memory are described. According to one embodiment, priorities of N function modules accessing the memory are compared to obtain location information of a function module with the highest priority. A bus of the function modules accessing the memory is switched to the function module with the highest priority by performing logic operation on the location information and bus information of each function module. Further, a bus arbitration device including a priority arbitration unit and a bus switching unit is described.

Abstract: This application relates to systems and methods for controlling the flow of transport layer packets (TLP) in a peripheral component interconnect express (PCIe)-based environment. In an exemplary embodiment, an arbiter in a PCIe device determines the amount of data, if any, that should be expected in response to transmission of a particular TLP. If a receive buffer of the PCIe device has enough available space for storing the expected data, the arbiter permits transmission of the particular TLP. If the receive buffer does not have enough available space for storing the expected data, the arbiter suppresses transmission of the particular TLP until the receive buffer has enough available space. The exemplary embodiment may improve data flow through the PCIe environment by reducing fragmented transfers of data.

Abstract: Systems and methods presented herein provide for the management of link rates for connecting targets devices (e.g., storage devices) to initiators (e.g., host systems). In one embodiment, an expander includes a plurality of PHYs including a PHY having a first link rate and a PHY having a second link rate that is different than the first link rate. The expander also includes a link manager communicatively coupled to the PHYs and operable to process a connection request from an initiator for the first link rate, extract a timer from the connection request, and determine whether the first link rate is available. The link manager is also operable to start the timer when the link manager determines that the first link rate is unavailable and issue a response to the initiator to inform the initiator that the timer has started and that connection at the first link rate is delayed.

Abstract: A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path.

Abstract: Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.

Abstract: Apparatus and associated methods for a simplified multi-client initiator/target within a SAS device. Features and aspects hereof provide a simplified initiator/target component to enable cost reduction and simplification of SAS devices requiring only limited initiator/target functionality. In one embodiment, a SAS expander may incorporate simplified SSP/STP/SMP initiator/target features and aspects hereof to permit simple management of devices coupled to the expander or coupled downstream through other expanders. The simplified multi-client initiator/target suffices for simple management functions while reducing cost and complexity of the SAS expander. Features and aspects hereof may be implemented with shared circuits for each of multiple client protocols coupled with firmware operable in a general or special purpose processor embedded in the SAS device.

Abstract: Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.

Abstract: Certain aspects of an apparatus and method for interconnection may include an interconnection section, a request processing section and a response processing section. The interconnection section may be configured to transfer a request from a master interface bus to a slave interface bus and to transfer a response from the slave interface bus to the master interface bus. A slot number within the request specifies a time slot during which the interconnection section may be permitted to transfer the response to the master interface bus. The request commands the processing section to load the slot number into a management table. The response commands the response processing section to read out the slot number from the management table.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: According to one embodiment, an electronic device forming a first communication path which couples a first interface of a high-rank unit and a second interface of a mid-rank unit and a second communication path which couples a third interface of the mid-rank unit and a fourth interface of a low-rank unit, while cutting off a third communication path which couples the first interface and the fourth interface, in an ordinary state. When data needs to be write from the high-rank unit to the low-rank unit, the electronic device forming the third communication path and cutting off the first communication path and the second communication path.

Abstract: A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state.

Abstract: A television includes at least two ports (e.g. HDMI ports). The television polls the ports before presenting a user interface that displays some or all of the ports and before toggling between any two of the ports. The polling ascertains whether a device is connected to each of the ports and whether the device is powered. The television modifies the display and/or toggling based on the current state of each port. For example, in toggling, ports that are not connected and ports that are connected to inactive devices are skipped. In another example, when displaying a list of ports, only those ports that are connected to devices appear in the list.

Abstract: In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.

Abstract: A method, node device, signal, and instruction set to reduce the size of data packets in a telecommunications network. The invention provides a solution wherein a size of SDU position identifiers in a header of a packet data unit is optimized depending on the actual size of the packet data unit, reducing the amount of data sent in the telecommunication network.

Abstract: Embodiments of the invention describe an apparatus, system and method for slave devices to “self-select” their own Inter-Integrated Circuit/System Management Bus (I2C/SMBus) slave addresses upon initialization. Embodiments of the invention describe logic/modules to retrieve a first SMBus slave address included in non-volatile memory for a slave device, wherein said slave device is communicatively coupled to a host system via an SMBus. A first message (e.g., a ping) is transmitted to the first SMBus slave address via the SMBus. If a response to the first message is not received, the first SMBus slave address is selected for the slave device. If a response to the first message is received, the first SMBus slave address is changed by an offset value to determine a second SMBus slave address for transmitting a second message via the SMBus.