Arbitration Patents (Class 710/309)
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Publication number: 20130227191Abstract: An image forming apparatus according to the present disclosure includes: a first IC chip; a second IC chip connected to the first IC chip via a serial bus; and a memory that is either connected to or included in the first IC chip. The first IC chip includes: a first internal bus; a memory controller of the memory; a first processing circuit which outputs an access request to the memory; plural buffers corresponding to plural arbitration priority degrees of the first internal bus, and a request classifying circuit which identifies an arbitration priority degree of a requester of the access request received from the second IC chip and causes a buffer corresponding to the identified arbitration priority degree to buffer the access request. The first internal bus performs arbitration of access requests from the first processing circuit and the plural buffers in accordance with the arbitration priority degrees.Type: ApplicationFiled: February 22, 2013Publication date: August 29, 2013Applicant: KYOCERA Document Solutions Inc.Inventor: KYOCERA Document Solutions Inc.
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Patent number: 8521937Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.Type: GrantFiled: February 16, 2011Date of Patent: August 27, 2013Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Research & Development) LtdInventors: Ignazio Antonino Urzi, Philippe D'Audigier, Olivier Sauvage, Stuart Ryan, Andrew Michael Jones
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Patent number: 8516177Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.Type: GrantFiled: April 20, 2012Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Carl A. Bender, Jeffrey C. Hanscom, Thomas D. Needham
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Patent number: 8495265Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.Type: GrantFiled: June 1, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Carl A. Bender, Jeffrey C. Hanscom, Thomas D. Needham
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Patent number: 8468283Abstract: An arbitration diagnostic circuit and method provide diagnostic information in arbitration-based systems and/or provide detection of and response to excessive arbitration delays. For example, in one embodiment, an arbitration diagnostic circuit maintains a chronological memory trace of arbitration events, including resource request events and corresponding resource grant events for two or more entities having arbitrated access to a shared resource. The trace, which may be regarded as a running, ordered list, may comprise time-stamped event identifiers, which aid the analysis of arbitration related errors or failures. Indeed, in one or more embodiments, an arbitration diagnostic circuit is configured to track elapsed times for resource requests, and to detect resource grant delay violations.Type: GrantFiled: June 1, 2006Date of Patent: June 18, 2013Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventor: John Stewart Petty, Jr.
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Patent number: 8468282Abstract: An arbitration device includes an arbitration section, a counter, and a changing section. While write request signals and read request signals for a transfer path, are inputted from request sources, the arbitration section arbitrates an order that the write and read request signals use the transfer path, and when arbitration is settled, outputs use permission signals to the request sources. The changing section changes a time from outputting of the write request signals until inputting of the write request signals to the arbitration section, and/or a time from outputting of the use permission signals for the write request signals until inputting of the use permission signals to the request sources.Type: GrantFiled: June 8, 2010Date of Patent: June 18, 2013Assignee: Fuji Xerox Co., Ltd.Inventor: Yoshinori Awata
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Patent number: 8423693Abstract: Provided is an arbitration circuit included in a host controller that can be connected to a plurality of external devices via a plurality of pipe control circuits. The arbitration circuit includes an available state information storage unit that stores available state information. The available state information indicates an available state of the plurality of pipe control circuits and is updated by the pipe control circuit by a unit of data transfer of a predetermined communication size. The arbitration circuit further includes an arbitration unit that refers to the available state information storage unit, selects the arbitrary pipe control circuit from the available pipe control circuit, and allocates the selected pipe control circuit to the external device, while updating the available state information storage unit.Type: GrantFiled: October 12, 2010Date of Patent: April 16, 2013Assignee: Renesas Electronics CorporationInventor: Kunihiro Kondo
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Publication number: 20130073773Abstract: An access control apparatus includes an external bus control unit that controls an external bus for transmitting and receiving data to and from an external device. The external bus control unit includes: a plurality of storage units disposed corresponding to the external device for temporarily storing data from an internal bus; and an arbitration unit that selects a storage unit for transferring data to the external bus from the plurality of storage units in response to an access request from the internal bus and outputs the data stored in the selected storage unit to the external bus.Type: ApplicationFiled: September 13, 2012Publication date: March 21, 2013Inventor: Yuuji MATSUDA
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Patent number: 8386665Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: June 28, 2011Date of Patent: February 26, 2013Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 8364926Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.Type: GrantFiled: February 29, 2012Date of Patent: January 29, 2013Assignee: Rambus Inc.Inventors: Craig E. Hampel, Frederick A. Ware
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Publication number: 20130019030Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.Type: ApplicationFiled: June 28, 2012Publication date: January 17, 2013Inventors: Hung-Ju Huang, Shu-An Huang Ho, Jen-Min Yuan
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Patent number: 8335229Abstract: In some embodiments, a method for supporting multiple devices on a high speed physical link may be described. An embedded device may assert a link request pin to request to transmit data on a multi-point communications link that may serve a plurality of embedded devices. A controlling device may receive the link request signal. When the controlling device finishes sending data on the link, it may address the plurality of embedded devices in a round robin format and may determine which device asserted the link request pin. The embedded device that asserted the link request pin may send an acknowledgement signal to the controlling device when it is addressed.Type: GrantFiled: February 4, 2010Date of Patent: December 18, 2012Assignee: Marvell International Ltd.Inventors: Peter D. Mueller, Mark N. Fullerton, Nir Nossenson
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Patent number: 8327054Abstract: A data check circuit comprising: a request signal output circuit configured to output a request signal for requesting occupation of a bus to an arbitration circuit configured to arbitrate the occupation of the bus, when a CPU connected, as a bus master, with the bus for accessing a memory outputs an instruction signal for providing an instruction for starting detection of whether or not data stored in the memory is correct; a data acquisition circuit configured to acquire data stored in the memory through the bus, when the arbitration circuit outputs a permission signal for permitting the occupation of the bus based on the request signal; and a data processing circuit configured to perform processing for detecting whether or not the acquired data is correct, the acquired data acquired by the data acquisition circuit.Type: GrantFiled: June 2, 2010Date of Patent: December 4, 2012Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.Inventor: Naoyuki Ogino
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Publication number: 20120297106Abstract: A method and system for dynamically managing a bus within a portable computing device (“PCD”) are described. The method and system include monitoring software requests with a bus manager. The bus manager determines if a software request needs to be converted into at least one of an instantaneous bandwidth value and an average bandwidth value. The bus manager then converts the software requests into these two types of values as needed. The bus manager calculates a sum of average bandwidth values across all software requests in the PCD. With these values, the bus manager may dynamically adjust settings of the bus based on instantaneous or near instantaneous demands from the master devices. This dynamic adjustment of the bus settings may afford more power savings for the PCD during low loads or during sleep states.Type: ApplicationFiled: May 16, 2011Publication date: November 22, 2012Applicant: QUALCOMM INNOVATION CENTER, INC.Inventors: Robert N. Gibson, Joshua H. Stubbs
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Patent number: 8316200Abstract: A microcomputer includes a flash memory and a flash controller that controls access to the flash memory, the flash memory including a protection information storage section that stores protection information, the protection information indicating whether or not access to a given area of the flash memory is available; the flash controller including a flash protection section that performs a protection process relating to access to a given area of the flash memory based on the protection information; and the flash protection section performing the protection process relating to access to the flash memory when an access target is data.Type: GrantFiled: April 9, 2008Date of Patent: November 20, 2012Assignee: Seiko Epson CorporationInventors: Hiroki Matsuoka, Keisuke Hashimoto
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Patent number: 8301820Abstract: A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.Type: GrantFiled: June 12, 2009Date of Patent: October 30, 2012Assignee: STMicroelectronics Belgium N.V.Inventor: Rudolph Alexandre
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Patent number: 8301821Abstract: A communication module for connecting a serial bus, which transmits data in packets, to a plurality of system buses of a gateway, which transmit data word by word, the communication module having a communication protocol unit, which is connected to the serial bus, for converting between data packages and messages, which are respectively made up of a plurality of data words, a message relaying unit for relaying messages between at least one message memory and the communication protocol unit, as well as buffer memories, a plurality of interface units, which are respectively connected to an associated system bus of the gateway, each interface unit being connected to at least one associated buffer memory, which stores a message temporarily, a transmission of data words via a plurality of system buses and their associated interface units from and to the buffer memories of the interface units taking place simultaneously, without delay.Type: GrantFiled: May 3, 2007Date of Patent: October 30, 2012Assignee: Robert Bosch GmbHInventors: Markus Ihle, Tobias Lorenz, Jan Taube
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Patent number: 8285908Abstract: A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses.Type: GrantFiled: January 24, 2010Date of Patent: October 9, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Amar Nath Deogharia, Hemant Nautiyal
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Patent number: 8285907Abstract: Methods and apparatus, including computer program products, implementing techniques for forming an Advanced Switching (AS) packet by applying AS path binding information to a packet received over a Peripheral Component Interconnect-Express (PCIe) fabric according to a downstream port identifier associated with the packet, and sending the AS packet to an AS fabric. Methods and apparatus, including computer program products, implementing techniques for processing an AS packet received over an AS fabric by comparing an AS payload of the AS packet with one or more memory spaces associated with port identifiers, determining whether the AS payload comprises a base packet to be transmitted to the PCIe fabric based on the comparison, and if so, removing an AS header from the AS packet to reveal the base packet.Type: GrantFiled: December 10, 2004Date of Patent: October 9, 2012Assignee: Intel CorporationInventors: Christopher L. Chappell, James Mitchell
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Patent number: 8271673Abstract: A system and method are disclosed for processing commands to network target devices through a SCSI router in a Fiber Channel network having a plurality of Fiber Channel hosts. The system and method are implemented in the SCSI router and include receiving a command from one of the plurality of Fiber Channel hosts and, if the command is for a transfer of data larger than a threshold size, streaming the data to the target device. If a preset size memory block is free, a data block is requested from the Fiber Channel host that issued the command. Otherwise, the method of this invention waits to request the data block until the preset size memory block is free. The SCSI router receives the data block and stores the data block in a FIFO queue. The method of this invention repeats until an initial number of data blocks are stored in the FIFO queue. The command and the first data block received are forwarded to the network target device.Type: GrantFiled: August 9, 2004Date of Patent: September 18, 2012Assignee: Crossroads Systems, Inc.Inventors: Keith M. Arroyo, Stephen K. Wilson
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Patent number: 8244948Abstract: A first SAS expander including at least phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.Type: GrantFiled: June 1, 2010Date of Patent: August 14, 2012Assignee: LSI CorporationInventors: Stephen B. Johnson, Christopher McCarty
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Patent number: 8166339Abstract: An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.Type: GrantFiled: March 11, 2009Date of Patent: April 24, 2012Assignee: Sony CorporationInventor: Hiroshi Kyusojin
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Patent number: 8156260Abstract: A data transfer device for performing direct memory access (DMA) transfer of data stored in a storage unit to a plurality of other devices includes: a plurality of channel units arranged to correspond to the other devices, the channel units retaining DMA transfer instructions, and outputting number of the DMA transfer instructions retained; a plurality of priority controllers for determining priorities of the channel units on the basis of the number of the DMA transfer instructions retained in the channel units, respectively; an arbiter for selecting one of the DMA transfer instructions retained in one of the channel units on the basis of the priorities determined by the priority controller; and a data transfer processor for performing DMA transfer of data stored in the storage unit to one of the other devices in accordance with the DMA transfer instruction selected by the arbiter.Type: GrantFiled: July 14, 2009Date of Patent: April 10, 2012Assignee: Fujitsu LimitedInventor: Yuichi Ogawa
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Publication number: 20120079159Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.Type: ApplicationFiled: March 4, 2011Publication date: March 29, 2012Inventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
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Patent number: 8108583Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.Type: GrantFiled: March 23, 2005Date of Patent: January 31, 2012Assignee: Emulex Design & Manufacturing CorporationInventors: Shawn Adam Clayton, Brian Mark Fortin, Daniel Brian Willie, John Leland Wood
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Patent number: 8099539Abstract: A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a memory clock and a host clock based on an arbitration status, driving a final output on an interface to provide glitchless switching of an interface signal, connecting the interface signal to a tri-state buffer, and setting the direction of a data and address bus based on the connection of the interface signal to the tri-state buffer. The method may include applying a fair arbitration policy to ensure that none of the devices coupled to the interface signal and application threads running on processor requiring data from different devices are starved.Type: GrantFiled: March 10, 2008Date of Patent: January 17, 2012Assignee: LSI CorporationInventors: Rajendra Sadanand Marulkar, Gurvinder Pal Singh
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Patent number: 8095744Abstract: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.Type: GrantFiled: November 7, 2008Date of Patent: January 10, 2012Assignee: Panasonic CorporationInventors: Isao Kawamoto, Yoshiharu Watanabe
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Publication number: 20110276739Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: ApplicationFiled: July 22, 2011Publication date: November 10, 2011Applicant: ITE TECH. INC.Inventor: Ching-Min Hou
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Patent number: 8051233Abstract: A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the integrated Ethernet controllers may be identified based on information within the received data. The particular one of the integrated Ethernet controllers may be granted access to a shared resource within the single chip. The access to the shared resource may be granted using at least one semaphore register within the shared resource. The particular one of the integrated Ethernet controllers may be granted access to the single bus interface. The information may include a bus identifier, a bus device identifier and/or a bus function identifier. The shared resource may include a nonvolatile memory (NVM).Type: GrantFiled: January 5, 2010Date of Patent: November 1, 2011Inventors: Steven B. Lindsay, Gary Alvstad
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Patent number: 8046513Abstract: An operating method applied to an out-of-order executive bus system includes: according to dependency constraints, linking requests using the bus system to form dependency request links having an order; and processing the order of the requests according to the dependency request links. In addition, a bus system is provided. The bus system includes a request queue and a dependency request link generator. The request queue receives and stores a newly received request including at least a link tag. The dependency request link generator generates N dependency request links according to dependency constraints of N link tags of the newly received request, where N is any positive integer. Each link tag of the newly received request is implemented to indicate a link relation with respect to an order of the newly received request and a plurality of unserved requests preceding the newly received request.Type: GrantFiled: July 22, 2009Date of Patent: October 25, 2011Assignee: Realtek Semiconductor Corp.Inventor: Yu-Ming Chang
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Patent number: 8041868Abstract: A combination includes a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus, a second bus master coupled to the first bus to output a second signal group including at least one of signals onto the first bus, an interconnect section coupled between the first bus and a second bus to receive the first and second signal groups and to output a third signal group including at least one of signals onto the second bus, and a bridge section coupled between the second bus and a third bus to receive the third signal group and to output a fourth signal group including at least one of signals onto the third bus free from performing a selecting operation for the third signal group.Type: GrantFiled: July 13, 2010Date of Patent: October 18, 2011Assignee: Renesas Electronics CorporationInventor: Atsushi Kazama
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Patent number: 8041869Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.Type: GrantFiled: June 17, 2010Date of Patent: October 18, 2011Assignee: Koninklijke Philips Electronics N.V.Inventors: Bijo Thomas, Milind Manohar Kulkarni
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Patent number: 8028144Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.Type: GrantFiled: February 24, 2009Date of Patent: September 27, 2011Assignee: RAMBUS Inc.Inventors: Craig E. Hampel, Frederick A. Ware
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Patent number: 8010723Abstract: The present invention relates to a SPC comprising at least one data processing means for realizing a first data channel 1 and a second data channel 2, and comprising a data transmission means 3 which is connected to data channels 1,2 in a manner such that, using data transmission means 3, data may be transferred from at least one data channel 1, 2 to a higher-order device 5 that is connectable to the controller. The object of the present invention is to further increase the safety of safety controllers. This aim is achieved by providing an active data lock 4, using which it is possible to influence the data transmission—which may be realized using data transmission means 3—to higher-order device 5. As a result, only error-free data are sent via higher-order device 5 to external I/O assemblies.Type: GrantFiled: December 22, 2008Date of Patent: August 30, 2011Assignee: Robert Bosch GmbHInventors: Horst-Dieter Nikolai, Volker Rug
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Patent number: 8006014Abstract: A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple scheduled TLPs and DLLPs for transmission. A programmable storage element provides a value to control the selector. In one embodiment, the distinct priority rule employed by at least a first of the arbiters prioritizes TLPs higher than Ack/Nak DLLPs, and the distinct priority rule employed by at least a second of the arbiters prioritizes Ack/Nak DLLPs higher than TLPs. In one embodiment, at least a first arbiter prioritizes TLPs higher than Ack/Nak DLLPs and UpdateFC DLLPs, at least a second arbiter prioritizes Ack/Nak DLLPs higher than TLPs and UpdateFC DLLPs, and at least a third arbiter prioritizes UpdateFC DLLPs higher than TLPs and Ack/Nak DLLPs.Type: GrantFiled: July 24, 2009Date of Patent: August 23, 2011Assignee: VIA Technologies, Inc.Inventors: Yen-Ting Lai, Wen-Yu Tseng
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Patent number: 7990999Abstract: Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams.Type: GrantFiled: January 14, 2009Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Khee Wooi Lee, Mikal C. Hunsaker, Darren L. Abramson
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Publication number: 20110185102Abstract: A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses.Type: ApplicationFiled: January 24, 2010Publication date: July 28, 2011Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Amar Nath DEOGHARIA, Hemant NAUTIYAL
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Publication number: 20110179212Abstract: Systems and methods of bus arbitration for sideband signals in a multichip system are disclosed. An exemplary method comprises packaging at least one sideband signal as a micropacket. The method also comprises holding the micropacket in an outgoing sideband register. The method also comprises monitoring a bus for a quiescent state, the bus having a plurality of links to other chips in the multichip system. The method also comprises issuing the micropacket from the outgoing sideband register if the bus is in a quiescent state.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Inventor: Charles Andrew Hartman
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Patent number: 7970961Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: November 11, 2008Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 7966440Abstract: An image processing controller performs transmission and processing of image data by connecting an engine and a CPU connected via a chipset. A first controller controls communication with the chipset via a first PCI-Express I/F. A second controller controls communication with the engine when it is connected via a second PCI-Express I/F. A third controller controls communication with the engine when it is connected via a PCI I/F. The first controller receives, on behalf of the engine, an access from the CPU to the engine and inhibits a reference by the CPU to a resource connected to the image processing controller.Type: GrantFiled: May 6, 2008Date of Patent: June 21, 2011Assignee: Ricoh Company, LimtedInventor: Mutsumi Namba
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Patent number: 7937447Abstract: Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using input/output (I/O) buses such as PCI Express buses. The I/O buses are extended to allow interconnection between computer systems without having to introduce network infrastructure. A transfer controller supporting Direct Memory Access (DMA) is provided to allow even more efficient communication between computer systems.Type: GrantFiled: March 21, 2005Date of Patent: May 3, 2011Assignee: Xsigo SystemsInventors: Ariel Cohen, Shreyas Shah, Raymond Lim, Greg Lockwood
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Patent number: 7934043Abstract: A data processing apparatus contains a first bus connected to a first memory, a first central processing unit (CPU) being accessible to the first memory via the first bus, a first Direct Memory Access (DMA) controller being accessible to the first memory via the first bus, and a monitor circuit connected to the first bus and monitoring addresses transferred on the first bus. The addresses transferred on the first bus are transmitted from the first DMA controller to the first memory via the first bus. The monitor circuit compares the address transferred on the first bus with a preset monitor target address. The CPU acquires the comparison results by the monitor circuit. If the comparison results show an address match, then the CPU accesses the first memory. The CPU can in this way access the first memory at a correct timing.Type: GrantFiled: August 6, 2007Date of Patent: April 26, 2011Assignee: Renesas Electronics CorporationInventor: Kenichi Takeda
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Patent number: 7934046Abstract: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.Type: GrantFiled: July 2, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Adrian S Butter, Eric M Foster, Glenn D Gilda
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Publication number: 20110082961Abstract: The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems.Type: ApplicationFiled: September 28, 2010Publication date: April 7, 2011Inventors: Alexander L. Minkin, Steven L. Heinrich, Rajeshwaran Selvanesan, Stewart Glenn Carlton, John R. Nickolls
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Patent number: 7917706Abstract: A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its different inputs. The SDRAM controller has multiple inputs, at least one of which allows connections to multiple bus master devices. The SDRAM controller forms a queue of bus access requests, based amongst other things on a relative priority given to the input on which a request is received. When a request is received on an input which allows connections to multiple bus master devices, the SDRAM controller forms the queue of bus access requests, based amongst other things on a relative priority given to the bus master device which made the request.Type: GrantFiled: December 15, 2003Date of Patent: March 29, 2011Assignee: Altera CorporationInventor: Roger May
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Patent number: 7868892Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.Type: GrantFiled: September 24, 2008Date of Patent: January 11, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Hara, Hiroyuki Hamasaki, Mitsuhiro Saeki, Kazuhiro Hirade, Makoto Takano
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Patent number: 7865645Abstract: A bus arbiter includes an arbitration stop determining unit and a transaction arbitrating unit. The arbitration stop determining unit generates an arbitration stop signal based upon transaction grouping request signals which indicate whether successive transactions are requested. The transaction arbitrating unit selectively performs an arbitration operation based upon the arbitration stop signal.Type: GrantFiled: May 7, 2009Date of Patent: January 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Eui-Cheol Lim
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Patent number: 7861026Abstract: A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main masters on a bus. The burst access engine exchanges signals with the bus arbiter and an external memory controller. The signal relay device facilitates data transfer of large groups of read/write commands between the main masters and the external memory controller.Type: GrantFiled: April 3, 2009Date of Patent: December 28, 2010Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Yu-Chen Shen, Yi-Shin Li, Ming-Chung Hsu
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Publication number: 20100321394Abstract: An information processing device includes: a first processing unit which asserts a first chip select signal or a second chip select signal in accordance with an address space to access; and a second processing unit accessible by the first processing unit by a first access method or a second access method, wherein when asserting the first chip select signal, the first processing unit accesses the second processing unit by the first access method, and when asserting the second chip select signal, the first processing unit accesses the second processing unit by the second access method.Type: ApplicationFiled: June 9, 2010Publication date: December 23, 2010Applicant: Seiko Epson CorporationInventor: Toru Shinomiya
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Patent number: 7853737Abstract: A communication data processing device according to an aspect of the invention includes a memory storing data, a data bus transmitting data read from the memory, a plurality of buffer memories temporarily storing data from the memory via the data bus and being capable of receiving and providing data independently of each other, a bus arbiter arbitrating use of the data bus to control data read from the memory to the plurality of buffer memories, an aligner aligning input data in a sequence corresponding to a packet communication, and a selector selecting a buffer memory from the plurality of buffer memories to output data from the selected buffer memory toward the aligner.Type: GrantFiled: May 5, 2005Date of Patent: December 14, 2010Assignee: NEC Electronics CorporationInventor: Daisuke Kawakami