Abstract: An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an address corresponding to an access request to the second bus sent from a first bus, responsive to the access request, and a count value generator generating a count value up to the wait periodicity set to the number-of-waits setting circuit. A control signal holding circuit holds a control signal for holding a state of the second bus at the setting of the wait periodicity by the number-of-waits setting circuit during a count period of the count value generator and maintains the access state of the status controller. A clock control circuit divides a clock for the first bus according to the wait periodicity set and outputs the result of division to the second bus.

Abstract: A bus arbitration device includes a top arbiter, and the hierarchical bus arbitration device also includes a first arbiter. The said first arbiter arbitrates the first kind of requests, wherein the first kind of requests relates to the first kind of master units. The said second arbiter arbitrates the second kind of requests different from the first kind of requests, wherein the second kind of requests relates to the second kind of master units different from the first kind of master units. Wherein the said first arbiter and the said second arbiter are downward respectively from the top arbiter to form the hierarchical bus arbitration structure. Bus arbitration efficiency increases by this bus arbitration device.

Abstract: A multi-computer system has many processors that share peripherals. The peripherals are virtualized by hardware without software drivers. Remote peripherals appear to the operating system to be located on the local processor's own peripheral bus. A processor, DRAM, and north bridge connect to a south bridge interconnect fabric chip that has a virtual Ethernet controller and a virtual generic peripheral that act as virtual endpoints for the local processor's peripheral bus. Requests received by the virtual endpoints are encapsulated in interconnect packets and sent over an interconnect fabric to a device manager that accesses remote peripherals on a shared remote peripheral bus so that data can be returned. Ethernet Network Interface Cards (NIC), hard disks, consoles, and BIOS are remote peripherals that can be virtualized. Processors can boot entirely from the remote BIOS without additional drivers or a local BIOS. Peripheral costs are reduced by sharing remote peripherals.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”).

Abstract: A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.

Abstract: A method for reducing an amount of process data to be transferred from a field device, wherein the process data includes information concerning an operating condition of the field device, and/or information concerning process variables registered with the field device, and/or identification data of the field device. It is provided that process data occurring during an interval between two transfers of data is evaluated and stored, wherein the process data are reduced through the evaluating, and wherein the reduced process data is transferred to a process control station.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: A bus bridge interfaces a primary-side bus with a plurality of secondary-side buses. The primary side bus is a local bus in a system and the secondary-side buses are external buses connected to the system. The bus bridge supports a plurality of kinds of operations one of which is an operation related to a serial bus in accordance with IEEE1394. An access right is given equally to each of the secondary-side buses, when access demands to the primary-side bus are lodged from more than two of the secondary side buses at the same time, by not giving a priority to any one of the secondary side buses.

Abstract: A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several functions share a common PCIe interface logic. A predetermined number of function entities with logical gates, connected in daisy chain configuration, process incoming information, and a decision is made whether each function entity will generate a blocking control or a pass-through control. The error messages are aggregated across the function entities in a single clock cycle with the help of an error controller. The functions can be from IEEE 1394 interface, graphics display controller, sound card, PCIe switch, or PCIe to PCI bridge connection. Each function preferably has a different configuration and security level setting for error reporting and messaging.

Abstract: A bridge is disclosed. The bridge comprises a first interface having at least one multiplexed clock signal line. The multiplexed clock signal line outputs first and second control signals for respectively controlling the access to first and second devices coupled to the bridge. The bridge selectively outputs the first clock signal or the second clock signal to the multiplexed clock signal line to access the first device or the second device respectively.

Abstract: A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the efficiency of the bus system. A method including sending a read command and transferring bus control to another one of a plurality of masters before receiving the response to the read command.

Abstract: In one embodiment, a controller comprises one or more transaction queues, one or more age counter circuits, and a control circuit. The transaction queues are configured to store a plurality of transaction requests, each having a transaction type. The age counter circuits are configured to generate one or more age counters, where each age counter corresponds to a respective pair of transaction types. Coupled to receive an indication of an input transaction type corresponding to an input transaction request to the controller and coupled to the age counter circuits, the control circuit is configured to select at least one of the plurality of age counters to be stored with the input transaction request in the one or more transaction queues, each of the selected counters indicative of a relative age of the input transaction request with transaction requests of another transaction type.

Abstract: A multiple node network includes a plurality of terminal nodes. A management node manages the terminal nodes. A bus connects the respective terminal nodes and the management node to one another. The respective terminal nodes and the management node communicate with each other using a frame that includes at least an identifier field and a data field. The data field has a discriminative number. Each terminal node transfers the frame to the management node. A contention between the terminal nodes is arbitrated by comparing the respective identifier fields of the terminal nodes. When the arbitration fails, each terminal node repeatedly transfers the frame to the management node after a delay time that is unique for the particular terminal node and that is calculated based upon the discriminative number in the data field.

Abstract: A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

Abstract: An electronic circuit includes processors (CPU1, CPU2) operable to make respective voltage requests (Vcpu1, Vcpu2), and a power management circuit (1470) having a controllable supply voltage output (VDD1) is coupled to said processors (CPU1, CPU2) and further has a voting circuit (4520) responsive to the voltage requests (Vcpu1, Vcpu2) and operable to automatically establish a function (Fct) of the respective voltage requests (Vcpu1, Vcpu2) to control the controllable supply voltage output (VDD1).

Abstract: A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

Abstract: A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared volumes formed in the storage device. The storage system contains a switch for switching and connecting the multiple disk controllers containing cache memories, with a disk array containing the shared volumes capable of being commonly accessed from the multiple disk controllers. The switch performs exclusive access control of the multiple disk controllers' writing on the shared volumes, and performs control to match data other than modified data among the cache memories.

Abstract: In a highly available storage system, an enclosure includes first and second power supplies, and first and second controller boards. Each of the first and second controller boards includes first and second serial bus controllers. First and second serial buses are coupled to both of the first and second serial bus controllers on each of the first and second controller boards. The first serial bus is coupled to the first power supply, while the second serial bus coupled to the second power supply. The first and second serial buses are used for exchanging enclosure management and environmental information between the first and second power supplies and the first and second controller boards. The first and second serial buses are coupled to isolation switches so that redundant modules can operate if a serial bus controller fails.

Abstract: Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from accessing the bus. An initiator transmits I/O requests on the bus to the I/O controller, wherein the I/O requests are queued in an I/O queue, wherein the I/O controller is inhibited by the reconnection inhibitor from draining the queue while the initiator transmits requests to the I/O controller.

Abstract: An integrated circuit comprising a plurality of processing modules M, S and a network N; RN arranged for providing at least one connection between a first and at least one second module M, S is provided. Said connection supports transactions comprising outgoing messages from the first module to the second modules and return messages from the second modules to the first module. Said integrated circuit comprises at least one dropping means DM for dropping data exchanged by said first and second module M, S. Accordingly, an alternative scheme for transaction completion is provided, where full and immediate transaction completion is merely applied for certain cases. The invention is based on the idea to allow the dropping of data in certain cases.

Abstract: The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request completions may trigger corresponding snooping transactions and request completions to the cores. The order in which the transactions are observed on the system interconnect may impose the order in which the transaction triggered to the core are generated. Since this ordering is between multiple interfaces this is referred to as global ordering.

Abstract: A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.

Abstract: A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

Abstract: A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the hosts to the single-ported storage drive so that the bridge need not store read or write data being received from or provided to the storage drive.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: Circuits for improving efficiency and performance of processor-memory transactions are disclosed. One such system includes a processor having a first bus interface unit and a second bus interface unit. The processor can initiate more than one concurrent pending transaction with a memory. Also disclosed are methods for incorporating or utilizing the disclosed circuits.

Abstract: Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.

Abstract: An information processing apparatus includes a plurality of data communication devices via a high-speed serial bus with a plurality of traffics in different directions present between the data communication devices. A transfer-rate measuring unit measures a transfer rate of each of the traffics. A parameter adjusting unit adjusts a parameter for a data transfer in each of the traffics in such as manner that the transfer rate of each of the traffics measured by the transfer-rate measuring unit becomes a preset target value.

Abstract: A bus bridge is connected to a first bus and a second bus. In the bus bridge, an arbiter grants ownership of the first bus to one of a plurality of devices connected to the first bus. A detecting unit detects a read cycle initiated by the device on the first bus to read data from a memory which is also accessible by another device connected to the second bus. A first signaling unit sends a first signal to the arbiter, when the data is not yet transferable to the device when the read cycle is detected. A second signaling unit sends a second signal to the arbiter, when the data becomes transferable to the device. The arbiter deprives the device of the ownership of the first bus upon receipt of the first signal, and withholds from granting the ownership to the device until receipt of the second signal.

Abstract: A PCI bridge device includes an arbiter that uses state information comprised of knowledge of the bus protocol and a history of recent transactions to predict the type of transaction a requestor will issue. The prediction is then used as a basis to mask or allow bus requests from the requester. The arbiter does not grant access to devices that will predictably issue transactions that do not result in the transfer of data. This approach can decrease time wasted by devices attempting unsuccessful transactions and can provide a commensurate increase in bus utilization. The overall effect is an increase in average bus bandwidth and a decrease in average data transfer latencies.

Abstract: A buffer bypass circuit for reducing latency in information transfers to a bus is described. Access to the bus is governed by a bus arbiter employing a bus parking scheme. The buffer bypass circuit comprises a multiplexer and logic configured such that the information to be transferred is either buffered in a buffer if a grant generated by the bus arbiter indicates that the bus is unavailable, or transferred directly to the bus if the grant indicates that the bus is available and the buffer is empty at the time.

Abstract: A storage device for a multibus architecture includes at least one memory to store data, information, and/or addresses, along with a memory connection having a port to connect the memory to one of the buses of the multibus architecture. The memory connection, the port, and the bus have data lines to transmit data along with address lines to transmit addresses, and/or control information to control the memory and other devices connected to each specific bus within the multibus architecture. A switching device selectively connects the memory connection to one of the buses to enable a memory access to transmit data, addresses, and/or control information to or from the selected one of these buses.

Abstract: A variable speed bus has its frequency adjusted based upon bandwidth requirements of active units coupled to a variable speed bus. As units coupled to the bus are stopped, bandwidth requirements are lowered and the bus frequency is reduced in response to the lowered bandwidth requirements. An arbiter selects an appropriate arbitration configuration based on which units are active and which are stopped. The arbitration configuration is adjusted to ensure that the bandwidth requirements of the active units are sustained despite the reduced clock frequency.

Abstract: A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.

Abstract: A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to a weight-information updating unit in real time, and is reflected in an arbitration table. A priority is set to the packet data corresponding to a quantity of the packet data actually transferred on a serial communication path.

Abstract: In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the common bus is not prevented in the CPU contained LSI. A CPU contained LSI includes a CPUa, common address/data buses 111 and 112 connected to the CPUa, CPUb address/data buses 211 and 212 connected to a CPUb, and a bus adjusting circuit 105 disposed between the common address/data buses and the CPUb address/data buses to exclusively control accesses from the CPUa and the CPUb to a device connected to the common address/data buses and connect the CPUb adress/data buses to the common address/data buses only when the CPUb is permitted to access the device connected to the common address/data buses.

Abstract: Method, apparatus and system for controlling input/output adapter data flow operations in a data processing system that includes at least one of a traffic class mechanism in conjunction with virtual channel resources so as to be able to associate Load/Store and DMA flows to/from an input/output adapter, and a relaxed ordering mechanism for associating a relaxed ordering bit to Load/Store operations to an input/output adapter. Functionality for controlling the input/output adapter data flow is provided in a host bridge that connects the input/output adapter to a system bus of the data processing system.

Abstract: It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

Abstract: A system and method for improving the performance of a central processing unit (CPU), in which the system includes a first master such as a CPU, a first local bus connected to a memory device, a bridge, and a main bus connected to a second master and a peripheral device. The bridge is connected among the first master, the memory device, and the main bus and functions as a wrapper and also serves to decode an address output from the first master, monitor a status of ownership of the main bus, and output a wait signal to the first master based on a decoding result and a monitoring result. Accordingly, even while the second master is accessing the peripheral device via the main bus, the first master can access the memory device via the first local bus. The memory device includes a memory core storing predetermined data and a controller having an arbitration function.

Abstract: A computing system with a mode-selectable bus interface. In one embodiment, the computing system includes a system bus, a processor coupled to the bus via an interface unit, and a controller coupled to the bus. The system bus implements one of a first and a second system bus protocols. The interface unit is compatible with the first system bus protocol in a first selectable mode and the second system bus protocol in a second selectable mode, and the controller is compatible with one of the system bus protocols. A mode register is coupled to the interface unit, and the interface unit selects the first mode responsive to a first value of the mode register and selects the second mode responsive to a second value of the mode register. A scan controller is coupled to the mode register for scanning a value into the mode register.

Abstract: Several local IEEE1394 buses are bridged together over a second bus type to create a global bus wherein each local bus node is able to address nodes across the global bus without the local nodes being aware of the bridging operation. A bridging device operates by translating local bus node addresses to a global bus for communication over the second bus type. Alternatively, the local bus node identification process is controlled by the bridging device operating as the root node to cause the local nodes to be identified with a node address that is unique for the global network. The second bus type operates as a backbone for the global network and can be any type of communication bus or network with capability to transport the local bus traffic. The bridging devices that interface the local IEEE1394 buses to the backbone contain portals specific to each bus type that can communicate data between the dissimilar buses.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format.

Abstract: The bus circuit of a master electronics card in a backplane-based communications system adaptively grants the upstream bus to the slave electronics cards by the early termination of a scheduled number of grants to a slave electronics card when the bus circuit on the master electronics card detects idle cells.

Abstract: A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.

Abstract: A data output device is disclosed having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal, first and second logic units for performing logic operations with respect to pre-flag signals and data inversion flag signals, a first output unit for inverting or non-inverting and outputting a plurality of bits contained in the first output data in response to the first data inversion flag signal, a second output unit for inverting or non-inverting and outputting a plurality of bits contained in the second output data in response to the second data inversion flag signal, and an output data initializer for, when a no-operation period is generated in a series of data output operations, initializing the arbitrary output data and supplying the resulting data to the first comparator.

Abstract: A system for addressing bus components comprises a bus controller component that controls access between a CPU and a memory address space. A plurality of bus components connected to said bus controller over a bus are addressable via a memory mapped address within the address space. An address translation table is stored on at least one of the plurality of bus components. The bus translation table stores a translation between a virtual address and a real address.

Abstract: A method for facilitating read completion in a computer system supporting write posting operations. A posted memory write and its associated tag both need to be buffered, where the associated tag is designated to a master of a local bus originating the posted memory write. When a read request moving in an opposite direction of the posted memory write is detected, the read request is checked to identify which master of the local bus is addressed. A destination tag is then assigned to the read request contingent upon the currently addressed master. Further, the destination tag of the read request is compared with the associated tag of the posted memory write. If the destination tag of the read request differs from the associated tag of the posted memory write, the read request can be completed directly regardless of the outstanding posted writes.

Abstract: It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

Abstract: A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus. The peripherals include at least one memory. An arbiter circuit is coupled to the high speed primary bus for managing access requests to the high speed primary bus by any one of the master devices. The microprocessor system further includes a secondary bus, and a bridge interface circuit coupled between the high speed primary bus and the secondary bus. The bridge interface circuit includes a direct memory access controller so that during each data transfer routine between a peripheral connected to the secondary bus and one of the peripherals reduces to a single transfer phase engagement of the high speed primary bus.