Abstract: A method and apparatus for calculating an expected access time associated with one of a plurality of disk drive commands employs one or more neural networks. A plurality of disk drive commands received from an external source are stored in a memory, typically in a queue. Using a neural network, an expected access time associated with each of the queued commands is determined. Determining the expected access time associated with each of the queued commands involves determining a time for performing a seek and settle operation for each of the queued commands and a latency time associated with each of the queued commands. The command indicated by the neural network as having a minimum expected access time relative to access times associated with other ones of the queued commands is identified for execution.

Abstract: A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory controller agents, which are coupled to each other via a series of busses, an incoming memory transaction dispatch unit, and an outgoing memory dispatch unit. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to the plurality of agents. For each incoming transaction, one of the agents will accept the transaction. Each agent is responsible for ensuring coherency and fulfilling memory transactions for a single memory line. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.

Abstract: A circuit arrangement, apparatus and method control the transfer of data into an intermediate buffer associated with a split transaction bus by conditioning such transfer on both the amount of free space in the intermediate buffer and whether a data transfer request associated with such transfer of data is ready to be processed at a shared resource that is the target for the data transfer request. In an example embodiment, data transfer requests represent AGP write transactions to a shared memory, and control logic for an intermediate buffer used to store the write data associated with such transactions is configured to selectively inhibit the storage of write data associated with an AGP write transaction unless both at least one block of free space (representing the minimum amount of space necessary to start the write transaction) exists in the intermediate buffer, and the shared memory is ready to process the transaction.

Abstract: A method and apparatus for prioritizing the use of multifunctional printing system's basic processing resources to permit job streaming. The printing system employs a controller with an improved job contention manager (JCM). A plurality of basic resources of the printing system are provided with a queue. One or more job services, at desired times, signals the JCM to carry out a sub-job of a given job. The signal for each of the sub-jobs includes information about the respective sub-job's, job service and its priority. Responsive to the signal from the job service the JCM adds a corresponding basic resource sub-job to the queues of each basic resource which the sub-job will require to perform the sub-job. A first of the sub-jobs is placed in an “Active” state ready for processing, if the first sub-job is at the top of all of the queues, of all the basic resources, required to perform the first sub-job.

Abstract: A computer system includes a read ahead buffer coupled to a memory controller and an input/output controller coupled to an input/output channel. An I/O device provides an initial read request over the input/output channel which specifies an address in system memory. The memory controller retrieves an amount of data from system memory larger than specified by the read request and provides the requested data to the input/output channel and thus the I/O device. At least a portion of the data retrieved from system memory is stored in the read ahead buffer. The read ahead buffer is marked as valid and identified by at least a portion of the address specified in the read request. When the same I/O device performs a subsequent read access, the I/O request circuit determines whether at least a portion of the address of the subsequent read request matches the portion of the address identifying the read ahead buffer and provides a tag match signal as an indication thereof.

Abstract: A memory processing system and method for accessing memory in a graphics processing system are disclosed in which memory accesses are reordered. A memory controller arbitrates memory access requests from a plurality of memory requesters (referred to as “masters”). Reads are grouped together and writes are grouped together to avoid mode switching. Instructions are reordered to minimize page switches. In one embodiment, reads are given priority and writes are deferred. The memory accesses come from different masters. Each master provides memory access requests into its own associated request queue. The master provides page break decisions and other optimization information in its own queue. The masters also notify the memory controller of their latency requirements. The memory controller uses the queue and page break decisions to reorder the requests from all queues for efficient page and bank access while considering latency requirements. A sort queue may be used to reorder the requests.

Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Abstract: A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references, such that the arbiter services a same queue until the chaining bit is cleared.

Abstract: Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.

Abstract: A local integrated circuit device provides remote configuration access to one or more remote integrated circuit devices. The local integrated circuit device receives configuration access requests through at least two interfaces. The local integrated circuit device accesses a configuration space of one or more remote integrated circuit devices in accordance with the received configuration access requests.

Abstract: Redundant data storage systems and methods of operating a redundant data storage system are presented. In one aspect of the invention, a redundant data storage system includes: a plurality of storage devices configured to redundantly store digital data; a plurality of transaction originating devices configured to originate a plurality of transactions to control operations of the storage devices; a plurality of parallel data buses configured to communicate data relative to the respective transaction originating devices; and a plurality of transaction processing devices coupled with the parallel data buses and configured to process the transactions in an order according to a transaction ordering protocol common to at least some of the transaction processing devices.

Abstract: A method and apparatus for distributing input/output (I/O) operations among at least two paths in a multi-path computer system including a host computer, a system resource and a plurality of paths coupling the host computer to the system resource. For a next I/O operation to be assigned for transmission between the host computer and the system resource, a selection is made of one of the at least two paths for transmission of the next I/O operation based upon a state of previously assigned I/O operations queued for transmission over the at least two paths.

Abstract: A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface has a memory with a high address memory section and a low address memory section. A plurality of directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. A pair of high address busses electrically is connected to the high address memory and a pair of low address busses is electrically connected to the low address memory. Each one of the directors is electrically connected to one of the pair of high address busses and one of the pair of low address busses. A front-end portion of the directors is electrically connected to the host computer and a rear-end portion of the directors is electrically connected to the bank of disk drives.

Abstract: A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the input queue (12). The input queue (12) queues commands and requests a number of output queue credits in response to receiving a command. The input queue (12) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue (14) queues commands and requests a number of output queue credits in response to receiving a command.

Abstract: According to the present invention, a scheduler suitable for reordering of memory requests to achieve higher average utilization of the command and data bus is described. The scheduler for scheduling a plurality of commands to an associated memory, the memory comprising a plurality of M memory banks and a plurality of N memory pages includes restriction circuitry for determining an earliest issue time for each command based at least in part on access delays associated with others of the commands corresponding to a same memory bank and reordering circuitry for determining an order in which the commands should be transmitted to the associated memory with reference to the earliest issue time associated with each command and a data occurrence time associated with selected ones of the commands.

Abstract: A novel method and apparatus for managing communication transactions between electronic appliances is presented. The invention includes a source input/output (I/O) communications function which establishes a first communication link between the apparatus and a source appliance, and a destination I/O communications function which establishes a second communication link between said apparatus and a destination appliance. The apparatus stores and executes a communications program in program memory which manages communications transactions between the source I/O communications function and destination communications function.

Abstract: A server machine receives a printing job, including information to be printed, and a first print parameter, and based on that information, sets a second print parameter that is suitable for the information and also alters the first print parameter. A printer prints the received information based on the printing parameters that are set or changed. Further, users who submit information that is received are identified and the printed results are stored at storage locations that differ for each user. In addition, information may be requested from an external device, and the requested information printed when it is received. Furthermore, information that is input may be transmitted to external devices to request that those devices process that information. Moreover, when an output device that is designated by a received output instruction is a locally owned apparatus, the apparatus performs the processing as instructed.

Abstract: The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

Abstract: A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requester will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requester to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus.

Abstract: A conflict detection method for a disk drive controller is used to handle a conflict potentially occurring if the execution sequence of queued commands sent from a host to a controller is reordered to optimize disk drive transfers. The conflict detection method determines if there is an address range overlap between two queued commands. If an overlap exists, a conflict flag is set. The controller microprocessor utilizes this flag to restrict command reordering and prevent a conflict from producing erroneous data. Conflict detection and command reordering restriction are facilitated by a queued command RAM and a command FIFO. The queued command RAM stores command parameters indexed by command tag values. These parameters include command direction (read or write), LBA, block count, a valid flag and a conflict flag. The conflict detection method compares the address range of a new command with the address range of valid commands in the command RAM to determine range overlaps.

Abstract: A system for handling write requests is described. The system uses two queues for storing posted write requests. When a posted write error results, software handles the posted write error using information stored in a first queue of the two queues. The write request producing the posted write error is cleared from the second queue which continues to handle physical packets containing write requests.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: A processor includes a store queue and a store queue number assignment circuit. The store queue number assignment circuit assigns store queue numbers to stores, and operates upon instruction operations prior to the instruction operations reaching a point in the pipeline of the processor at which out of order instruction processing begins. Thus, store queue entries may be reserved for stores according to the program order of the stores. Additionally, in one embodiment, the store queue number identifying the youngest store represented in the store queue may be assigned to loads. In this manner, loads may determine which stores in the store queue are older or younger than the load based on relative position within the store queue. Checking for store queue hits may be qualified with the entries between the head of the store queue and the entry indicated by the load's store queue number.

Abstract: A host channel adapter is configured for efficiently managing multiple queue pairs by compressing queue pairs having similar properties into queue pair tables configured for storing compressed queue pair entries having shared attributes. Hence, multiple virtual queue pairs can be created out of fewer physical queue pairs stored within a queue pair attribute database.

Abstract: In a router comprising one or more network processing (NP) devices for routing data packets from a source NP device to a destination device via a switch fabric, with each network processing device supporting a number of interface ports, each port capable of interfacing with one or more data queues for receiving packets associated with a class-of-service characterizing the routing of the packets, a system and method for routing packets comprising: classifying a packet to be forwarded from a source NP device according to a particular class-of-service and determining outgoing interface port information of a destination NP device to forward the packet, the interface port having a pre-defined queue base address associated therewith; encoding a queue index offset for the packet associated with a particular class-of-service associated with the packet to be routed; forwarding the packet, queue index offset and outgoing interface port information to the destination NP; and, determining a queue identifier from the base

Abstract: A memory controller may include a request queue for receiving transaction information (e.g. the address of the transaction) and a channel control circuit. A control circuit for the request queue may issue addresses from the request queue to the channel control circuit out of order, and thus the memory operations may be completed out of order. The request queue may shift entries corresponding to transactions younger than a completing transaction to delete the completing transaction's information from the request queue. However, a data buffer for storing the data corresponding to transactions may not be shifted. Each queue entry in the request queue may store a data buffer pointer indicative of the data buffer entry assigned to the corresponding transaction. The data buffer pointer may be used to communicate between the channel control circuit, the request queue, and the control circuit. In one implementation, the request queue may implement associative comparisons of information in each queue entry (e.g.

Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

Abstract: A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing. A storage device stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing. A counter updates a count value thereof every sampling period and generates the updated count value as a basic address.

Abstract: Provided is a system, method, and program for managing read and write requests to a cache to process enqueue and dequeue operations for a queue. Upon receiving a data access request to a data block in a memory, a determination is made as to whether any data block is maintained in a cache line entry in the cache. If so, a cache line entry maintaining the data block is accessed to perform the data access request. A first flag, such as a read flag, associated with the accessed cache line entry is set “on” if the data access request is a read request. Further, if the data access request is a write request to update the data block in the memory, a second flag, such as a write flag, associated with the cache line entry including the data to update may be set “on”. The update data may be data to be enqueued onto a queue, where the queue may be, but is not limited to, a circular buffer in the memory having a head and tail pointer.

Abstract: Method and apparatus are disclosed which increase resource efficiency by collapsing writebacks to a memory. In general the method and apparatus receive an address of a memory request and compare that address to addresses of writebacks stored in a memory controller in order to determine whether the memory request maps to the same memory line of the memory as a stored writeback. If (1) the memory request generates a writeback, and (2) the memory request maps to the same line in the main memory as one of the stored writebacks, then the writeback generated from the memory request may be collapsed with one of the stored writebacks, thus reducing the number of writes to the main memory.

Abstract: A method of communicating between first and second processes running on a plurality of host processors that are connected to a data storage system, the method including the steps of establishing a connection between the first and second processes through the data storage system; and by using the connection established through the data storage system, sending information between the first and second processes.

Abstract: An arbitration protocol is provided for determining between a pair of subsystems within a networking system having a plurality of subsystems which subsystem might obtain access to a common hardware resource. The protocol allows the networking system to determine which subsystem becomes the sender and which becomes the receiver. The protocol is based on a point-to-point communication between two peer subsystems . It is based on an asymmetrical quality such that the first or priority subsystem has a zero latency in accessing the switch while the second subsystem must wait at least one clock cycle before obtaining access to the network system after requesting it and after the end of control by the first subsystem.

Abstract: A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as “deferred” requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure.

Abstract: A method and system for servicing disk I/O requests from domains which have been guaranteed minimum quality of disk service maintains I/O requests for each domain are in separate queues. The queues are serviced by a disk scheduler which selects requests from the queues in accordance with a fair queuing scheduling algorithm that considers the estimated time required to service the request at the head of a queue with regard for the size of the input or output associated with the request, the proportion of disk bandwidth assigned to the particular domain, and the state of the other queues.

Abstract: A method and apparatus are for use with a computer system. Write requests to store data in one or more memory locations that are collectively associated with a cache line are received. The first requests are combined to furnish a memory operation. The computer system may include a peripheral device that furnishes a stream of data to be stored in a memory, and the apparatus may include first and second interfaces, a queue and logic. The first interface is adapted to convert a portion of the stream of data into a first request, and the queue is adapted to store the second request. The logic is adapted to determine if the first and second requests target memory locations that are collectively associated with a cache line and based on the determination, selectively combine the first and second requests. The second interface is adapted to furnish a memory operation in response to the combination of the first and second requests. The requests may be, as examples, read requests and/or write requests.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: A technique for an enhanced transaction order queue is disclosed. A transaction order queue is used to prioritize transactions flowing through a bridge. The present technique enhances the transaction order queue by providing logic within a module, facilitating the enqueuing of a plurality of transaction entries within a single device and ensures that PCI/PCI-X ordering rules are not violated. The technique also provides that the logic device within the PCI-X bridges and buses selects and enqueues a single transaction entry from simultaneous multiple transaction entries.

Abstract: An improved and more efficient mapping scheme between a fiber channel (FC) interface and small computer system interface (SCSI) for multiple initiator support. In accordance with the method of the present invention an alternate mapping path is provided for processing commands from a FC host to a SCSI target while a single command is being processed therebetween through the normal mapping path. The alternate mapping path may be provided by designating another command pin(s) on the SCSI chip in the gateway or bridge box as an additional mapping address(es) or may be provided by using and coupling additional port(s) on each of the targets having multiple ports wherein the additional port(s) is/are associated with an additional mapping address(es).

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: A multi-level cache structure and associated method of operating the cache structure are disclosed. The cache structure uses a queue for holding address information for a plurality of memory access requests as a plurality of entries. The queue includes issuing logic for determining which entries should be issued. The issuing logic further comprises find first logic for determining which entries meet a predetermined criteria and selecting a plurality of those entries as issuing entries. The issuing logic also comprises lost logic that delays the issuing of a selected entry for a predetermined time period based upon a delay criteria. The delay criteria may, for example, comprise a conflict between issuing resources, such as ports. Thus, in response to an issuing entry being oversubscribed, the issuing of such entry may be delayed for a predetermined time period (e.g., one clock cycle) to allow the resource conflict to clear.

Abstract: Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent.

Abstract: A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory and transmitted in a weakly ordered fashion over a bus to a graphics device. The graphics device reorders the incoming data into the same order as which the data was written into the contiguous region of system memory, thereby allowing the use of order dependent encoded commands with the weakly ordered bus interface.

Abstract: A computer system includes an address and data path interconnecting an on-chip CPU with a module and an external communication port, event request packets being generated by the CPU and the module and memory access packets being generated by the CPU, each packet having a destination address and being distributed in parallel format on-chip with a reduction to a more serial format for off-chip communication.

Abstract: A Redundant Array of Independent Disks (RAID) data storage system includes an AutoRAID memory transaction manager for a disk array controller that enables a consistent, coherent memory image of the data storage space to all processors across hot-plug interfaces. To external processes seeking to read or write data, the memory image looks the same across the hot-plug interface. The disk array controller has two identical controllers, each with its own non-volatile memory, to maintain redundant images of disk array storage space. A hot-plug interface interconnects the two controllers. Each controller has an AutoRAID memory transaction manager that enables sharing of cyclic redundancy check (CRC)-protected memory transactions over the hot-plug interface between the two controllers. The AutoRAID memory transaction managers also facilitate ordered execution of the memory transactions regardless of which controller originated the transactions.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.

Abstract: A queuing architecture and method for scheduling disk drive access requests in a video server. The queuing architecture employs at least two access request queues for each disk drive within a disk drive array, and a queue selector for selecting the first and second queues. The first queue is for disk access requests by steady-state users requesting new data streams who are currently viewing a program from the video server. The second queue is for all other types of disk access requests, including requests by new users, requests for loading content, disk maintenance, meta-data synchronizing, and the like. Steady-state disk access requests are serviced in order of ascending time deadlines. The queue selector gives highest priority to requests in the first queue, and requests from the second queue are serviced only upon a guarantee that all of the steady-state requests in the first queue will meet their time deadlines in the worst case access times for the disk drives.

Abstract: A method and system in data processing system are disclosed for efficiently servicing requests to access a disk. Each of the requests are associated with a location on the disk. The requests include real-time requests and non-real time requests. A most urgent one of the requests is determined. The most urgent one of the requests is associated with a first deadline and a first location on the disk. A second most urgent one of the requests is also determined. The second most urgent one of the requests is associated with a second deadline and a second location on the disk. The first deadline is earlier in time than the second deadline. A service time is determined. The service time is earlier in time than the first deadline. The service time is determined so that sufficient time will exist to service the most urgent one of the requests before the first deadline and service the second most urgent one of the requests before the second deadline.

Abstract: A method and apparatus for enabling a common data set to be utilized by multiple data processes. During a first operating mode, first and second data stores in a data storage facility with a common buffer attach to a first data process and act as mirrors. Data to be written transfers to the common buffer and then to the data stores. A second command produces a split whereby the first data store remains attached to the first data process and the second data store is available to the second data process. After the second command is executed, any data in the common buffer is transferred to the corresponding data stores in parallel with and transparently to the actions between the first and second data processes and the first and second data stores, respectively.

Abstract: Hot replacement of a storage device in a serial array of storage devices. The apparatus and the process of the invention allow one device to be removed from the array, without causing critical error to be delivered to the host computer and, in turn, all of the delays and problems associated with the delivery of such an error signal. The invention includes a buffer to buffer data requests from the host computer while the replacement process is ongoing. After the drive is replaced, the requests stored in the buffer are performed.