Abstract: A centralized queue for a network printing system allows clients to make job requests and be placed in a job queue without transmitting the actual print job data to the network. An imaging device protocol (IDP) operates independently of the network layers below and only requires that a transport protocol/port be bidirectional. A variety of heterogenous network protocols may be supported by IDP for placing all of the incoming print job information in a print queue regardless of the protocol. Print job information from both IDP and non-IDP protocol/ports may be placed in the print queue by emulating IDP on the non-IDP protocol/ports. As a result, job information for all of the print jobs attempting to access a busy printer may be stored in the print queue so that the print jobs can be printed by the printer with a fair arbitration once the network printer becomes available.

Abstract: Provided are a method, system, and program for managing requests to an Input/Output (I/O) device. The I/O requests directed to the I/O device are queued and a determination is made as to whether a number of queued I/O requests exceeds a threshold. If the number of queued I/O requests exceeds the threshold, then a coalesce limit is calculated. A number of queued I/O requests not exceeding the calculated coalesce limit are coalesced into a coalesced /O request and the coalesced I/O request is transmitted.

Abstract: A network interface device couples a host computer to a network. The network interface device includes a processor and a DMA controller. The processor causes the DMA controller to perform multiple DMA commands before the processor takes a particular software branch. The processor issues the DMA commands by placing the DMA commands in a memory and then pushing values indicative of the DMA commands onto a DMA command queue. The values are popped off the DMA command queue and are executed by the DMA controller one at a time. The DMA commands are executed in the same order that they were issued by the processor. The processor need not monitor multiple DMA commands to make sure they have all been completed before the software branch is taken, but rather the processor pops a DMA command complete queue to make sure that the last of the DMA commands has been completed.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

Abstract: An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.

Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

Abstract: A method and mechanism for allocating transaction tags. A request queue includes a counter whose value is used to identify a corresponding tag of a plurality of unique tags. The queue is configured to increment the counter and use the current count value to index into a buffer pool. If the tag corresponding to the currently indexed buffer pool entry is available for allocation, a determination is made as to whether the currently identified tag is corresponds to the last tag which has been de-allocated. If the identified available buffer pool entry/tag matches the last tag which was de-allocated, the queue continues the process of counter incrementation and searching of the buffer pool for an available entry to select for allocation. When a request is received, the currently selected tag is allocated. Additional circuitry may be used to identify a fallback tag in the event a request is received while the queue is searching for a tag. In such an event, the fallback tag may be allocated.

Abstract: A data processing system has a single configurable write buffer within a peripheral interface unit that is shared among multiple peripherals. Configuration registers are dynamically programmed to control criteria for determining whether control of a system bus will be released prior to completion of a write access to a peripheral. The criteria include which peripheral is being accessed, the particular bus master that is requesting the write request, and a mode of operation, such as supervisor or user write access modes. Write buffering may also be dynamically disabled for individual peripherals based on the state of a peripheral by using a hardware side band signal driven by the peripheral to override a static buffer write policy programmed in control registers.

Abstract: Generalized queues and specialized registers associated with the generalized queues are disclosed for coordinating the passing of information between two tightly coupled processors. The capacity of the queues can be adjusted to match the current environment, with no limit on the size of the entry as agreed upon between the sending and receiving processors, and with no practical limit on the number of entries or restrictions on where the entries appear. In addition, the specialized registers allow for immediate notifications of queue and other conditions, selectivity in receiving and generating conditions, and the ability to combine data transfer and particular condition notifications in the same attention register.

Abstract: Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future. Each channel is thereby guaranteed a response time.

Abstract: A clustered computer system includes a shared data storage system, preferably a virtual shared disk (VSD) memory system, to which the computers in the cluster write data and from which the computers read data, using data access requests. The data access requests can be associated with deadlines, and individual storage devices in the shared storage system satisfy competing requests based on the deadlines of the requests. The deadlines can be updated and requests can be killed, to facilitate real time data access for, e.g., multimedia applications such as video on demand.

Abstract: Embodiments of the present invention are devices with a queue for receiving a plurality of data write requests and having a means for comparing the data write requests in the queue and then requesting only data identified by the data write requests that would not be overwritten by any later received data write requests in the queue. By requesting only the data that is not overwritten by subsequent data write requests, the data actually transferred over the bus is minimized given the current queue of data write requests. One aspect of the present invention includes a method of requesting data from a host over a data bus.

Abstract: An embedded host channel adapter includes a transport layer module, a transport layer buffer, and a link layer module. The transport layer buffer is configured for storing transmit packet entries for virtual lanes serviced by the embedded host channel adapter. The link layer module is configured for supplying virtual lane priority information and virtual lane flow control information, for each virtual lane, to the transport layer module. The link layer module also configured for constructing transmit packets to be transmitted based on retrieval thereof from the transport layer buffer. The transport layer module is configured for selecting one of the virtual lanes for servicing based on the supplied virtual lane priority information and virtual lane flow control information for each of the virtual lanes, enabling the transport layer module to prioritize received work notifications, for generation of respective transmit packet entries.

Abstract: An interface between a host and a slave device having a latency greater than the latency of the host is disclosed. The interface includes a register and a state machine. The state machine provides data to the host from any address in the slave in two host read cycles. The state machine receives a first request from the host for data stored at a first address in the slave at a first time. The state machine stores the data returned from the slave in response to the first request in the register at a second time. The state machine receives a second request from the host for data stored at a second address in the slave at a third time. The state machine provides the data specified in the first request to the host at a fourth time. The state machine is additionally adapted to provide data to the host from a second address in the slave in one read cycle.

Abstract: Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests are presented to memory may be changed to avoid or minimize page replace conflicts, DIMM turn around conflicts, and other types of conflicts that could otherwise impair the efficiency of memory operations.

Abstract: A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in the request FIFO. Each issued requests is tagged to either enable or disable a re-order feature. When a request that is tagged as re-order enabled is granted, the FIFO logic monitors the response provided for the request. If the response is a retry, the request is removed from the first position of the request FIFO and the next sequential request is moved into the first position. The removed requests may be re-ordered within the request FIFO or sent back to the initiator. In the former implementation, controller logic reorders the first request within the request FIFO.

Abstract: A disk input/output (I/O) system includes a controller, a cache, a disk I/O subsystem, and a command queue. The load on the queue is monitored and when it reaches a threshold, commands are designated cache only. Cache only commands are added to the queue only if they can be completed without accessing the disk I/O subsystem. If the disk I/O subsystem would be accessed in order to complete a cache only command, the command is returned to the operating system with an error. The operating system can then add the command to an operating system or back-up queue.

Abstract: A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous log-in (steps S210 and S212). In the case of an affirmative answer, the management agent ME1 reads an ordinal number of precedence ‘n’ allocated to a GUID of the initiator of interest from a queue (step S213) and reads a time constant mapped to the input ordinal number of precedence ‘n’ from a time constant table (step S214). The management agent ME1 subsequently sends a status packet, which includes a log-in error status and the time constant, to the initiator of interest (step S216). The initiator of interest receives the status packet, reads the time constant included in the input status packet, and outputs another request of log-in to the target T1 at a timing specified by the time constant.

Abstract: Provided is a method, system, and program for managing Input/Output (I/O) requests generated by an application program. The I/O requests are transmitted to an output device. A determination is made of a priority associated with the I/O request, wherein the priority is capable of being at least one of a first priority and a second priority. The I/O request is transmitted if the determined priority is the first priority. Transmittal of the I/O request is deferred if the determined priority is the second priority.

Abstract: In one embodiment, a system is disclosed having a first device, a second device, and two sets of bi-directional buses that couple the first and second devices. The devices are to perform transactions with each other over the buses, such that each set of buses has a dominant, but not exclusive, direction, for sending transaction information and data, that is opposite the other. Other embodiments are also described and claimed.

Abstract: Coded requests are received from Memory Port Interfaces (608 and 612) and stored into Outgoing Queue (604). Coded requests are also received from Transaction Pipeline (610), some of which may be linked requests. In response to each linked request stored in Outgoing Queue (604), multiple bus requests are generated by Outgoing Queue (604) and assembled by Assembler (602) and placed onto Bus Interface (620).

Abstract: A method for associating reliable datagram queue pairs with an underlying end-to-end context of a channel adapter is provided. The method comprises storing a reliable datagram domain (RDD) within the context of a reliable datagram queue pair (RD QP). The same RDD is stored within an end-to-end context (EEC). A partitioning key (P—key) is also stored within the EEC. The RDD cannot be accessed by consumer processes. In the case of incoming messages, the P—keys of the incoming data packet and EEC are compared. If P—keys match, then the RDD's of the RD QP and EEC are compared. If the RDD's match, the packet is processed normally. In the case of outgoing messages, the RDD's of the RD QP and EEC are first compared, and if they match, the P—Key of the EEC is inserted into the transport header of the data packet.

Abstract: A disk drive is disclosed comprising a disk, a head, and a voice coil motor (VCM) for actuating the head over the disk. The disk drive executes a rotational position optimization (RPO) algorithm to select a next command to execute relative to an estimated seek time computed for each command in a command queue. A motor capability of the VCM is estimated and used to modify the estimated seek time for each command in the command queue to thereby optimize the RPO algorithm.

Abstract: In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.

Abstract: A microprocessor prioritizes cache line fill requests according to request type rather than issuing the requests in program order. In one embodiment, the request types include blocking accesses at highest priority, non-blocking page table walk accesses at medium priority, and non-blocking store allocation and prefetch accesses at lowest priority. The microprocessor takes advantage of the fact that the core logic clock frequency is a multiple of the processor bus clock frequency, typically by an order of magnitude. The microprocessor accumulates the various requests generated by the core logic each core clock cycle during a bus clock cycle. The microprocessor waits until the last core clock cycle before the next bus clock cycle to prioritize the accumulated requests and issues the highest priority request on the processor bus.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.

Abstract: An apparatus for providing direct data processing access in a network computing system environment. The system environment has a main storage which can be connected to one or more application servers and is in processing communication with an interface element. The interface element has at least one adapter and can be connected to one or more application user(s). One or more queues are established in the main storage that can handle data without causing interrupts in the running programs. Incoming data is received using the adapter and as data is received or modified, the status of the network computing system will be updated to reflect the new data or change. Data is then processed in the main storage after interrogating the multiple existing queues in the main storage simultaneously and forwarding them in turn to their appropriate destination or application server after a determination has been made by interrogating these queues.

Abstract: Methods, systems, and articles of manufacture for communicating with an I/O processor (IOP) are provided. Polling of message queue pointers is utilized to detect the occurrence of certain message queue related events, rather than rely on interrupts generated by the IOP. The polling may decrease the disruptive effects of IOP generated interrupts. In an effort to minimize the latency associated with detecting IOP related events, the polling may be initiated frequently by an operating system task dispatcher. In an effort to minimize context switches, the task dispatcher may schedule the processing of upstream messages detected while polling to coincide with naturally occurring task swaps.

Abstract: The present invention is directed to an interface. An interface system suitable for coupling a first bus interface controller with a second bus interface controller includes a first bus interface controller and a second bus interface controller in which the second bus interface controller is coupled to the first bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data.

Abstract: Provided are a method, system, and program for processing operations in a system including a bus, a target device and devices capable of accessing the target device over the bus. The target device receives a transaction request from one of the devices over the bus and determines whether a delayed read request is pending after receiving the transaction request. The target device issues a command to disconnect the device initiating the transaction request from the bus. The device initiating the transaction request is allowed to reconnect to the bus and complete the transaction request after the delayed read request is completed.

Abstract: A disk drive is disclosed which pre-computes first seek parameters to seek to a continuation track storing read-ahead data, and second seek parameters to seek to a target track of a next command. An abort window is also computed for aborting a read-ahead operation early in order to seek to the target track of the next command. If the head enters the abort window, the disk drive is programmed with the second seek parameters to seek to the target track of the next command. If the read-ahead operation requires a seek to the continuation track prior to the head entering the abort window, the disk drive is programmed with the first seek parameters to seek to the continuation track.

Abstract: A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption), or mark its queue node to allow reclamation by a successor thread.

Abstract: A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.

Abstract: An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next location to be written in a queue. The system also allows an incoming descriptor to point to a plurality of data frames for transfer to the host processor, wherein the peripheral need not read a new descriptor each time a frame is to be transferred to the host.

Abstract: A method and apparatus for efficiently executing a read request issued from a host computer when write requests are cached in a cache memory.

Abstract: A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

Abstract: An apparatus for monitoring the state of computer system resources. According to the invention, the apparatus includes bus interface logic and a queue. The bus interface logic is used to interface with a serial bus and parse a bitstream through the serial bus into a command and an address. Also, the apparatus includes bridge logic, an arbitrator and a decoder. The decoder is used to decode the command. If the command represents a predetermined request for access to a resource bus, the decoder passes the predetermined request associated with the address to the queue. Whenever the predetermined request occurs, the arbitrator grants the resource bus to the predetermined request and allows the queue to output the predetermined request as well as the associated address. The bridge logic is provided to transfer data to and from computer system resources according to the predetermined request and the address.

Abstract: An apparatus for gathering queue performance data includes an event conditioning logic unit that receives a queue enter signal, a queue exit signal, and a queue not empty signal from a queue. The apparatus also includes a counter that may be both incremented and decremented. The event conditioning logic unit may be programmed to increment the counter upon occurrences of a predetermined combination of the queue signals. The event conditioning logic unit may also be programmed to decrement the counter upon occurrences of an additional predetermined combination of the queue signals.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: Provided are a method, system, and program for increasing processor utilization. A list of work is divided for processing among a plurality of processes, wherein a process is allocated a part of the list of work to process, and the processes execute in parallel. If a process completes the list of work allocated to the process then the process is made available on an available process queue. Before a process performs any work, the process reads the available process queue and determines if any process is available to share the work. If so, the work is split up between the examining process and the available process. In one implementation, the work involves scanning a cache and if necessary destage data.

Abstract: A DMA controller including a request queue for holding DMA transfer requests clears only the request queue without executing unnecessary DMA transfers and provides information about the states of the queue. A DMA controller is configured to enable data transfer control with respect to plural channels and includes a request queue capable of holding the identification information of channels concerned in plural data transfer requests, wherein the states of the request queue can be outputted and information held in the request queue can be cleared.

Abstract: The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.

Abstract: Methods and a system for combining commands for data transfers between a drive and memory. One exemplary method includes receiving multiple read or write commands in a queue. Then, a first command of the multiple read or write commands is processed. Next, the multiple read or write commands are combined. The combination includes identifying like commands each being associated with a file stored on a drive and ascertaining which of the files associated with the like commands are contiguous. Then, a combined command is created, where the combined command consolidates the identified like commands being associated with contiguous files. Next, the combined command is issued to the drive.

Abstract: The present invention is in the field of memory. More particularly, embodiments of the present invention can enhance an interface of a memory device by processing more than one request at a time.

Abstract: The present invention provides an apparatus and system for buffering data in a communication network with an arranged priority which enables traffic shaping. A cell buffer unit (600) is arranged with a plurality of queues (614) configured to store PDUs on-chip and off-chip. There are associated queues both on-chip and off-chip for each priority queue. A cell buffer controller (620) forwards PDUs to a predetermined priority queue and manages the transfer of PDUs off-chip when a priority queue on-chip is fully occupied. The controller (620) also manages the transfer of PDUs from the off-chip queue when the on-chip priority queue becomes less than fully occupied.

Abstract: A host channel adapter configured for outputting packets according to InfiniBand™ protocol is implemented using partitioned link modules configured for performing selected link operations prior to outputting the packets. A pre-link module is configured for ordering work queue entries in an order based on determined service level and virtual lane priorities. The pre-link module outputs the ordered work queue entries to a transport service module configured for generating a transport layer header for the packets based on the respective work queue entries. Once the transport layer headers have been generated, a post-link module is configured for retrieval of the transport layer header and transport data and preparing the transmit data packets for transmission on the network by constructing the link layer fields. The post-link module outputs the transmit data packets based on the ordering and the flow control protocol for the appropriate virtual lanes.

Abstract: A data transfer technique between a source port and a destination port of a transfer controller with plural ports. In response to a data transfer request (401), the transfer controller queries the destination port to determine if it can receive data of a predetermined size (402). If the destination port is not capable of receiving data, the transfer controller waits until said destination port is capable of receiving data (412). If the destination port is capable of receiving data, the destination port allocates a write reservation station to the data (403). Then the transfer controller reads data of the predetermined size from the source port (404) and transfers this read data to the destination port (405). The destination port forwards this data to an attached application unit, which may be memory or a peripheral, and then disallocates the write reservation station freeing space for further data transfer (406).

Abstract: A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.