Abstract: A peripheral interface circuit for handling graphics responses in an I/O node of a computer system. A peripheral interface circuit includes a buffer circuit coupled to receive packet commands. The buffer circuit includes a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The peripheral interface circuit may determine whether a given one of the received packet commands is a graphics response belonging to a particular respective virtual channel. In response to determining that the given packet command is a graphics response belonging to the particular respective virtual channel, the buffer circuit may cause the given packet command to bypass the plurality of buffers.

Abstract: An electronic queue management system for implementation on a chip. The queue management system comprises a plurality of primitive queue elements each including a register for a next-pointer and a register for a queue number. The next-pointer values may be selected via a register input and can be fed out via a registered output. Such queue elements are associated with a respective entry in a central array which stores the data belonging to the actual request. The separation of the data array and queue elements facilitates queue management as the data amounts are quite large compared to the small amount of data being required for the pre logic of the queue management system. Multiple add requests and multiple remove requests operations for different queue elements may be concurrently achieved in a single cycle.

Abstract: When a user process issues an input/output request in a process performed in response to the input/output request generated by the user process, the input/output request is queued in the input/output request list which is a queue in a list format on the user space side. On the kernel side, when a input/output request in the input/output request list is processed, the status is changed into ‘processed’, and a list element whose status indicates ‘processed’ is removed from the request list on the user space side. On the kernel side, a thread for performing a process in response to an input/output request is divided into a plurality of threads, and the CPU is released to another thread before completion of the process.

Abstract: A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

Abstract: Disclosed is a method, system, program, and data structure for queuing requests. Each request is associated with one of a plurality of priority levels. A queue is generated including a plurality of entries. Each entry corresponds to a priority level and a plurality of requests can be queued at one entry. When a new request having an associated priority is received to enqueue on the queue, a determination is made of an entry pointed to by a pointer. The priority associated with the new request is adjusted by a value such that the adjusted priority is associated with an entry different from the entry pointed to by the pointer. The new request is queued at one entry associated with the adjusted priority.

Abstract: An SMP computing system has a RAID controller and an interconnect bus system for communication processors and the RAID controller. There are in host memory a plurality of reply queues, at least one of which is associated with each processor of the SMP computing system. Replies associated with commands originating from a first processor are buffered by the RAID controller in a first reply queue, and replies associated with commands originating from a second processor are buffered in a second reply queue.

Abstract: A processing system includes a local or local storage and a number of remote or remote storage systems that store data mirroring that maintained by the local storage system. Data that is written, changed, deleted or other wise modified by the local storage system is periodically sent to the remote storage systems via remote copy commands to update the mirroring data maintained by each. Failure of a local or a remote storage system will cause the surviving storage systems to exchange information indicative of the data maintained by each, and if differences exist, to exchange data so that the mirrored and/or mirroring data is the same.

Abstract: In a data processing system, the effective speed of transferring data packets between a data processing unit and various other devices with different performance characteristics is improved by a data transfer method and a packing and buffering device, thus offloading the data processing unit or the various devices. FIFO buffers provide intermediate storage of transfer data, and packing and unpacking modules ensure efficient use of bus widths that are different on the data processing side and the device side. Data packet transfer control is effected using a control and status module with a common byte counter, and a direct transfer is facilitated via a supplementary direct data path between the data processing unit and other devices.

Abstract: A host channel adapter is configured for servicing a work notification, supplied by a host process to an assigned destination address accessable by the host channel adapter, based on matching the assigned destination address with a stored notification address from one of a plurality of queue pair context entries stored within the host channel adapter. The host channel adapter receives a queue pair context entry including a notification address, based on creation of a corresponding queue pair for a host process. The queue pair enables the host process to post a work descriptor and output a work notification to the host channel adapter by writing the work notification to an assigned destination address. The host channel adapter matches the assigned destination address with a stored notification address, and services the work descriptor based on the corresponding queue pair attributes specified in the identified queue pair context entry.

Abstract: A method and system for allocating logical paths between a host and a controller in a virtual data storage system such that the loads on the logical paths from storage devices are distributed evenly across the logical paths. When a connection request for connecting a storage device to the host is received by the controller, the controller counts an amount of queued connection requests from the storage devices to the host on each logical path. A logical path for the new connection request is then selected as a function of the amount of queued connection requests on each logical path and the current input/output activity on each logical path. The controller selects the logical path void of current input/output activity that has the lowest amount of queued connection requests to be the selected logical path. The controller then associates the new connection request with the selected logical path.

Abstract: DMA transfer request signals corresponding to respective channels are received and held in respective transfer request holding circuits. DMA transfers are assigned to the DMA transfer request signals respectively in a channel transfer request arbitrating circuit according to priorities set in advance for the DMA transfer request signals, and the DMA transfers for the DMA transfer request signals are performed in the order of lower priority. Also, a transfer waiting time period from the reception of one DMA transfer request signal to the assignment of the DMA transfer is measured in a transfer waiting time counter for each DMA transfer request signal, and the transfer waiting times are, for example, stored in a storing circuit and are selectively read out.

Abstract: A system and method for scheduling packet output according to a quality of service (QoS) action specification. A system is provided with a calendar queue with a plurality of bandwidth timeslots, wherein the bandwidth timeslots are organized into groups. A look-up logic circuitry inspects a group of bandwidth timeslots substantially simultaneously and determines from the group a first unoccupied bandwidth timeslot in which a current packet can be scheduled. The look-up logic circuitry also determines a first occupied bandwidth timeslot that contains a next packet to be transmitted.

Abstract: A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues. The memory controller may be used in parallel processing systems and may also include an order queue, a lock lookup content addressable memory (CAM) and a read lock fail queue. A system including a media access controller (MAC), a network processor and an SRAM controller, and a method for controlling a RAM, are also described.

Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors. Further presented is a method including determining whether a queue head has less than or equal to a predetermined packet size and whether a period is one of greater than and equal to a predetermined schedule window. The method includes storing contents of a current entry in a frame list in a next pointer in the queue head. Also replacing the current entry in the frame list with a pointer to a new queue head. Many queue heads are directly coupled to the frame list.

Abstract: A frame receive queue may perform disassembly and validation operations on frames received by a node in a Fiber Channel network. The frame receive queue may store information used for later processing of the frames, e.g., header data and the first eight payload words, in an on-chip memory for fast processor access. The payload data for the frames may be stored in a larger, external memory.

Abstract: A data storage device and method for improving the performance of data storage devices examines a command queue and performs data transfers to memory within the device before prior commands have completed. A process running in the idle loop of the controller in the storage device checks the queue for write requests and if a cache space within a dual-port cache to hold the transfer data is available, the data transfer portion of the transfer is completed, while the device is still waiting for completion of prior commands in the queue, and data transfers are completing from the cache to the physical media for the prior command.

Abstract: A method of managing ring-buffer memory space in a digital signal processor when processing a filter, includes releasing ring-buffer memory space previously reserved for ring-buffer data upon completing a filter process and determining that the ring-buffer data stored in said ring-buffer memory space is no longer necessary after the filter-process is carried out.

Abstract: An arbitration mechanism for an input/output node of a computer system. An arbitration mechanism includes a buffer circuit for storing received control commands corresponding to a posted virtual channel and a second virtual channel. Each of the control commands includes an identifier value indicative of the source of the control command. A tag circuit that may generate a tag value for each of the control commands prior to the control commands being stored. The tag value may be indicative of an order of receipt of each of the control commands relative to other control commands and may be dependent upon the identifier value. In addition, an arbitration circuit may arbitrate between control commands stored within the buffer circuit dependent upon the tag value of each of the control commands. The arbitration circuit may select, independently of the tag values, a given control command and having a flag bit set.

Abstract: An apparatus is contemplated, including a router and a memory controller. The router is configured to route a write request and write data to the memory controller. The memory controller is coupled to receive the write request and the write data. If the write data is a number of bytes less than a minimum number of bytes writeable to a memory to which the memory controller is capable of being coupled, the memory controller is configured to read first data from the memory. The first data comprises the minimum number of bytes and includes bytes to be updated with the write data. The memory controller is configured to return the first data to the router as a read response. The router is configured to return the first data to the memory controller.

Abstract: A disk drive is disclosed wherein if a write command is aborted, the write command is re-executed according to a rotational position optimization (RPO) algorithm rather than immediately re-executing the write command to better optimize drive performance relative to mechanical latencies. An aborted write command is replaced into an input/output queue together with other pending commands. The aborted write command is eventually re-selected for execution by the RPO algorithm when executing the write command minimizes mechanical latencies relative to the other pending commands.

Abstract: An apparatus and method for accessing a data item from a storage system having a plurality of data storage devices are disclosed. I/O operation requests are submitted to multiple data storage devices for each data item to be accessed. The I/O operation requests are issued to copies of the data items that reside on a plurality of data storage devices. More I/O operation requests are submitted than the number of data items that are to be accessed, written, or updated.

Abstract: A computer system includes a processor, a cache, a system bus, a memory-control subsystem, an external memory bus, RAM memory, and flash memory. All but the last three are fabricated on a single ASIC. The memory control subsystem includes a RAM controller, a flash-memory controller, and a memory interface between the controllers and the memories. In addition, the memory-control subsystem includes a system-bus FIFO write buffer. During an external-memory access, the request information is transferred from the system bus to the system-bus buffer instead of directly to the memory interface. The system-bus buffer stores address data, content data (in the case of a write request), and control data. In turn, the control data is forwarded to the appropriate controller and the address data and the content data are forwarded to external memory bus. Note that only one system-bus write buffer is required despite the plural memory controllers.

Abstract: An attribute of object information to be processed and a corresponding process are designated, and a command to be executed is set. When the process designated for the object information having the designated attribute is performed, the command that is set is executed. Further, a status that is employed as a process execution condition is designated, and a corresponding process that is to be performed while the status corresponds to that of the designated status is stored with that status. Then, when it is determined that the current status is the designated status, the corresponding process is performed, and thus, each time a specific event occurs, a corresponding process can be performed without an instruction having to be issued. Specifically, a trigger for the issuance of a notification is set, and a time period extending from the time the trigger is tripped until the notification is issued is designated.

Abstract: A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

Abstract: An automated direct memory access system is implemented as an advanced ATA host IC for mother board or adapter applications. The system transfers data from two independent ATA channels using the ATA Ultra-100 protocols. The ADMA implements a command chaining technique to de-couple the host command sequence from channel execution. Software builds a command chain for hardware execution. The ADMA hardware independently reads command chain requests from memory and executes the next task on the list. When the ADMA hardware completes a task, it interrupts the host in order to inform the host that the task is complete, but immediately proceeds to the next task without waiting for interrupt servicing by the host.

Abstract: A data processing system may include an interconnect and first and second components coupled to the interconnect for data transfer therebetween. The first component contains a write pipeline that includes an address register and a queue including storage locations for a plurality of data granules. In response to receipt of a plurality of data granules that are each associated with a single address specified by the address register, the queue loads the plurality of data granules into sequential storage locations in order of receipt. Upon the queue being filled with a predetermined number of data granules, the queue outputs, to the second component via the interconnect, the predetermined number of data granules at least two at a time according to the order of receipt. Thus, data transfer efficiency is enhanced while maintaining the relative ordering of the data granules.

Abstract: A queuing architecture and method for scheduling disk drive access requests in a video server. The queuing architecture employs a controlled admission policy that determines how a new user is assigned to a specific disk drive in a disk drive array. The queuing architecture includes, for each disk drive, a first queue for requests from users currently receiving information from the server, and a second queue for all other disk access requests, as well as a queue selector selecting a particular first queue or second queue for enqueuing a request based on the controlled admission policy. The controlled admission policy defines a critical time period such that if a new user request can be fulfilled without causing a steady-state access request for a particular disk drive to miss a time deadline, the new user request is enqueued in the second queue of the particular disk drive; otherwise, the controlled admission policy enqueues the new user request in a second queue of another disk drive.

Abstract: In collective I/O processing in which a plurality of processes access the same file in a shared manner, when each user process issues an I/O request, the user process notifies the system of information on a file region accessed by all the processes; information for specifying whether or not a prefetch is performed, and information for specifying whether or not a disk preallocate is performed, together with the I/O requests issued by all associated processes, as hint information. The system provides a buffer for storing data in a file region accessed by all the processes based on the hint information, such that the I/O processing for all the processes is performed using this buffer.

Abstract: A multi-port adapter and method for scheduling jobs at the adapter input/output ports. A plurality of queues are provided, each associated with one of the input/output ports. A processor arranges the jobs in each of the queues in a normal queued order for selection by the associated port. Upon selecting a next job for one of the ports, the processor determines the number of queued jobs of each of the queues for each of the other ports; and determines whether the number of queued jobs of each queue for the other ports is less than a threshold. If the number of jobs is less than the threshold, the processor selects the next job for the one port from the jobs in the queue for the one port identified as one that may be conducted in out of queue order, e.g., having attached heuristic information; else, selects the next job for the one port from the jobs in the queue for the one port on the normal queued basis.

Abstract: A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source port (460-461), a channel controller (410-412) and a destination port (460, 461). Channel to port buses (CP0-CP2) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC0-PC1) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry (420, 421) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller (460, 461) on each clock cycle for providing an address for a transaction performed on each clock cycle.

Abstract: A method and apparatus are provided for efficiently sorting queued commands with unknown rotational latency in a direct access storage device (DASD). For each command an initial expected access time (EAT) including a probability of success calculation is calculated and stored in a miss table. An actual starting location for the next command to be executed is identified. Utilizing the miss table, and a calculated best candidate command list for a plurality of different starting locations, a command in a command queue is selected based upon the actual starting location. The best candidate command list for a plurality of different starting locations is calculated by first sorting the miss table row by increasing EAT values and sequentially incrementing a miss time value by the predefined unit of time and updating all variable in the first row and adjusting a potential value in the second row of the miss table.

Abstract: Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel's BEN.

Abstract: A medical image filing system having a first recording device for recording a plurality of image data from a medical image pickup device; a second recording device for recording the plurality of image data from the medical image pickup device, the second recording device has a recording speed slower and a recording capacity greater than that of the first recording device; and at least one image reproducing device for reading and reproducing designated image data from the plurality of image data recorded in the first and second recording devices. The at least one image reproducing device has a third recording device for recording the designated image data, wherein the designated image data recorded in the third recording device can also be reproduced by the at least one reproducing device.

Abstract: Provided are a method, system, and program for managing access to a device. An I/O request directed toward the device is received and a determination is made of a device object for the device associated with at least one path object. A determination is made of a queue object associated with the device object, wherein the queue object corresponds to one queue. A determination is made of a queue status from the determined queue object and the I/O request is transmitted on a path indicated in the path object that is associated with the determined device object if the queue status is set to a state indicating to transmit I/O requests.

Abstract: This invention (The Customer Contact Channel Changer) enables the integration of different Customer Contact Channels such as live call center ACD (Automatic Call Distribution) agents, ADSI (Analog Display Services Interface) enhanced IVR (Interactive Voice Response) systems and WWW (World Wide Web) servers. The world wide web servers are used to allow customers with computer equipment to access information from an organizations databases in a self service mode. Frequently these customers have questions best answered by human ACD agents. With this invention the connection between the customer with the question and the agent with the answer is done quickly and efficiently with both parties sharing screens of common information. Also control is retained by the customer to make the call happen when they want it.

Abstract: A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requestor will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requestor to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus.

Abstract: Data transfers from the peripheral interface of a disk array to a data buffer are snooped to determine if the starting address of a data transfer matches an entry in a list of starting addresses for requested data. If a match is identified, third party transfer is initiated and the data is simultaneously transferred to the host interface of the host system. The resulting data bandwidth is increased. A throttling/suspension mechanism can temporarily or indefinitely hold up actual data movement into the data buffer to allow for temporary buffering and interface speed matching as data is transferred to the host interface.

Abstract: A method for allowing appliance-to-appliance communication transactions wherein an appliance communications manager that stands apart from source and destination appliances receives a connection request from a source appliance. A phonebook having a plurality of phonebook entries, and stored in the appliance communications manager, is then accessed. Each of the phonebook entries includes a destination appliance identifier and associated destination appliance communication information. A user of the source appliance is presented with a list having a plurality of the phonebook entries. The appliance communications manager receives the identity of a destination appliance selected from said list and, via the appliance communications manager, a communication link is established with the selected destination appliance. When a communication message is received from the source appliance, the communication message is sent to the selected destination appliance.

Abstract: A system, computer program product and method for servicing requests. A server may be configured to receive a stream of requests to access particular logical block addresses in one or more logical drives in a RAID from one or more clients. The server may be coupled to one or more RAID adapters that are coupled to the RAID. The server may comprise a software RAID and each RAID adapter may comprise a hardware RAID. By monitoring the utilization of the processors in the server and in each RAID adapter, all or part of these received requests may subsequently be routed to either the software RAID or the hardware RAID based on which implementation is more desirable to service these requests.

Abstract: A circuit comprising a memory and a logic circuit. The memory may be configured to read and write data in a plurality of memory queues to/from a write data path and a read data path in response to (i) a first and a second select signal and (ii) a first control signal. The logic circuit may be configured to generate (i) the first and second select signals and (ii) the control signal in response to one or more signals received from a read management path and/or a write management path.

Abstract: The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

Abstract: A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as needed. When the buffer is flushed, groups of memory access commands are selected for flushing whose row/bank addresses are associated, thereby creating page coherency in the flushed memory access commands. Batches of commands may be flushed from the buffer according to a sequence designed to minimize same-bank page changes in frame buffer memory devices. Good candidate groups for flushing may be chosen according to criteria based on the binary bank address for the group, the size of the group, and the age of the group. Groups may be partially flushed. If so, a subsequent flush operation may resume flushing a partially-flushed group when to do so would be more beneficial than flushing a different group chosen solely based on its bank address.

Abstract: A memory controller may include a request queue for receiving transaction information (e.g. the address of the transaction) and a channel control circuit. A control circuit for the request queue may issue addresses from the request queue to the channel control circuit out of order, and thus the memory operations may be completed out of order. The request queue may shift entries corresponding to transactions younger than a completing transaction to delete the completing transaction's information from the request queue. However, a data buffer for storing the data corresponding to transactions may not be shifted. Each queue entry in the request queue may store a data buffer pointer indicative of the data buffer entry assigned to the corresponding transaction. The data buffer pointer may be used to communicate between the channel control circuit, the request queue, and the control circuit. In one implementation, the request queue may implement associative comparisons of information in each queue entry (e.g.

Abstract: In one embodiment, a system has a first device, a second device, and two sets of bi-directional buses that couple the first and second devices. The devices are to perform transactions with each other over the buses, such that each set of buses has a dominant, but not exclusive, direction, for sending transaction information and data, that is opposite the other. This configuration may allow the number of turnaround cycles on split transaction buses to be reduced, thus helping increase bandwidth.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: In an example embodiment, a data transfer method adaptively transfers data from a host device to a target device across a channel-based interconnect. The method includes determining whether or not the size of the data to be transferred is greater than the maximum payload of a cell for the channel-based interconnect. If the size of the data to be transferred is not greater than the maximum payload, then a single cell is transferred from the host device to the target device which includes all of the data. If the size of the data to be transferred is greater than the maximum payload, then a request message is transferred from the host device to the target device. The request message includes a portion of said data to be transferred and control information indicating that not all of the data to be transferred is included in the request message.

Abstract: A hardware-based linked list queues memory transactions in a memory controller. The memory controller includes a plurality of memory controller agents. Each agent has a head flag, a tail flag, and a next agent field, thereby allowing the agents to be arranged into linked lists. Memory transactions are received from cacheable entities of a computer system at an incoming memory transaction dispatch unit via an interconnection fabric. The incoming transactions are then presented to the plurality of agents. For each incoming read transaction, one of the agents will accept the transaction. If there are pending memory read transactions for the memory line, then the accepting agent joins a linked list of agents that are queued up to access that memory line. The accepting agent drives its index out onto a bus that connects all agents. One agent in the linked list will have its tail flag set, and that agent will clear its tail flag and latch into its next agent field the index provided by the accepting agent.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: A method and apparatus for calculating an expected access time associated with one of a plurality of disk drive commands employs one or more neural networks. A plurality of disk drive commands received from an external source are stored in a memory, typically in a queue. Using a neural network, an expected access time associated with each of the queued commands is determined. Determining the expected access time associated with each of the queued commands involves determining a time for performing a seek and settle operation for each of the queued commands and a latency time associated with each of the queued commands. The command indicated by the neural network as having a minimum expected access time relative to access times associated with other ones of the queued commands is identified for execution.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.