Abstract: A target device in a computer bus system allocates resources by selecting a priority requester for allocation of scarce resources. In a non-bus arbiter configuration, the first initiator device to receive a retry response to a transaction request after the resources are exhausted is designated as a priority requester. In a bus arbiter configuration, the priority requester is chosen on a round-robin basis from initiator devices that received a retry response to the initiator's most recent transaction request. If only one resource is available when an initiator sends a transaction request, the initiator receives a retry response unless the initiator is the priority requester.

Abstract: A technique for implementing a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of first-in-first-out (FIFO) queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high-speed cache portion that resides in high-speed memory and a low-speed high-density portion that resides in low-speed high-density memory. Each high-speed cache portion contains FIFO data that contains head and/or tail information associated with a corresponding FIFO queue. The low-speed high-density portion contains FIFO data that is not contained in the high-speed cache portion. A queue identifier (QID) directory refills the high-speed portion of one or more queues with data from a corresponding low-speed portion. Queue head start and end offsets are used to determine whether a corresponding queue is empty.

Abstract: An apparatus, method and program product for controlling the transfer of data in a data processing system having a processor handling an I/O request in an I/O operation, main storage controlled by the processor for storing data, and one or more I/O devices for sending data to or receiving data from said main storage. The apparatus includes a vector mechanism operable to register I/O requests by the devices to send or receive data from said main storage. A dispatcher is included which is operable to poll the vector mechanism to determine if there is an outstanding I/O request. An override bit has a first condition when an immediate interrupt is to be sent to the processor for handling an I/O request from the I/O device(s), and a second condition when the dispatcher is to poll the vector mechanism to determine if there is an outstanding I/O request. The override bit is set to its first condition or reset to its second condition by the processor.

Abstract: An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Abstract: A clustered computer system includes a shared data storage system, preferably a virtual shared disk (VSD) memory system, to which the computers in the cluster write data and from which the computers read data, using data access requests. The data access requests can be associated with deadlines, and individual storage devices in the shared storage system satisfy competing requests based on the deadlines of the requests. The deadlines can be updated and requests can be killed, to facilitate real time data access for, e.g., multimedia applications such as video on demand.

Abstract: In one of the many embodiments disclosed herein, a method for dispatching read and write requests to a memory is disclosed which includes queuing at least one write request in a write queue and queuing an incoming read request in a read queue. The method also includes comparing the read request with at least one write request in the write queue to detect a matching write request, and if there is a matching write request, storing a write queue index of the matching write request as a first entry in an ordering queue. The method further includes dispatching the at least one write request to the memory in response to the first ordering queue entry.

Abstract: In a multiprocessor system in which a plurality of processors share an n-way set-associative cache memory, a plurality of ways of the cache memory are divided into groups, one group for each processor. When a miss-hit occurs in the cache memory, one way is selected for replacement from the ways belonging to the group corresponding to the processor that made a memory access but caused the miss-hit. When there is an off-line processor, the ways belonging to that processor are re-distributed to the group corresponding to an on-line processor to allow the on-line processor to use those ways.

Abstract: Data is moved between zones of a central processing complex via a data mover located within the central processing complex. The data mover moves the data without sending the data over a channel interface and without employing processor instructions to perform the move. Instead, the data mover employs fetch and store state machines and line buffers to move the data.

Abstract: An image data input device comprises a scanner, which has a SCSI driver and a connector, and a personal computer, which has a SCSI cable. The scanner is connected to the personal computer through the SCSI driver, the connector and a SCSI cable. The scanner is provided with an EEPROM, in which an application program, for processing digital image data obtained by the scanner, and an installation program are stored. The personal computer recognizes the EEPROM as an external storage, and performs an installation operation of the application program when the scanner is connected to the personal computer.

Abstract: A disk drive is disclosed wherein a write command is verified according to a rotational position optimization (RPO) algorithm rather than immediately after the write command to better optimize drive performance relative to mechanical latencies.

Abstract: A method for enabling a Q_key that is tamper proof from applications on a distributed computer system to protect selected network operations is provided. Applications and an operating system (OS) execute on the end nodes and each may access various network resources. In the invention, the network resources are configured for selective access by particular applications or OS. In a preferred embodiment, a control bit of a Q_key, which allows applications to authenticate their use of particular communication resources, i.e., the send and receive queues, is reserved and utilized to signal whether a particular application is allowed access to the resources. Setting the control bit to 0 allows the Q_key to be set by an application directly. When the control bit is set to 1, the Q_key cannot be set by an application and can only be set using a privileged operation performed only by the OS.

Abstract: A coherency resolution technique enables efficient resolution of data coherency for packet data associated with a service queue of an intermediate network node. The packet data is enqueued on a write buffer prior to being stored on an external packet memory of a packet memory system. The packet data may be interspersed among other packets of data from different service queues, wherein the packets are of differing sizes. In response to a read request for the packet data, a coherency operation is performed by coherency resolution logic on the data in the write buffer to determine if any of its enqueued data can be used to service the request.

Abstract: A hardware command queue for mass storage systems having a memory device. A plurality of entries are defined in the memory device, at least some of which are active entries. At least some of the active entries correspond to pending access commands and at least one entry is a head entry corresponding to an in-flight access command. A physical target location is stored in each active entry and a computed servo distance value is stored in each active entry. A link list including pointers defining an execution sequence is stored with the command queue.

Abstract: In a disk array system of the present invention, each host or disk interface unit is connected to each shared memory unit through a switch unit. The switch unit includes the number of packet buffers greater than the number of the host or disk interface units connected thereto, and can always hold the number of access requests greater than the number of the host or disk interface units. The disk array system uses the packet buffers to compensate for a transfer rate difference between the host interface units and the shared memory units, thereby allowing connection of the host interface units having different performance. The disk array system improves the efficiency of usage of internal paths without increasing the number of I/O ports of the switch unit. The system throughput is thereby improved, and the support for host I/Fs having different performance is thereby facilitated.

Abstract: A disk drive is disclosed which links disk commands that access near sequential data sectors. The linked and non-linked disk commands are inserted into an input/output queue and selected for execution according to a rotational position optimization (RPO) algorithm. If an error occurs while executing a linked disk command, the disk commands are unlinked and at least one of the unlinked disk commands is executed. The residual unlinked disk commands are inserted back into the input/output queue for later execution in an order determined by the RPO algorithm.

Abstract: Methods and apparatus are disclosed for communication between appliances. In one embodiment, the method comprises receiving at an appliance communications manager that stands apart from source and destination appliances, a connection request from a source appliance, receiving at the appliance communications manager destination appliance communication information for a destination appliance, and receiving at the appliance communications manager a communication message from the source appliance. The method additionally comprises storing the communication message in a data memory of the appliance communications manager, establishing, via the appliance communications manager, a communication link with the destination appliance, and transferring the stored communication message to the destination appliance via the communication link.

Abstract: A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

Abstract: A technique for decreasing VLAN lookup times in hardware-based packet switches by emulating the functionality of a content addressable memory (CAM) with software and random access memories (RAM). The decrease in lookup time is achieved by using content from the data packet to index directly into a table that stores forwarding information. Since the forwarding information is addressed directly by content from the packet, the need to spend time and resources sorting through the table of forwarding information with a key search is eliminated.

Abstract: A method and apparatus for a burst mode write in a shared bus architecture comprising detecting a write data burst, determining if at least one memory unit is available to receive the write data burst, writing the write data burst to the at least one memory unit if the at least one memory unit is available to receive data. Storing a first portion of the write data burst in a buffer, concurrently with activating the at least one memory unit to receive data, if the at least one memory unit is not available to receive data; writing a second portion of the write data burst to the at least one memory unit when the at least one memory unit is available to receive data, and writing the first portion of the write data burst from the buffer to the at least one memory unit after writing the second portion of the write data burst.

Abstract: A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.

Abstract: A virtual channel buffer of a transaction scheduler in a computer system I/O node. A control unit includes a plurality of scheduler units. Each scheduler unit may include a first and a second buffer circuit. The first buffer circuit may include a first plurality of buffers and the second buffer circuit may include a second plurality of buffers, each of which are coupled to receive control commands from a first and second source, respectively. Each buffer of the first and the second plurality of buffers corresponds to a respective virtual channel of a plurality of virtual channels and may be configured for storing selected control commands that belong to said respective virtual channels. Each scheduler unit may also include an arbitration unit for arbitrating between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit.

Abstract: In a first form, a method for managing requests in a disk array having a number of disks includes associating priorities with respective requests. A new request is processed, which includes determining a maximum priority for at least certain ones of requests received and comparing the priority of the new request to the maximum priority. Responsive to the comparison, a selection is made between i) categorizing the new request as a foreground disk operation and ii) categorizing the new request as a background disk operation. A selection is also made between i) working the new request on at least one of the disks and ii) placing the new request in a queue.

Abstract: A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Abstract: A printing apparatus discriminates whether received print data is print data converted into a job packet constructed by a header portion and a data portion or print data which is not converted into a job packet and switches the processing operation in accordance with the print data.

Abstract: A hard disk unit includes a disk, controller microprocessor, host bus interface, buffer memory, buffer memory controller and disk formatter. The bus interface receives write operations, and the corresponding write operation data is stored in the buffer memory. The buffer memory controller also includes a set of address registers and a set of block count registers. The microprocessor loads the address registers with the buffer memory addresses of data of multiple write operations and loads the block count registers with the size of the corresponding data. The microprocessor then issues a single command to the buffer memory controller to transfer the data from the buffer memory to the disk formatter. The address registers and block count registers enable the data of multiple write operations to be transferred and written to a disk in an order other than the order in which the write operations were received at the bus interface.

Abstract: A microprocessor includes a register and a comparator. The register stores an address area, the address area requiring a guarantee of an access order. The comparator compares an address of the address area held in said register with an address of an address area indicated in an access request from CPU, and outputs a signal to execute an access request succeeding the access request from the CPU after executing an access request preceding the access request from the CPU when the address area indicated in the access request from the CPU matches the address area held in said register.

Abstract: An apparatus for initiating partial transactions in a peripheral interface circuit for an I/O node of a computer system. An apparatus for performing partial transfers on a peripheral bus in response to a request for a stream of data includes a data buffer coupled to a control unit. The data buffer may be configured to store one or more data packets each containing data forming a portion of the data stream. The control unit may be configured to determine the presence of data packets stored in the data buffer that collectively contain a sequence of data forming a portion of the data stream. The control unit may be further configured to cause the sequence of data to be conveyed on the peripheral bus.

Abstract: The present invention is directed to a system and method for tuning retry performance of read requests of data from electronic data storage devices. In an aspect of the present invention, a method for performing a delayed read in an electronic data storage system having an initiator and a target device may include initiating a delayed read by the initiator to the target device and issuing at least one delayed read. The initiator then delays for a programmed interval before reissuing the at least one delayed read.

Abstract: Systems and methods for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir for reducing or eliminating device buffers is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Analysis factors include how much data is remaining in the data reservoir, how long will that data last, and how long until the channel will be analyzed again. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future.

Abstract: A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to “post” a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time.

Abstract: The present invention provides an apparatus, system and method for providing a generalized queue pair for use with host channel adapters of a system area network. With the apparatus, system and method, the hypervisor of a host channel adapter maintains a P_Key table for each logical port of the host channel adapter. When a request is received to allocate a queue pair from a requestor application associated with a logical port, a P_Key mode is set in a control register associated with the queue pair based on the type of requestor application that sent the request. Based on this P_Key mode, one or more P_Keys from a P_Key table associated with the logical port from which the request was received are written to one or more P_Key registers allocated to the queue pair. These P_Keys are then used to perform P_Key checks of incoming data packets. In addition, these P_Keys are inserted into headers of outgoing data packets.

Abstract: An adaptive maximum seek velocity clipping technique is employed in a disk drive to reduce head movement power requirements. Separate maximum seek velocities are established for respective categories of access commands, where the categories are defined by seek distance and estimated extra latency. The maximum seek velocity established for each category of access commands reflects actual experience in executing access commands of the given category. The maximum seek velocity values for the various categories are stored in a maximum seek velocity table, which is referred to upon execution of access commands. The inventive power-saving technique may be advantageously applied in conjunction with a probability-based shortest access time first (SATF) command queue ordering algorithm.

Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Abstract: A sectioned ordered queue in an information handling system comprises a plurality of queue sections arranged in order from a first queue section to a last queue section. Each queue section contains one or more queue entries that correspond to available ranges of real storage locations and are arranged in order from a first queue entry to a last queue entry. Each queue section and each queue entry in the queue sections having a weight factor defined for it. Each queue entry has an effective weight factor formed by combining the weight factor defined for the queue section with the weight factor defined for the queue entry. A new entry is added to the last queue section to indicate a newly available corresponding storage location, and one or more queue entries are deleted from the first section of the queue to indicate that the corresponding storage locations are no longer available.

Abstract: In a method for adaptive arbitration of requests for accessing a memory unit in a multi-stage pipeline engine that includes a plurality of request queues corresponding to the stages of the pipeline engine, each of the request queues is assigned to one of a high-priority group and a low-priority group in accordance with an operating state of the memory unit. The request queues in the high-priority group are then processed prior to the request queues in the low-priority group.

Abstract: An input/output hub includes an inbound ordering queue (IOQ) to receive inbound transactions. All read and write transactions have a transaction completion. Peer-to-peer transactions are not permitted to reach a destination until after all prior writes in the IOQ have been completed. A write in a peer-to-peer transaction does not permit subsequent accesses to proceed until the write is guaranteed to be in an ordered domain of the destination. An IOQ read bypass buffer is provided to receive read transactions pushed from the IOQ to permit posted writes and read/write completions to progress through the IOQ. An outbound ordering queue (OOQ) stores outbound transactions and completions of the inbound transactions. The OOQ also issues write completions for posted writes. An OOQ read bypass buffer is provided to receive read transactions pushed from the OOQ to permit posted writes and read/write completions to progress through the OOQ.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: An input/output control apparatus controls input/output requests from a host unit to a plurality of subordinate unit. A priority order managing section in the input/output control apparatus controls a priority order of the input/output requests based on priority orders of the input/output requests given by the host unit, for each of the subordinate units.

Abstract: A system and method that uses a pluggable preprocessor for monitoring a running job data stream that looks for header information to determine the appropriate queue for the job data stream. The data stream is then routed to the appropriate queue. The header information typically comprises a job name, an owner, and routing information. Thus, a print job will appear in the appropriate queue immediately while it is still being spooled. A job scheduler can trigger processing of the job when the processor is available and the job is ready for processing. This facilitates the handling of many jobs simultaneously segregated into their respective priority queues as soon as the clients send the jobs. Processing may then be serialized based on the processor load and job scheduling logic.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.

Abstract: An input/output request sent from a host is once cued through a channel adapter and is then transferred to a resource manager and is cued, and the cuing is distributed. Even if sequential input/output requests of the host are separated through a distribution processing to a plurality of paths, they are recognized on the device controller side and a countermeasure is taken. In the case in which a path from the host to the device controller is caused to be redundant into an operation system and a standby system, a path confirmation command is issued to the device drivers of a standby system path in order to confirm that the standby system path is normally operated or not.

Abstract: An information processing apparatus, disposed between a controlling portion and hardware, for performing a process corresponding to a program that contains capsulated process portions for controlling the hardware in response to messages received from the controlling portion. The program includes a first process portion for communicating with the controlling portion; a second process portion for communicating with first and second hardware; a third process portion for communicating with the first process portion and the second process portion and executing an interfacing process corresponding to the first hardware; and a fourth process portion for communicating with the first process portion and the second process portion and executing an interfacing process corresponding to the second hardware. The first process portion outputs a message to either the third process portion or the fourth process portion corresponding to a message received from the controlling portion.

Abstract: A system and method for processing I/O requests in a computing system. I/O packets are created via an operating system associated with the computing system, where the I/O packets include I/O transaction information. The I/O packets are made accessible to an I/O system. A command for a channel type connecting a target I/O component to the I/O system is constructed, where this command construction is based on the I/O transaction information provided in the I/O packet, and based on physical aspects of the target I/O component and channel type provided independently of the I/O packet. The constructed command is issued to the target I/O component in accordance with the channel type.

Abstract: An apparatus comprising one or more storage elements. The one or more storage elements may be configured to switch an input/output between a first domain and a second domain in response to one or more control signals.

Abstract: One embodiment comprises an apparatus for reordering requests for access to a subdivided resource. The apparatus includes a non-FIFO request buffer for temporarily storing the requests for access, a selector for selecting a next request from the request buffer, and a mechanism for outputting the next request to a controller for the resource. Another embodiment comprises a method for reordering requests for access to a subdivided resource. The method includes temporarily storing the requests for access, selecting a next request from among the stored requests in non-FIFO order, and outputting the next request to a controller for the resource.

Abstract: A method and apparatus for reducing latency due to set up time between DMA transfers are described. The method comprises initiating arbitration of DMA channel requests prior to completion of a current DMA transfer; and initiating set up for a next DMA transfer prior to completion of the current DMA transfer according to the arbitration. One implementation of the apparatus includes one or more DMA channel interfaces providing a series of DMA channel requests such that a DMA channel request for a next DMA transfer is provided before a current DMA transfer is completed; and a DMA controller that initiates arbitration of DMA channel requests after they are provided by the one or more DMA channel interfaces and before the current DMA transfer is completed, and initiates set up for the next DMA transfer prior to completion of the current DMA transfer according to the arbitration.

Abstract: A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to “post” a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time.

Abstract: One aspect is directed to a method and apparatus for transferring information, through a shared storage system, between first and second processes running on first and second computers, respectively. Both computers are coupled to a data storage system, with the first computer being coupled through multiple paths. In accordance with one aspect of the invention, at least one of the multiple paths is selected through which to transfer the information between the first process and the data storage system, so that communication between the first process and the shared storage system is not constrained to any particular path. Another aspect is directed to a method and apparatus for processing an out of band control command executed by a host computer in a multi-path system and targeting a device.

Abstract: A system and method are provided for hard disk drive command queue ordering with locational uncertainty of commands. For each command in the hard disk drive command queue, an expected access time is calculated utilizing a probability distribution for a currently executing command and a probability distribution for a candidate command. A command in the hard disk drive command queue having a minimum calculated expected access time is identified. Then the identified command having a minimum calculated expected access time is executed. The probability distribution for a currently executing command represents an ending location distribution for the currently executing command. The probability distribution for a candidate command represents a starting location distribution for the candidate command.

Abstract: A data queue system comprises plural memory blocks defined in memory, and a queue which comprises a number of memory blocks each including a link to the following block in the data queue. A queue descriptor includes identities which identify: the final block in the queue, the memory location where the most recent read commit occurred (and optionally an offset from a predetermined location in that block), the memory location where the most recent write commit occurred (and optionally an offset from a predetermined location in that memory block), the size of the blocks, the memory location the most recent write occurred, the number of unused blocks, the number of blocks which contain data to be read, the type of data queue, the memory location where the most recent read occurred and the number of blocks which have been read since the most recent read commit.