Abstract: A system for handling write requests is described. The system uses two queues for storing posted write requests. When a posted write error results, software handles the posted write error using information stored in a first queue of the two queues. The write request producing the posted write error is cleared from the second queue which continues to handle physical packets containing write requests.

Abstract: This invention (The Customer Contact Channel Changer) enables the integration of different Customer Contact Channels such as live call centre ACD (Automatic Call Distribution) agents, ADSI (Analog Display Services Interface) enhanced IVR (Interactive Voice Response) systems and WWW (World Wide Web) servers. The world wide web servers are used to allow customers with computer equipment to access information from an organizations databases in a self service mode. Frequently these customers have questions best answered by human ACD agents. With this invention the connection between the customer with the question and the agent with the answer is done quickly and efficiently with both parties sharing screens of common information. Also control is retained by the customer to make the call happen when they want it.

Abstract: A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the asynchronous bus is bounded. A first device is coupled to the asynchronous bus to receive an isochronous transaction from an isochronous device and output the isochronous transaction to the asynchronous bus. A second device is coupled to the asynchronous bus to receive the isochronous transaction from the asynchronous bus and output the isochronous transaction to a third device.

Abstract: Data communications device and method for arbitrating access to a system memory of the communications device via a peripheral component interconnect (PCI) bus in a network interface having a memory management unit for managing transmit data transfers from the system memory to a transmit buffer memory, and receive data transfers from a receive buffer memory to the system memory. The memory management unit includes an arbitration block having an arbiter state machine, which receives requests for access to the PCI bus in order to provide the transmission and reception of data, descriptors and status information. The arbiter state machine grants the PCI bus access to a request having a higher priority in accordance with a preset priority scheme.

Abstract: A method for specifying devices able to handle device requests in a computing network environment comprising a main memory having a queuing mechanism with a plurality of queues in processing communication with an adapter and a plurality of devices and/or processors. The format and attributes of devices in said the environment is determined as well as the size and attributes of the queues. When a request for data processing is received from at least one input/output device capable of attaching to the computing environment, the characteristics of any processors or device capable of processing the data is determined. A special store subchannel command is issued specifying which device or processor the request can be sent to after analyzing all information about the size, characteristics and attributes previously gathered. In this way information is provided about which processor or device can process the information using the special store subchannel command.

Abstract: A microprocessor having a logic control unit and a memory unit. The logic control unit performs execution of a number of instructions, among them being memory operation requests. A memory operation request is passed to a memory unit which begins to fulfill the memory request immediately. Simultaneously with the memory request being made, a copy of the full memory request is made and stored in a storage device within the memory unit. In addition, an identification of the request which was the origin of the memory operation is also stored. In the event the memory request is fulfilled immediately, whether it be the retrieval of data or the storing of data, the results of the memory request are provided to the microprocessor. On the other hand, in the event the memory is busy and cannot fulfill the request immediately, the memory unit performs a retry of the memory request on future memory request cycles.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

Abstract: A queuing method and apparatus for receipt and transfer of incoming and outgoing data inn a network environment having a main storage. The mechanism includes at least one set of dedicated input queues and at least another set of dedicated output queues. In addition a plurality of queuing components is also provided that include attributes of devices to and from which data is to be transferred or received, and information about the queuing mechanism itself. The input and output queues also comprise an information block containing address of all input and output queues, a storage information block providing information about the queuing mechanism and storage list information blocks that defined for each queue containing specific information about that queue itself.

Abstract: An apparatus and method for accessing a data item from a storage system having a plurality of data storage devices are disclosed. I/O operation requests are submitted to multiple data storage devices for each data item to be accessed. The I/O operation requests are issued to copies of the data items that reside on a plurality of data storage devices. More I/O operation requests are submitted than the number of data items that are to be accessed, written, or updated.

Abstract: A method of managing a storage system which includes a local and remote systems is provided. Link services between the two subsystems are provided though the use of a task queue. The task queue resides in a global memory of the local storage system and receives requests from the various host controllers, device, and remote controllers connected to the local storage. The remote controllers of the local storage service the requests placed in the task queue to enable data transfer between the local and remote storage systems. The task queue may be a doubly linked list of records including forward and backward pointers in addition to the request data. A two level locking scheme is employed to prevent the addition of incompatible requests to the queue and to enable maximum parallelism in servicing requests in the queue. The first level of locking applies to the entire queue and is used when records are added to and deleted from the queue. The second level of locking applies to the individual queue records.

Abstract: A data storage system receives multiple data streams, such as a telephone messages, each of which are to be stored in a multidisk array. The data storage system generates a disk write request for each data stream. The disk write request is allocated to a disk in the multidisk array that has the highest weighted available space. The weighted available space of each disk is determined by the space availability of the disk and the load on the disk relative to other disks in the multidisk array. Optionally, the method used to allocate the disk space availability is dependent upon the disk write request load level. Thus, if the request load level is in a first load range, a least full assignment method is used, if the request load level is in a second range, a round robin method is used and if the request level is in a third range the weighted available space method is used.

Abstract: A method and apparatus for asynchronously sharing a networked backup device among multiple users. A series of processes opportunistically perform operations, broadcast requests for physical media based upon the operations, and provide a series of canceling and status checking interfaces for users.

Abstract: A method and data storage system using the method, provides an efficiently approach for allocating a static amount of buffer space (e.g., records) among a number of logical volumes of a data storage system on the basis of the computing environment within which the data storage system is used. The method includes providing the data storage system from logical volumes, each including a command queue. Each command queue includes records, each for storing a command request. A memory pool is established from which one or more records can be allocated to each command queue associated with each logical volume. The memory pool has a predetermined number of records which can be allocated by the command queues of the logical volumes. Based on the computing environment, one of a number of allocation schemes for allocating records to a command queue is selected.

Abstract: This invention (The Customer Contact Channel Changer) enables the integration of different Customer Contact Channels such as live call centre ACD (Automatic Call Distribution) agents, ADSI (Analog Display Services Interface) enhanced IVR (Interactive Voice Response) systems and WWW (World Wide Web) servers. The world wide web servers are used to allow customers with computer equipment to access information from an organizations databases in a self service mode. Frequently these customers have questions best answered by human ACD agents. With this invention the connection between the customer with the question and the agent with the answer is done quickly and efficiently with both parties sharing screens of common information. Also control is retained by the customer to make the call happen when they want it.

Abstract: A method and apparatus is provided in which I/O data is tagged to identify an ordering of data transfer requests relative to other data transfer requests. Write and Read transaction requests are tagged for ordering relative to previous write requests. Current read and write transaction requests are selectively allowed to bypass earlier write transaction requests which have been temporarily delayed in transfer. In one embodiment, the bypass occurs in a bridge buffer positioned between I/O devices and a system memory. In another embodiment, the methodology is applied where a split read or write transaction includes reserved bits in the attribute fields which are utilized to indicate if the transaction is allowed to bypass previous write transactions.

Abstract: System and method for scheduling I/O requests in a multi-tasking data processing environment. An I/O request issued by an application is placed in an I/O request holding queue. Under control of the requesting application (or, alternatively, the operating system), the I/O request is selectively canceled or moved to a service pending queue for execution. Requests can be moved either by the application or by the Operating system when an I/O completes (and hence the service pending queue has room for another IO).

Abstract: A method is described for controlling pipelined memory access requests in an AGP-compliant computer system. Memory access requests are stored in separate write and read request queues. To control the ordering of the write and read requests relative to one another, each of the requests has an associated age tag assigned to it. In the event a read request is received, an age tag value is assigned to it that corresponds with the number of previously received and currently pending write requests. Similarly, when a write request is received, an age tag value is assigned that corresponds with the number of previously received and currently pending read requests. Employing such age tags provides AGP-compliant ordering of the write and read requests, while also providing write-passing-read capability without the attendant complex logic circuitry and time delays associated with conventional AGP implementations.

Abstract: A hazard control circuit for a cache controller that prevents overwriting of modified cache data without write back. The cache controller controls a non-blocking, N-way set associative cache that uses a write-back cache-coherency protocol. The hazard control circuit prevents data loss by deferring assignment until after completion of a pending fill for that way. The hazard control circuit of the present invention includes a transit hazard buffer, a stall assertion circuit and a way assignment circuit.

Abstract: A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

Abstract: The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a manner of switching for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a manner of configuration for prioritizing access requests by the plurality of master buses to the plurality of slave buses via the switching means. The cross-bar switch of the present invention has the capability of prioritizing requests between multiple parallel high speed buses. In a preferred embodiment, this arbitration is accomplished through Configuration Registers on the cross-bar switch. The Configuration Registers are programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmed and changed by a processor in a larger system.

Abstract: Disclosed is a system, method, and program for selecting an input/output (I/O) command in a queue of I/O commands. Each I/O command operates within a range of addressable locations on a storage medium. Each addressable location is defined according to a sector number and track number. The program makes use of a plurality of buckets, wherein each bucket represents a range of consecutive sector numbers. Each queued I/O command is associated with a bucket such that a sector number of an addressable location in which an I/O command operates is within the range of sectors comprising the associated bucket. A reference position is determined. A selection routine is then executed to select an I/O command. The selection routine selects a bucket including at least one I/O command and selects an I/O command within the selected bucket. The routine then determines whether the selected I/O command meets a selection criteria. The routine indicates the selected I/O command as the I/O command to process.

Abstract: A multiple logical FIFO system uses a single main register file to store payload data in association with link data so as to form one linked list data structure for each logical FIFO in the system. A write pointer register file stores one write pointer for each logical FIFO. A read pointer register file stores one read pointer for each logical FIFO. A free register identifier indicates a free register address at all times unless the overall system is full. The free register address corresponds to one free register within the main register file. In a first embodiment, the free register identifier is implemented using a priority encoder. In a second embodiment, the free register identifier is implemented using a conventional FIFO buffer. In a third embodiment, the free register identifier is implemented using one of the logical FIFO buffers stored in the main register file.

Abstract: A data processing system and method for substituting selected requests with substitute requests that perform the same or similar end function but achieve increased system performance are disclosed. Those requests that have a selected request characteristic are identified and converted or replaced with a predetermined substitute request. The substitute requests perform at least part of the function of the identified requests. The data processing system may include two or more processors, and the selected request characteristic may be that a write data packet of an identified write request was not changed by a first processor. A substitute request may update directory information associated with the identified write request but may not write to associated data packet to memory. The directory information can indicate whether identified memory locations are currently owned by a processor.

Abstract: A method and apparatus for providing very large logical volumes (Meta Device) in a storage system is provided. The storage system includes host controllers and disk controllers which communicate through a shared memory. I/O requests are received by the host controller and placed into request queues. The request queues are associated with logical devices. A number of request queues in the host controller are concatenated together to produce the larger logical volume. The large logical volume appears to the host as a single addressable logical unit. I/O requests to the large logical volume are analyzed by the host controller to determine which logical devices are actually needed to service the request. The host controller then makes the appropriate queue entries. Processing of the requests then occurs in the same fashion as if the request had been to a non-Meta Device. This allows the disk controllers and memory to operate without modification.

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Abstract: A system and method for managing the flow of data transfer requests from requesting devices to associated data transfer interconnection circuitry in a data processing system. Data transfers are initiated with data transfer requests that identify a data input queue and data output queue for which the data is to be transferred. The data transfer requests are issued from one or more requesting devices in the system. The data transfer requests are queued at a first queuing level. Within the first queuing level, data transfer requests identifying like data input queues are queued together, yet separate from data transfer requests identifying a different data input queue. Each of the data transfer requests from each of the queues in the first queuing level are transferred to a second queuing level to be queued according to the data output queue identified in the data transfer request. Each queue in the second queuing level stored only those data transfer requests identifying like data output queues.

Abstract: Disclosed is a system and method for processing a data access request (DAR). A processing unit, such as a storage controller, receives a DAR, indicating data to return on a channel, such as a channel connecting to a host system, and priority information for the received DAR. The processing unit retrieves the requested data for the received DAR from a memory area, such as a cache or direct access storage device (DASD), and determines whether there is a queue of data entries indicating retrieved data for DARs to transfer on the channel. The queued DARs include priority information. The processing unit processes at least one data entry in the queue, the priority information for the data entry, and the priority information for the received DAR to determine a position in the queue for the received DAR. The processing unit then indicates that the received DAR is at the determined position in the queue and processes the queue to select retrieved data to transfer on the channel to the host system.

Abstract: A system (100) for automatically ordering a request for access to a system memory (14) is disclosed. The system (100) includes a re-ordering buffer (102) having a data input (120) and a data output (122) and an input request position identifier (104) associated with the re-ordering buffer (102). The input request position identifier (104) indicates a position of the data input (120) in the re-ordering buffer (102) for the new request based on a status of the request. A method (230) of ordering a request for access to a system memory (14) in a buffer (102) is also disclosed and includes initiating a request (232) for access to the system memory (14), wherein the request contains a status indicating a priority of the request. The status of the request is evaluated (234) to determine whether the request is a high priority request or a low priority request and a location for inputting the access request into the buffer (102) is identified (236) in response to the evaluation.

Abstract: A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

Abstract: A system and method for selectively controlling the interface throughput of data transfer requests from request sources to request destinations. The system and method provide a manner in which the flow of data transfer requests from request sources to request destinations are controlled. The data transfer requests from each of the request sources are temporarily stored for future delivery to its addressed request destination. Delivery of the stored data transfer requests to the addressed request destination is enabled according to a predetermined delivery priority scheme. Certain stored data transfer requests are identified to be selectively suspended from being prioritized and delivered to the addressed request destination. The identified data transfer requests are suspended from delivery for a definable period of time.

Abstract: A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory.

Abstract: One embodiment of the present invention provides an apparatus that supports multiple outstanding load and/or store requests from an execution engine to multiple sources of data in a computer system. This apparatus includes a load store unit coupled to the execution engine, a first data source and a second data source. This load store unit includes a load address buffer, which contains addresses for multiple outstanding load requests. The load store unit also includes a controller that coordinates data flow between the load address buffer, a register file, the first data source and the second data source so that multiple load requests can simultaneously be outstanding for both the first data source and the second data source. These load requests return in-order for each of the multiple sources of data in the computer system, except for load requests directed to a data cache which can return out-of-order. Load requests may return out-of-order with respect to load requests from other data sources.

Abstract: A method and system for transmitting data among a plurality of cards in a crossbar interconnect network having a plurality of cards each having source paths and destination paths utilizes a plurality of source arbitrators and a plurality of destination arbitrators each associated with the cards. The source arbitrators generate connection request commands from the source paths requesting access to a desired destination path and broadcasts the request for receipt by all of the destination arbitrators. The destination arbitrator associated with the desired destination path captures the connection request command and processes the command based on whether or not the desired destination path is busy. If the desired destination path is not busy, the destination arbitrator generates a connection command requesting a connection be made between the source path and the desired destination path.

Abstract: The present invention provides a cache memory system which allows a user to update cache memory in advance without adding special hardware. The cache memory system comprises cache memory composed of a plurality of banks, a cache controller which issues an update instruction as directed by a command, and a DMA controller which transfers data. The cache controller has a command register in which a cache update instruction from a central processing unit is stored. When a cache miss occurs or when the cache controller detects that data was written into the command register, the cache controller issues a DMA transfer instruction to the DMA controller.

Abstract: A computer system includes a processor having a cache which includes multiple ports, although a storage array included within the cache may employ fewer physical ports than the cache supports. The cache is pipelined and operates at a clock frequency higher than that employed by the remainder of a microprocessor including the cache. In one embodiment, the cache preferably operates at a clock frequency which is at least a multiple of the clock frequency at which the remainder of the microprocessor operates. The multiple is equal to the number of ports provided on the cache (or the ratio of the number of ports provided on the cache to the number of ports provided internally, if more than one port is supported internally). Accordingly, the accesses provided on each port of the cache during a clock cycle of the microprocessor clock can be sequenced into the cache pipeline prior to commencement of the subsequent clock cycle.

Abstract: In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further than notification of non-error and maintenance status changes are processed with minimal latency.

Abstract: A memory system, and a method for controlling prestaging activities based upon the availability of resources within the memory system. Prestage requests are stored in a shared memory accessible to a resource controller and one or more memory controllers. When the resource controller determines that there are sufficient unused cache memory and sufficient unused memory device back-end bandwidth available to prestage at least one data track, a message is broadcast to all of the memory controllers. Those memory controllers with sufficient unused throughput accept the prestage requests and copy the associated data tracks from the memory devices to the cache memory. Counters are maintained in the shared memory to track the number of prestage requests in the process of being serviced, and the number of prestaged data tracks already buffered in cache memory and waiting to be accessed by an external host.

Abstract: A method and apparatus for queuing commands. An apparatus of the present invention utilizes one or more token queues and a storage block to avoid maintaining multiple separate queues and/or to facilitate reordering of queued elements. The apparatus includes at least one token queue and a token assignment circuit which queues a selected token in a token queue. A storage block stores an element in a slot corresponding to the selected token. One system employing the present invention includes a processor, a bus agent, a memory controller, and a main memory. The memory controller queues tokens representing received commands into appropriate command queues.

Abstract: An apparatus and method for restreaming data that has been queued in a bus bridging device. Data received via a first bus is stored in a first queue. A first portion of the data is output from the first queue onto a second bus while a second portion of the data remains in the first queue. In response to another data value being transferred from the first bus to the second bus before the second portion of the data is output to the second bus, the second portion of the data in the first queue is invalidated.

Abstract: A data storage system and method of scheduling commands in such a data storage system are provided in which commands are stored in a command sort queue and a scheduled command queue. Commands in the command sort queue are sorted and assigned a priority. Eventually, commands in the command sort queue are transferred to the scheduled command queue. Commands in the scheduled command queue are executed without further sorting. The desired queue depth or size of the scheduled command queue is determined as a function of both the queue depth of the command sort queue and a command execution rate value which is indicative of the rate at which commands in the scheduled command queue are executed. The desired queue depth may be dynamically determined using the queue depth of the command sort queue and the command execution rate value as inputs to a look-up table. The data storage system may include a small computer system interface (SCSI) disc (or “disk”) drive which executes commands from a host system.

Abstract: A method and apparatus for supplying new requests to a scheduler in an input-buffered multiport switch involve selecting a request that does not target output channels that conflict with output channels targeted by requests that are already accessible to the scheduler. Specifically, target output channels of requests that are presently accessible to the scheduler are identified and compared to target output channels of requests that are included in a queue of next-in-line requests. The queue of next-in-line requests is reviewed and the highest priority request having no conflicting output channels is supplied to the scheduler. By supplying the scheduler with a new request that targets non-conflicting output channels, the scheduler is presented with a wider range of requested output channels from which to choose in each arbitration cycle. In a first embodiment, one, two, or eight ports are connected to each one of four input/output controllers in a switch having a four-channel switch fabric.

Abstract: A system and method for maintaining security in a distributed computing environment comprises a policy manager located on a server for managing and distributing a security policy, and an application guard located on a client for managing access to securable components as specified by the security policy. In the preferred embodiment, a global policy specifies access privileges of the user to securable components. The policy manager may then preferably distribute a local client policy based on the global policy to the client. An application guard located on the client then manages access to the securable components as specified by the local policy.

Abstract: A method and apparatus for providing very large logical volumes (Meta Device) in a storage system is provided. The storage system includes host controllers and disk controllers which communicate through a shared memory. I/O requests are received by the host controller and placed into request queues. The request queues are associated with logical devices. A number of request queues in the host controller are concatenated together to produce the larger logical volume. The large logical volume appears to the host as a single addressable logical unit. I/O requests to the large logical volume are analyzed by the host controller to determine which logical devices are actually needed to service the request. The host controller then makes the appropriate queue entries. Processing of the requests then occurs in the same fashion as if the request had been to a non-Meta Device. This allows the disk controllers and memory to operate without modification.

Abstract: A system for, and method of, off-loading network transactions from a mainframe to an intelligent input/output device, including off-loading message queuing facilities. A storage controller has a processor and a memory, in which the controller receives I/O commands having corresponding addresses. In the controller memory, a communication stack is provided for receiving and transmitting information on a network. In addition, a message queue facilities (MQF) is provided that cooperates with the communication stack and that is responsive to a message queue verb. The MQF causes the communication stack to provide information to a queue in the MQF or causes a queue in the MQF to provide information to the communication stack. Moreover, interface logic is provided in the controller memory and is responsive to the I/O commands, to determine whether an I/O command is within a first set of predetermined I/O commands.

Abstract: A method and apparatus provide input/output allocation between a host and a data storage system. Input/output allocation is accomplished by organizing logical volumes (e.g., disk drives) in the data storage system and queuing requests to the data storage system in a manner which increases the speed and throughput of input/output (I/O) operations. The data storage system is provided from a plurality of logical volumes, each of the logical volumes including a command queue. A master command queue is established from one of the command queues of the logical volumes. The master command queue receives command requests from the host, each command request including an address of data being requested. Each command request is received from the host and stored in the master command queue. The logical volume where the address of the data associated with each command request resides is determined. Each command request is then forwarded to the logical volume where the data being requested resides.

Abstract: It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started.

Abstract: The present invention relates to a slot control method of a multi-port network switch and a switch structure therefor. More particularly, the present invention relates to a slot control method of a shared memory structure with a fixed sequence and a dynamic slot effect. According to the present invention, a slot processor is provided in a slot controller of a network switch for controlling and sequentially allowing a plurality of transportation ports connected to the slot controller to perform data transmission in a fixed round-robin manner while a maximum allowable slot time is set. The slot controller continuously detects whether active transportation port sends an operation request signal or whether the maximum allowable slot time is exceeded. If there is no operation request signal or the allowable slot time is exceeded, data transmission of the next transportation port is allowed and performed immediately, thereby reducing the packet latency.

Abstract: A system and method for high speed transferring of bus operations which are preferably strictly ordered in a processing system is provided. A system and method in accordance with the present invention comprises issuing a plurality of bus operation requests by a processor and determining if a first response has been received by the same processor indicating that one of the plurality of bus operation requests should be reissued. Then, if the first response is received, the processor provides a second response indicating that at least another of the issued bus operation requests should be reissued.

Abstract: A system and method is provided for enhancing the efficiency with which commands from and initiating device to a resource are processed by the resource. The system includes a command queue, a plurality of command reorder slots coupled to the command queue, and command selection logic coupled to the resource and the command reorder slots. Commands ready for processing are loaded into the command reorder slots, and the command selection logic applies an efficiency criterion to the loaded commands. A command meeting the efficiency criterion is transferred to the resource for processing. The system may also include response reordering logic, which is coupled to the command reorder logic. The response reorder logic returns to original command order data provided in response to reorder read commands.