Abstract: Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: Commands received from an apparatus that does not support virtual channels are assigned to a virtual channel. A command receiver 210 receives, from an external command transmitting entity that does not support virtual channels, a command designating an address. An assignment information storage unit 228 stores an assignment table in which an address space is divided into a plurality of areas and a channel is assigned to each area. A command storage unit 230 contains queues provided for respective channels, wherein each queue stores received commands temporarily. A distribution destination specifying unit 224 specifies a queue corresponding to an address by referring to the assignment table, and an execution unit 222 transfers the received command to the command storage unit 230 that corresponds to the specified queue.

Abstract: A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor.

Abstract: In a system in which an information processing apparatus and a peripheral are connected to each other. Initially, the information processing apparatus transmits, to the peripheral, a request to use a service provided by the peripheral. The peripheral determines whether to grant use permission to the received request, and notifies the information processing apparatus which has transmitted the request of the determination result. The peripheral stores information associated with the information processing apparatus to which use permission is granted in response to the request. The information processing apparatus then receives, from the peripheral, a response to the request.

Abstract: An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section (501) receives an I/O request issued from an external device (600). A process-information storage section (510) stores an I/O-request delay time (512) for each external device (600). A priority-process judgment section (520) registers the I/O request having a maximum I/O-request delay time (512) among the I/O requests which have been registered into an I/O-request cue (540).

Abstract: One embodiment of an interface request arbitration system comprises a queue for holding individual processing requests from at least one application process and an interface request arbiter which dynamically chooses to pass a request at the head of the queue to either a real-time interface of an external system that handles the request or a batch interface to the external system.

Abstract: Input/output (I/O) requests generated by processes are typically stored in I/O queues. Because the queued I/O requests may not be associated with the processes that generated them, changing a process' priority may not affect the priority of the I/O requests generated by the process. Therefore, after the process' priority has been increased, it may be forced to wait for an I/O handler to service its I/O request, which may be stuck behind an I/O request generated by a lower priority process. Functionality can be implemented to associate the processes' priorities with the I/O requests generated by the processes. Also, reordering the queued I/O requests to reflect changes in the processes' priorities can ensure that the I/O requests from high priority processes are serviced before the I/O requests from low priority processes. This can ensure efficient processing and lower wait times for high priority processes.

Abstract: An enhanced fibre channel adapter with multiple queues for use by different server processors or partitions. For a non-partitioned server, the OS owns the adapter, controls the adapter queues, and updates the queue table(s). An OS operator can obtain information from the fibre channel network about the fibre channel storage data zones available to the physical fibre channel adapter port and can specify that one or more zones can be accessed by a specific processor or group of processors. The processor or group of processors is given an adapter queue to access the zone or zones of storage data. This queue is given a new World Wide Port Name or new N-Port ID Virtualization identifier, to differentiate this queue from another queue that might have access to a different storage data zone or zones. For a partitioned server, one partition owns the adapter, controls the adapter queues, and updates the queue table(s).

Abstract: A network arbitration scheme is disclosed that manages device access fairness by selectively and dynamically increasing a requestor queue's likelihood of being serviced. A requestor queue increases its service priority by duplicating a request entry onto a set of priority rings maintained by arbitration hardware in a host bus adapter. Duplication occurs when (1) a requestor's queue fill count (the number of descriptors stored in the queue) exceeds a watermark level or (2) a requestor's queue timer times out. In the case of time-out, the requester in the lower priority ring will duplicate itself in the higher priority ring. Because the arbitration hardware services requesters using a round robin selection scheme, the likelihood of a requestor queue being serviced increases as the number of its duplicate request entries on a priority ring increases. Upon being serviced, the requester is able to perform the requested action.

Abstract: A system for processing multiple potentially related requests is provided. The system includes a pending request queue, a related request queue, an in-process queue, and an adapter. The pending request queue receives requests from at least one application. The in-process queue receives a first request from the pending request queue when no other requests are present in the in-process queue related to the first request. The related request queue receives the first request from the pending request queue when other requests are present in the in-process queue related to the first request. The adapter monitors the pending request queue, related request queue, and in-process queue. The adapter also communicates information related to the requests from the pending request queue to the related request and in-process queues as appropriate. The adapter also communicates information related to the requests from the in-process queue to a processor for processing the requests.

Abstract: A system includes an integrated encoder comprising an optical storage controller for coupling to an optical storage medium, and a data encoder for coding input data coupled to the optical storage controller, a first external memory coupled to a first memory controller in the integrated encoder, and a second external memory coupled to a second memory controller in the integrated encoder. In one aspect, the integrated encoder further comprises a first memory arbiter for selectively directing access to the first external memory by the optical storage controller and the data encoder, and a second memory arbiter for selectively directing access to the second external memory by the optical storage controller and the data encoder.

Abstract: A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

Abstract: Media drive control system and method. The media drive control system comprises a player console, a user operation filter, and a plurality of playback management devices. The player console provides an instant user operation (UOP) according to a received user command. The user operation filter comprises a queue and a management device. The queue receives and stores a plurality of UOPs, and outputs stored UOPs as control instructions on a first-in-first-out basis. The management device determines whether the queue is full. If the queue is full, the management device discards at least one of the stored UOPs prior to storing the instant UOP in the queue. Each playback management device receives control instructions for controlling corresponding playback devices.

Abstract: A method, system, and computer-usable medium for coupling a collection of devices to a bridge, wherein the collection of devices includes high-performance devices and low-performance devices, coupling a data bus to the bridge, utilizing a collection of transfer credits to allow transfer of commands to the collection of devices, transferring commands to the collection of devices only when at least one transfer credit is available, and in response to determining a number of transfer credits falls below a predetermined threshold, utilizing a command arbitration scheme that gives priority to commands to the high-performance devices among the collection of devices.

Abstract: A system for scheduling proportional sharing of storage shares includes one or more hosts which are IO attached to storage system including a storage coordinator, a buffer, and one or more storage devices which are provided as one or more storage shares. A storage share scheduler of the storage coordinator propagates an IO request to the one or more storage devices when a ranking value tagged to the IO request is higher than and/or equal to that of other IO requests. The storage share scheduler stores an IO request in the buffer when the ranking value of the IO request is lower than that of at least one other IO request. The storage share scheduler schedules the IO request stored in the buffer to be propagated when the ranking value is higher than and/or equal to the ranking value of the other IO requests.

Abstract: A method of ordering a job queue includes providing a marking system that includes a first marking engine and a storage device storing first and second print jobs in queue. The first marking engine includes first and second metrics. The method includes determining a present state value of the first and second metrics for the first marking engine, and estimating an incremental depletion value of the first and second metrics of the first and second print jobs. The method further includes comparing the incremental depletion value of the first and second metrics, respectively, with the present state value of the first and second metrics for the first marking engine. The method also includes ordering the first and second print jobs in the storage device based at least partially on the comparison. A system is also discussed.

Abstract: A technique includes identifying an address of a head end of a queue and monitoring a coherent interconnect to identify a data transfer that is communicated by a producer, which targets the address. The technique includes storing the data of the data transfer in the queue and selectively storing at least a portion of the data in a head-of-queue cache memory based at least in part on whether the monitoring identifies the address. At least a portion of the data is selectively retrieved from the head-of-queue cache memory instead of from the queue for transmission to a consumer.

Abstract: A data storage system is provided with command queue controller circuitry for positionally pushing pending access commands from a command queue to a selected target zone of a storage space. A method is provided for dividing a storage space into a plurality of LBA zones, selecting a target zone in relation to a number of pending access commands for each of the plurality of LBA zones, and pushing access commands to the target zone.

Abstract: Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests.

Abstract: A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decoding unit decodes the transaction clump tag to recover temporal information regarding the transaction to avoid violations of the ordering rules.

Abstract: Embodiments of the present invention provide for an IOC that does not limit each CPU to a particular port. Instead, the IOC may allow each CPU to communicate with all ports. Thus, the IOC can process CPU communications to determine which port to send them to, and send them to the correct port as well as process incoming communications from the ports to determine which CPU to send them to and send these communications to the correct CPU. This may significantly increase the flexibility and efficiency of a storage network.

Abstract: A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.

Abstract: Presented herein are system(s) and apparatus for a memory access unit for accessing data for a module. The memory access unit comprises an output port for providing access requests for lists of addresses in a memory over a link to a memory controller.

Abstract: Method for managing a queue in host memory for use with a peripheral device. Roughly described, the host makes a determination of the availability of space in the queue for writing new entries, in dependence upon historical knowledge of the number of queue entries that the host has authorized the device to write, and the number of entries that the host has consumed. In dependence on that determination, the host authorizes the device to write a limited number of new entries into the queue. The device writes entries into the queue dependence upon the number authorized. The host maintains a read pointer into the queue but does not need to maintain a write pointer, and the peripheral device maintains a write pointer into the queue but does not need to maintain a read pointer.

Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.

Abstract: Operations in a multi-processor, multi-control block environment are timed using timing queues and instruction queues. Upon receipt of a request for a subchannel control block (SCB) to perform an operation that needs to be timed, the SCB is queued on one of multiple timing queues based on an elapsed timeout limit (ETL) of the operation. There is an ETL for each operation, and each one the multiple timing queues is associated with an ETL for completing an operation. The SCB may be placed at the bottom of the timing queue, the timing queue ordered from oldest to youngest which allows for quickly checking large numbers of SCBs without having to check every element queue and without having to dequeuing the elements from this queue. Upon receipt of a request to perform a high-priority operation, the SCB may be queued in a high priority instruction queue. The SCB may remain the timing queue to retain its order and be placed on a high priority instruction queue for retrying an operation.

Abstract: Provided are a method, system, and article of manufacture for using priority to determine whether to queue an Input/Output (I/O) request directed to storage. A maximum number of concurrent requests directed to a storage is measured. The measured maximum number of concurrent requests is used to determine a threshold for a specified priority. Subsequent requests of the specified priority directed to the storage are allowed to proceed in response to determining that a current number of concurrent requests for the specified priority does not exceed the determined threshold for the specified priority. Subsequent requests directed to the storage having a priority greater than the specified priority are allowed to proceed. Subsequent requests directed to the storage having the specified priority are queued in a queue in response to determining that the current number of concurrent requests for the specified priority exceeds the overall threshold.

Abstract: System and method of a pace engine for governing the different transmission rates tailored for different connections by rate pacing a plurality of queues are described. Roughly described, the pace engine includes a binning controller for receiving queues from a transmit DMA queue manager and determines the earliest allowed time for a particular queue that is stored and paced in a Work Bin, a Fast Bin, or a Slow Bin. A pace table stores information about the minimum inter-packet-gap for each connection that is coupled to the transmit DMA queue manager. A timer is coupled to the binning controller with a multi-bit continuous counter that increments at a predetermined time unit and wraps around after a predetermined amount of time.

Abstract: Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and submitting the DMA request to an arbitration module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from plural buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.

Abstract: A system, apparatus and method for managing input/output requests in a multi-processor system is disclosed. An IO coherence unit includes an IO request handler, a variable size transaction table, and an IO response handler. The size of the transaction table varies according to the number of pending IO requests. The IO request handler stores information about pending IO requests in the transaction table to establish an order among related requests and to permit out-of-order handling of unrelated requests. The IO response handler tracks responses to the IO requests and updates the information in the transaction table. The IO coherence unit returns responses to requesting devices in compliance with device ordering requirements.

Abstract: An apparatus, system, and method are disclosed for enqueue prioritization. The apparatus for enqueue prioritization is provided with a plurality of modules configured to functionally execute the steps of holding one or more queued requests in a queue, sorting the queued requests according to a first priority identifier associated with each of the queued requests, and assigning a second priority identifier to a delayed request in response to a determination that the delayed request has resided in the queue for a predetermined length of time, wherein the second priority identifier indicates a higher priority than the first priority identifier indicates. These modules in the described embodiments include a queue module, a sorting module, and a reassignment module.

Abstract: An apparatus, system, and method are disclosed for enqueue prioritization. The apparatus for enqueue prioritization is provided with a plurality of modules configured to functionally execute the necessary steps of anticipating a need to access a computing resource, generating a dummy request, the dummy request configured to hold a place for an actual request in a queue of requests to access the computing resource, and generating an actual request to access the computing resource, wherein the actual request is configured to replace the dummy request in the queue. These modules in the described embodiments include a forecast module, a dummy generator, and a request generator.

Abstract: There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.

Abstract: Intelligent NIC optimizations includes system and methods for Token Table Posting, use of a Master Completion Queue, Notification Request Area (NRA) associated with completion queues, preferably in the Network Interface Card (NIC) for providing notification of request completions, and what we call Lazy Memory Deregistration which allows non-critical memory deregistration processing to occur during non-busy times. These intelligent NIC optimizations which can be applied outside the scope of VIA (e.g. iWARP and the like), but also support VIA.

Abstract: A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is used to store load data returned by a memory unit in response to a request issued by a processing module, such as a stream processing unit, in a processing core. As requests are issued, a destination queue buffer ID tag is transmitted as part of the request. When the request is returned, that destination number is reflected back and is used to control which queue within the circular queue will be used to store the retuned load data. Separate pointers are used to indicate the order of the queues to be read and the order of the queues to be written. The method and apparatus implemented by the present invention allows out-of-order data to be processed efficiently, thereby improving the performance of a fine grain multithreaded, multi-core processor.

Abstract: Various systems and methods for maintaining write order fidelity in a distributed environment are disclosed. One method, which can be performed by each node in a cluster, involves associating a current sequence number with each of several write operations included in a set of independent write operations. In response to detecting that one of the write operations in the set is ready to complete, a new sequence number is selected, and that new sequence number is thereafter used as the current sequence number. None of write operations in the set is allowed to return to the application that initiated the write operations until the new sequence number has been advertised to each other node in the cluster. The method also involves receiving a message advertising a first sequence number from another node in the cluster, and subsequently using the first sequence number as the current sequence number.

Abstract: Provided are methods, apparatus arid computer programs for scheduling storage input and/or output (I/O) requests. A method for scheduling storage access requests determines a request processing sequence calculated to maximize SLA-based revenues achievable from processing a number of requests. A storage controller includes a scheduler which implements a revenue-based scheduling function to determine a revenue-maximizing processing sequence, and then assigns storage access requests to locations in a queue corresponding to the determined sequence. In an on-line mode, the scheduler can adapt to additional received requests, evaluating the revenue function for the additional requests and modifying the schedule if required. The method may include analyzing a request stream to predict requests that are likely to be received in the near future, and taking account of the predicted requests when determining a processing schedule.

Abstract: This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.

Abstract: Circuitry and methods enable masters without split capability to communicate with split capable slaves in a multilayer system. The output stage associated with each split capable slave, which usually comprises an arbiter, is augmented with a split filter. This split filter designates a channel on behalf of the master without split capability, filters the split and unsplit responses from the slave, and issues a second read request on behalf of the same master. Consequently, both the master without split capability and the split capable slave do not perceive any difference between this transaction and a normal one. The split filter implementation requires, at most, little change to the master and slave devices of the system.

Abstract: In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an input/output memory management unit (IOMMU) coupled to the memory. The IOMMU is configured to implement address translation and memory protection for memory operations sourced by one or more input/output (I/O) devices. The memory stores a command queue during use. The memory management module is configured to write one or more control commands to the command queue, and the IOMMU is configured to read the control commands from the command queue and execute the control commands.

Abstract: A method for controlling access by processes running on a host device to a communication network includes assigning to each of the processes a respective doorbell address on a network interface adapter that couples the host device to the network and allocating instances of a communication service on the network, to be provided via the adapter, to the processes. Upon receiving a request submitted by a given one of the processes to its respective doorbell address to access one of the allocated service instances, the adapter conveys the data over the network using the specified instance of the service, subject to verifying, based on the doorbell address to which the request was submitted, that the specified instance was allocated to the given process.

Abstract: The management apparatus of web servers of the present invention monitors occurrence of link breakage set by requesting to other sites. For this purpose, log information resulting from an access from an external web site to HTTP contents is acquired from the web server. Then, refer information is generated by extracting the linking relationship with the external web site to the web page from the thus acquired log information. Furthermore, upon update of the HTTP contents, the possibility of occurrence of link breakage caused by page deletion is recognized with reference to refer information, and warning is issued.

Abstract: A disk control device stores write requests from a cache memory or reads commands from a host in a queue for a disk drive in chronological order. When the number of write requests stored in the queue for the disk drive is greater than a predetermined value, the storage location of write requests is changed to a queue for an extra disk drive, and the write requests are stored in the queue for the extra disk drive. When the number of write requests stored in the queue for the disk drive becomes smaller than a predetermined threshold, the write requests stored in the extra disk drive are written back to the disk drive.

Abstract: A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A driver for a data storage device includes an access command and a verification command. The access command initiates an access (write, erase or read) of the data storage device while allowing a calling application to continue running without having to wait for the completion of the access. The verification command queries a preceding access. If the query indicates failure of the preceding access, the verification command repeats the preceding access until the preceding access succeeds. The verification command is called by the access command before the access command initiates a new access. The verification command also is called by an application following a sequence of related access command calls. A write access command saves the data to be written in a memory separate from the data storage device, in case the verification command needs that data to repeat a failed write.

Abstract: Multiple disk access commands such as XOR commands are broken down into their constituent read and write parts and, if in LBA sequence, coalesced into pipes. These XOR read and write commands are then provided to the RPO algorithm of the HDD for scheduling along with data reads and writes. The actual XOR buffer operation is also scheduled by the RPO algorithm, advantageously to occur during a seek for another read or write.

Abstract: An apparatus, system, and method are disclosed for regulating the number of write requests in a fixed-size cache that facilitates differentiated treatment of write requests based on an assigned pacing value. The apparatus includes an examination module to examine a pending write request issued by an application. A priority module determines a priority for the write request based on an operating system defined input/output priority value. An assessment module assesses a storage demand level for storing write requests in a fixed-size cache. An assignment module assigns a pacing value to the write request based on the priority and in response to the storage demand level. A permission module permits the application to issue a subsequent write request once the pacing value of the write request is satisfied. The pacing value is satisfied by waiting until the amount of time specified by the pacing value expires.

Abstract: In a first aspect, a first method of reissuing a command involving bus access is provided. The first method includes the steps of (1) storing information associated with commands that are to be reissued, wherein the commands are each associated with respective input/output (I/O) devices seeking bus access; (2) storing a count for each of the commands, each count indicating a number of times the associated command has been reissued; (3) selecting a command to be reissued, from among the commands, based on the information associated with the command; and (4) determining a delay after which the selected command will be reissued, wherein the delay is determined based on the count associated with the selected command. Numerous other aspects are provided.

Abstract: A mechanism is presented for processing conditional payment requests in an electronic financial transaction system. In particular, the mechanism provides for the handling of concurrent conditional payment events. The status of a payment condition may be categorized into three categories, and a priority assigned relative to the category. In this way, concurrent events may be prioritized according to their respective categories. Events may then be executed in order of assigned priority.