Alternately Filling Or Emptying Buffers Patents (Class 710/53)
  • Patent number: 10318463
    Abstract: An interface controller coupling the main body of an external electronic device to a host, and the electronic device using the interface controller and a control method for the external electronic controller are disclosed. The interface controller has a control unit and a non-volatile memory. The control unit is configured to transmit a termination-on signal to the host when link information retrieved from the main body has been written into the non-volatile memory. When the host issues a link information request in response to the termination-on signal, the control unit uses the link information stored in the non-volatile memory to respond to the link information request.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: June 11, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Chia-Ying Kuo, Yi-Lin Lai
  • Patent number: 10298661
    Abstract: A method, hardware system, and/or computer program product controls message delivery from a publisher application to one or more subscriber applications in a publish/subscribe messaging mechanism. The one or more subscriber applications have a plurality of subscriptions registered with a broker application of the publish/subscribe messaging mechanism. A unified subscription description representing the plurality of subscriptions registered with the broker application is generated, and is then communicated to the publisher application.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Dominic P. Harries, Samuel D. Hughes
  • Patent number: 10262128
    Abstract: Various devices, methods, systems, and computer readable storage are provided for tokenizing data. In some examples, credit card numbers are tokenized using a pre-generated token map and absent the use of a networked database that stores a relatively large quantity of credit card numbers in a central location. The token map may be generated by a token map generator such that the token map can be used by a tokenizer to replace a portion of an account number with a token, and by a detokenizer to replace the token with the original portion of the account number. A pre-parser and parser may also be used to locate an account number and/or token in a message received over a network.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 16, 2019
    Assignee: Sabre GLBL Inc.
    Inventors: Kevin B. Bomar, Glenn E. Harper
  • Patent number: 10191871
    Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Simon Cottam, Patrice Woodward
  • Patent number: 10127112
    Abstract: A method begins by determining to rebuild one or more encoded data slices to a dispersed storage network (DSN) memory unit. The method continues by determining a rebuild rate of the DSN memory unit. The method continues by determining, based on the rebuild rate, a rebuild rate status of the DSN memory unit. The method continues by when the rebuild rate status is a high rebuild rate status, reducing the rebuild rate to the DSN memory unit. The method continues by rebuilding, when the rebuild rate is not zero, the one or more encoded data slices in the DSN memory unit.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Jason K. Resch, Ethan S. Wozniak
  • Patent number: 10110650
    Abstract: Client side stream switching enables substantially uninterrupted transmission of a highest compatible bit rate of a stream of media to a client via a network connection. The client may include one or more buffers for receiving the stream of media. Attributes including the buffer activity and a bandwidth of the network connection may be monitored by a streaming module to determine an alternative bit rate of the stream of media. The stream of media may be transitioned from the first bit rate to the alternative bit rate without an interruption of the stream of media to provide the client with the highest compatible bit rate based on the monitored attributes.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: October 23, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Samuel S. Gigliotti
  • Patent number: 10102458
    Abstract: An image processing apparatus for storing, in an intermediate data memory, intermediate data generated from print data, and processing the intermediate data is provided. The image processing apparatus has a configuration in which, in a case where it is determined that a size of a work memory exceeds a block size after processing for creating a first bit map is started, and where the processing for creating the first bit map is switched to processing for creating a second bit map, when the processing for creating the first bit map is started, processing for creating a bit map is started without delay by using a bit map memory in advance from the work memory.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: October 16, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takashi Ono
  • Patent number: 10031809
    Abstract: A method begins by a dispersed storage (DS) processing module identifying an encoded slice requiring rebuilding. The method continues by the DS processing module determining whether the encoded data slice is part of a fan-out encoded data slice group and, when it is part of a fan-out encoded data slice group determining by the DS processing module whether a valid encoded data slice of the fan-out data slice group is available. When a copy of the encoded data slice of the fan-out encoded data slice group is not available, the method continues by the DS processing module rebuilding the encoded data slice. A storage unit then stores the rebuilt encoded data slice and creates copies of the rebuilt encoded data slice to produce a rebuilt fan-out encoded data slice group.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Asimuddin Kazi
  • Patent number: 9900497
    Abstract: A system and method for recording video that combines video capture, touch-screen and voice-control technologies into an integrated system that produces cleanly edited, short-duration, compliant video files that exactly capture a moment after it has actually occurred The present invention maintains the device in a ready state that is always ready to capture video up to N seconds or minutes in the past (where N depends on available system memory). This enables the user to run the system indefinitely without having to worry about running out of storage. Touch gestures and voice commands actually initiate captures without having to actually monitor the system itself thereby allowing for complete focus on the live action itself. When the user sees something happen, he or she can use an appropriate voice or touch command to cause the system to create a video media file based on time points derived from the user's commands.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Fast Model Holdings LLC
    Inventors: Albert Tsai, David Yip
  • Patent number: 9832135
    Abstract: An apparatus for managing data queues is disclosed. The apparatus includes at least one sensor for collecting data, a data interface for receiving data from the sensor(s) and for placing the collected data in a set of data queues, and a priority sieve for organizing the set of data queues according to data priority of a specific task. The priority sieve includes a scoreboard for identifying queue priority and a system timer for synchronization.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: November 28, 2017
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Jeffrey E. Robertson, Dale A. Rickard
  • Patent number: 9811455
    Abstract: A system is provided that includes a remote device and bus controller coupled to the remote device via a digital network bus. The remote device includes one or more data channels for respective one or more peripherals, and includes volatile channel-based memory for each data channel and non-volatile device-based memory for the remote device. The bus controller is and configured to send a command across the network bus to the remote device, and in response thereto, the remote device is configured to acquire data from a designated data channel or command the designated data channel to perform a conversion. The command is from a communication protocol with which the remote device is compatible, and includes a set of channel commands for accessing the channel-based memory, and a different, distinct set of device-memory commands for accessing the device-based memory. The channel commands and device-memory commands have different timing requirements.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 7, 2017
    Assignee: THE BOEING COMPANY
    Inventors: Philip J. Ellerbrock, Robert N. Zettwoch
  • Patent number: 9665586
    Abstract: A first entry is received at an event log interface. The event log interface is configured to store received entries in an event log. It is determined that there is not enough storage space to store the first entry in the event log. A second entry is identified. The second entry is the oldest entry in the event log based on when the second entry was written to the event log. It is determined that the second entry contains an indicator to preserve. A copy of the second entry is sent to the event log interface to be written to the event log. One or more entries are deleted from the event log. The one or more entries includes the second entry. The first entry is written to the event log. The copy of the second entry is written to the event log.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventor: Calvin D. Ward
  • Patent number: 9542101
    Abstract: A data storage system and methods for managing data to be transferred between a host and a data volume distributed across solid state storage modules are disclosed. A storage controller couples the host to the data volume and manages data transfers to and from the logical volume. The storage controller receives a set of parameters that define how an array of blocks and chunks of buffered data will be distributed across solid state storage modules. The storage controller receives and buffers data to be stored and transfers the same when the capacity of the buffered data will fill a set of arranged stripes in the defined array in a single write operation.
    Type: Grant
    Filed: September 22, 2013
    Date of Patent: January 10, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Horia Simionescu, Anant Baderdinni, Luca Bert
  • Patent number: 9491505
    Abstract: This disclosure describes techniques to improve a user experience in a Wireless Display (WD) system. The WD system includes a source device that provides media data to one or more sink devices. The techniques are directed toward reducing end-to-end latency in the WD system while improving video playback quality at the sink devices. More specifically, the techniques include low latency screen capture and buffering at the source device. For example, a processing pipeline of the source device may be configured to include minimum-size buffers between processing steps to reduce latency. The techniques include buffering a most recent frame update captured from the media data in the minimum-size buffers and dropping older frame updates when the minimum-size buffers are full. In addition, the processing pipeline may be configured to use hardware acceleration to retrieve the frame updates from the buffers for processing.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 8, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaodong Wang, Fawad Shaukat, Vijayalakshmi R. Raveendran
  • Patent number: 9454333
    Abstract: Embodiments of the invention provide parity logs for raid systems with variable-capacity media. In one embodiment, a system includes a first set of data storage media devices having variable capacity. The storage devices include a data portion of a parity data set for storing write data being striped to the first. The system further includes a second set of data storage media devices having variable capacity. The second set includes a linear address space of blocks for storing a parity portion of the parity data set. The linear address space is written in a log form. The first and second sets comprise at least one array in a RAID configuration. The system writes the parity portion of the parity data set to the second set, which enables each storage device among the first set to be written to full capacity.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: September 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Veera W. Deenadhayalan, Steven R. Hetzler, Wayne C. Hineman, Robert M. Rees, Pin Zhou
  • Patent number: 9430596
    Abstract: A system and method of parallel processing includes a computer system including a first processor, the first processor being a control flow type processor, a second processor, the second processor being a data flow type processor. The second processor is coupled to a second memory system, the second memory system including instructions stored therein in an order of execution and corresponding events data stored therein in the order of execution. A first one of the instructions are stored at a predefined location in the second memory system. The system also includes a run time events insertion and control unit coupled to the first processor and the second processor. The first processor, the second processor and the run time events insertion and control unit are on a common integrated circuit.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: August 30, 2016
    Assignee: Montana Systems Inc.
    Inventor: Asghar Bashteen
  • Patent number: 9386058
    Abstract: A client device presents streaming media and includes a stream manager, a request accelerator, and a source component coupled to the stream manager and the request accelerator for determining which requests to make. A rate selection process can make rate decisions so that the buffer is filled when it is low, avoiding erratically changing rates and can choose the correct steady rate quickly. Multimedia download strategies can be used for HTTP that allow for accurate rate estimations, achieving link capacity even if network delays and packet loss rates are high, achieving timely delivery of the stream, and achieving relatively steady download rates with little short term variability. A receiver might use multiple HTTP connections, decompose media requests into smaller chunk requests, synchronize the connections using TCP flow control mechanisms, and request data in bursts. In addition, the receiver might use an HTTP pipelining process to keep the connections busy.
    Type: Grant
    Filed: January 20, 2013
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Qiang Gao, Michael George Luby, Yinian Mao, Lorenz Christoph Minder, Kevin Roland Fall
  • Patent number: 9367492
    Abstract: A storage virtualization apparatus includes: a first storing unit to store, with respect to each storage port, a process incomplete command count defined as number of commands not yet processed by the storage device having each storage port; a control unit to obtain process incomplete command counts accumulated by other storage virtualization apparatuses, and stores into a second storing unit a process incomplete command total count that is a total of the process incomplete command counts obtained from the other storage virtualization apparatuses and the first storing unit; and an access request responding unit to, when receiving an access request, obtain the process incomplete command total count about a storage port corresponding to the received access request, and to, when the obtained process incomplete command total count is larger than a prescribed number, cause completion timing of an access responding process to the access request to be delayed.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: June 14, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Shiomi
  • Patent number: 9363302
    Abstract: An implementation, as described herein, facilitates fast start-up of a new media stream while avoiding temporal interruption (i.e., “hiccups”) of the presentation of that new media stream. At least one implementation, described herein, coordinates the delivery of multiple simultaneous media streams on a media-stream network. Its coordination accounts for traversal of bandwidth-restricted chokepoints; quickly stopping delivery of one or more media streams from the set of streams; quickly initiating delivery and presentation of one or more new media streams not previously in the set (i.e., a “channel chlangee”): and producing clean playback of all of the streams in the set, despite their different timelines. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: June 7, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Dustin L. Green
  • Patent number: 9342384
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Brian T. Lewis, Rajkishore Barik, Tatiana Shpeisman
  • Patent number: 9336293
    Abstract: Provided are a data management apparatus and a data management method for a surveillance system. The data management apparatus includes: a first storage unit configured to store therein data provided from a data input unit; a second storage unit configured to store therein a copy of the data; and a control unit configured to control the first storage unit to store the data therein on a real time basis, and if the data stored in the first storage unit is equal to or larger than a predetermined threshold amount, generate the copy and control the second storage unit to store the copy in the second storage unit as much as a given amount.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: May 10, 2016
    Assignee: Hanwha Techwin Co., Ltd.
    Inventor: Ji-Yeon Ha
  • Patent number: 9183077
    Abstract: A data storage apparatus includes: a memory configured to store data; an input delay circuit configured to input a set of data of a plurality of bits into the memory at different timings between the plurality of bits by adding different delays to the plurality of bits in the set of data or by adding different delays to bits in bit groups obtained by grouping the plurality of bits in units of a consecutive bits; and an output delay circuit configured to obtain an original set of data, which is the set of data before the input delay circuit adds the different delays, by adding, to the plurality of bits in the set of data output from the memory, delays having a pattern opposite that of the delays added by the input delay circuit.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Katsuya Tsushita
  • Patent number: 9170928
    Abstract: Write operations are scheduled for multiple nodes in a shared storage cluster that supports volume replication. Requests are received from nodes for allocation of space for write operations in a replication log. In response to a received request, the current capacity of the requesting node to manage a backlog can be determined. The amount of space in the replication log allocated to the node is then calibrated to the node's capacity, thereby preventing self-throttling. A separate priority can be assigned to each volume, and space in the replication log assigned to each volume based on its priority. Nodes can target synchronous and other latency sensitive operations to higher priority volumes. A single global queue can be maintained to schedule write operations for all nodes, thereby providing a fair scheduling. A separate local queue can be maintained for each node, thereby providing specific levels of preference to specific nodes.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 27, 2015
    Assignee: Symantec Corporation
    Inventors: Suhas Dantkale, Satyendra Thakur, Kirubakaran Kaliannan, Prasad Vadlamannati
  • Patent number: 9118586
    Abstract: A method and system for routing frames based on a port's speed using a switch element. The method includes receiving a portion of a frame in a receive buffer of a port; determining a frame length threshold value; and setting up a status bit based on the port's speed, the frame length threshold value and an amount of the frame received. The status bit is sent to a transmit segment of the switch element and the frame length threshold value is proportional to the port's speed. Also, if the receive buffer is almost full when the frame arrives at the receive port, then a cut status is based on the frame's end of frame (“EOF”) value.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: August 25, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss
  • Patent number: 9043514
    Abstract: A transfer control circuit stores data in a FIFO memory, outputs data in the FIFO memory in response to a data request signal, and outputs a state signal in accordance with an amount of stored data in the FIFO memory. An output data generating unit outputs image data having a horizontal image size in accordance with a horizontal count value and a horizontal synchronizing signal, and thereafter, outputs blank data. When the state signal indicates that the FIFO memory is in a “EMPTY” or “MODERATE” storage state, a blank control unit outputs a blank addition signal until the FIFO memory changes to a “FULL” storage state.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 26, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yuji Yoshida
  • Patent number: 9037704
    Abstract: A monitoring server receives the latest monitored data and corresponding monitoring time from monitoring devices connected to the server at a specified time interval. The monitoring server records monitored data of each monitoring item and the corresponding monitoring time to a pointed node of a device data list, and adds the monitored data and the corresponding monitoring time, which are recorded in the pointed node of the device data list, into a monitored data list. When a web server requests real-time monitored data, corresponding monitored data is read from the device data list and sent to the web server. When the web server requests historical monitored data of an designated period, corresponding monitored data of the designated period is read from the monitored data list and sent to the web server.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: May 19, 2015
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chung-I Lee, Yi-Guo Wang, Kuan-Chiao Peng, Jian Huang, Yi-Ming Lu
  • Patent number: 9032114
    Abstract: The invention relates to an access controller which comprises a module (24) for managing writing in a circular buffer (16), means (38) for storing a first read pointer (PL) and a second write pointer (PE), a module (30) for managing reading in the circular buffer (16), means (24, 30, 40) for blocking reading, respectively writing, means (38) for storing a read or write work pointer (PT) which is different from the first and second pointers (PL; PE), and means (24, 30, 40) for updating the wo: pointer (PT) according to a predetermined update logic. The predetermined update logic comprises forward or backward movements of the work pointer (PT) inside the circular buffer (16), and the controller includes means for blocking the read or write work pointer if the read work pointer (PT) points outside a memory space reserved for reading or, respectively, if the write work pointer (PT) points outside a free memory space for writing.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: May 12, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Yves Durand, Christian Bernard
  • Patent number: 9026695
    Abstract: An asymmetrical processing multi-core system used in a network device is provided. A sub processing core within the asymmetrical processing multi-core system facilitates a main processing core of the asymmetrical processing multi-core system in processing tasks, thereby improving an overall performance of the entire network device and causing the network device to operate more facilely. Different from a conventional processing method, the asymmetrical processing multi-core system does not require moving or copying a large amount of processed packet data, and thus a large amount of memory bandwidth is saved and the power consumption is reduced.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Gemtek Technology Co., Ltd.
    Inventor: Pei-Lin Wu
  • Patent number: 9026697
    Abstract: A data processing apparatus may include a data acquisition unit, a buffer unit that includes a plurality of division buffers, a valid data area determination unit that calculates an area of valid data, a buffer state management unit that manages whether or not the data is stored in the division buffer, a data write control unit that writes data of a unit of the storage capacity of the division buffer, which at least includes data indicated to be valid data by the valid data information within the data, to the division buffer in which no data is stored, the division buffer being selected based on the management information, and a data read control unit that reads data indicated to be valid data by the valid data information from the division buffer in which data is stored, the division buffer being selected based on the management information.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: May 5, 2015
    Assignee: Olympus Corporation
    Inventors: Tomonori Yonemoto, Hideru Ikeda, Keisuke Nakazono
  • Patent number: 9015375
    Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 21, 2015
    Assignee: SIGMATEL, Inc.
    Inventors: Roderick Holley, II, Raymond L. Vargas, John Gregory Ferrara
  • Patent number: 9015378
    Abstract: Methods and systems for acquiring and batching sensor data using a mobile device are described. In one example, a system in a mobile device is provided. The system includes one or more sensors, a memory, a sensor processor, and a main application processor. The sensor processor is configured to determine sensor data using the one or more sensors on an interval basis and store the sensor data into one or more first-in, first-out (FIFO) queues. Additionally, the sensor processor is configured to replace at least a portion of the stored sensor data if a main application processor of the mobile device does not request the stored sensor data within a certain amount of time. The main application processor is configured to receive data indicating a request for sensor data for a recent time period and, in response, to retrieve the sensor data from the one or more FIFO queues.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 21, 2015
    Assignee: Google Inc.
    Inventors: Etienne Le Grand, Mathias Agopian
  • Publication number: 20150067200
    Abstract: Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on (i) partial match results determined from walking segments of a payload of a flow through a first finite automation and (ii) a historical search context associated with the flow. The search context may be modified via push or pop operations to direct at least one processor to walk segments of the payload through the at least one second finite automation. The search context may be maintained in a manner that obviates overflow of the search context and obviating stalling of the push or pop operations to increase match performance.
    Type: Application
    Filed: April 14, 2014
    Publication date: March 5, 2015
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Yossef Shanava, Timothy Toshio Nakada, Abhishek Dikshit
  • Patent number: 8972629
    Abstract: A method for queuing thread update buffers to enhance garbage collection. The method includes providing a global update buffer queue and a global array with slots for storing pointers to filled update buffers. The method includes with an application thread writing to the update buffer and, when filled, attempting to write the pointer for the update buffer to the global array. The array slot may be selected randomly or by use of a hash function. When the writing fails due to a non-null slot, the method includes operating the application thread to add the filled update buffer to the global update buffer queue. The method includes, with a garbage collector thread, inspecting the global array for non-null entries and, upon locating a pointer, claiming the filled update buffer. The method includes using the garbage collector thread to claim and process buffers added to the global update buffer queue.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: March 3, 2015
    Assignee: Oracle America, Inc.
    Inventors: Antonios Printezis, Paul H. Hohensee
  • Patent number: 8949491
    Abstract: Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Gary Lin, Robert Jackson, Yoav Weinberg, William L. Guthrie, Girish B. Desai
  • Publication number: 20150019767
    Abstract: A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 15, 2015
    Inventor: Bok Rim KO
  • Publication number: 20150019766
    Abstract: This disclosure provides examples of circuits, devices, systems, and methods for managing a buffer memory. Regions of the buffer memory are dynamically reserved, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Gary Lin, Robert Jackson, Yoav Weinberg, William L. Guthrie, Girish B. Desai
  • Patent number: 8934502
    Abstract: A method and system for processing buffer status reports (BSRs) such that when BSR triggering is performed, the size(s) of the necessary sub-header(s) are also to be considered together in addition to the BSR size. The steps of checking whether any padding region is available in a MAC PDU that was constructed, comparing the number of padding bits with the size of the BSR plus its sub-header, and if the number of padding bits is larger than the size of the BSR plus its sub-header, triggering BSR are performed. Doing so allows the sub-header(s) to be inserted or included into the MAC PDU or transport block (TB) or other type of data unit.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: January 13, 2015
    Assignee: LG Electronics Inc.
    Inventors: Sung Duck Chun, Seung June Yi, Sung Jun Park, Young Dae Lee
  • Publication number: 20150006769
    Abstract: Under control of the consumer, it is determined that a first buffer is empty and that a second buffer contains data; a first compare-double-and-swap operation within a spin loop is executed to swap a double pointer of the first buffer and a double pointer of the second buffer, wherein responsive to the executing of the operation the consumer drains the second buffer, and wherein the executing of the operation directs the at least one producer to fill the first buffer; and it is determined that the first buffer and the second buffer are empty and the consumer waits for a notification from one of i) the at least one producer and ii) a timer. Under control of the at least one producer, a second compare-double-and-swap operation within a spin loop is executed to atomically locate the first buffer and update the double pointer of the first buffer.
    Type: Application
    Filed: September 18, 2014
    Publication date: January 1, 2015
    Inventor: Vitali Mints
  • Patent number: 8918561
    Abstract: A computer implemented method, data processing system, and apparatus for hardware resource arbitration in a data processing environment having a plurality of logical partitions. A hypervisor receives a request for a hardware resource from a first logical partition, wherein the request corresponds to an operation. The hypervisor determines the hardware resource is free from contention by a second logical partition. The hypervisor writes the hardware resource to a hardware resource pool data structure, as associated with the first logical partition, in response to a determination the hardware resource is free. The hypervisor presents the hardware resource to the first logical partition. The hypervisor determines that the operation is complete. The hypervisor release the hardware resource from a hardware resource pool, responsive to the determination that the operation is complete.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yogesh L Hegde, Vijayaprasanna Laxmikanthappa, Jorge R Nogueras
  • Publication number: 20140359175
    Abstract: For re-timing sampled data, input data samples at an input data rate are stored in a FIFO buffer and output at an output data rate according to an output clock that is locked to the input data rate in dependence on a loop-filtered measure of the fill level of the said buffer. The frequency of the output clock is additionally controlled by an estimate of the input data rate.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 4, 2014
    Inventor: Jeff Butters
  • Patent number: 8904067
    Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Microsoft Corporation
    Inventor: Erwien Saputra
  • Patent number: 8880761
    Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: November 4, 2014
    Assignee: BlackBerry Limited
    Inventors: Scott Edward Bulgin, Cyril Martin, Bengt Stefan Gustavsson
  • Patent number: 8874810
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a plurality of storage nodes and a master controller. The storage nodes store information. The storage node includes an upstream communication buffer which is locally controlled at the storage node to facilitate resolution of conflicts in upstream communications. The master controller controlls the flow of traffic to the node based upon constraints of the upstream communication buffer. In one embodiment, communication between the master controller and the node has a determined maximum latency. The storage node can be coupled to the master controller in accordance with a chain memory configuration.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: October 28, 2014
    Assignee: Spansion LLC
    Inventors: Roger Dwain Isaac, Seiji Miura
  • Patent number: 8874809
    Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: October 28, 2014
    Assignee: Napatech A/S
    Inventor: Peter Korger
  • Patent number: 8874860
    Abstract: A method for logical buffer pool extension identifies a page in a memory for eviction, and analyzes characteristics of the page to form a differentiated page. The characteristics of the page include descriptors that include a workload type, a page weight, a page type, frequency of access and timing of most recent access. The method also identifies a target location for the differentiated page from a set of locations including a fastcache storage and a hard disk storage to form an identified target location. The method further selects an eviction operation from a set of eviction operations using the characteristics of the differentiated page and the identified target location. The differentiated page is written to the identified target location using the selected eviction operation, where the differentiated page is written only to the fastcache storage.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew A. Huras, Aamer Sachedina
  • Patent number: 8874808
    Abstract: The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device with a memory core, a high speed upstream data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer spanning a plurality of asynchronous timing domains that delivers the data onto the upstream data bus to minimize gaps in a data transfer. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a high speed data bus with pre-determined timing in a manner which minimizes latency to the extent that the returning read data beats are always transmitted contiguously with no intervening gaps.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Hnatko, Gary A. Van Huben
  • Patent number: 8862795
    Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes first and second memory banks. A first waveform is stored in chunks alternating between successive buffers in the first and second memory banks, and concurrently, the first and second chunks may be transferred to first and second FIFOs, respectively, which may be accumulated with respective first and second chunks of a second waveform into the first and second memory banks. This process may be repeated for respective successive pairs of the first and second waveforms, where the first and second memory banks and FIFOs are used in an alternating manner, and further, to accumulate additional waveforms, where previously stored (and accumulated) waveform data are accumulated chunkwise with successive additional waveform data, and where at least some of the accumulation is performed concurrently with waveform data transfers to and from the memory banks and FIFOs.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 14, 2014
    Assignee: National Instruments Corporation
    Inventor: Rafael Castro Scorsi
  • Patent number: 8856407
    Abstract: Methods and systems for conducting a transaction between a USB device and a virtual USB device driver are provided. A client USB manager stores in a buffer one or more data packets associated with the virtual USB device driver. The client USB manager dequeues one of the one or more data packets from the buffer. The client USB manager transmits the dequeued data packet to the USB device for processing. The client USB manager re-fills completed data packets from the buffer and queues the data packets for transmitting to the USB device without waiting for the virtual USB device driver.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: October 7, 2014
    Assignee: Red Hat, Inc.
    Inventor: Hans de Goede
  • Patent number: 8850090
    Abstract: Methods and systems for conducting a transaction between a virtual USB device driver and a USB device are provided. A virtual USB manager of a hypervisor receives a one or more data packets from a client. The virtual USB manager stores of the one or more data packets in a buffer. The virtual USB manager dequeues a data packet from the buffer. The virtual USB manager transmits the data packet to the virtual USB device driver for processing.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: September 30, 2014
    Assignee: Red Hat, Inc.
    Inventor: Hans de Goede
  • Publication number: 20140281060
    Abstract: A method for queuing thread update buffers to enhance garbage collection. The method includes providing a global update buffer queue and a global array with slots for storing pointers to filled update buffers. The method includes with an application thread writing to the update buffer and, when filled, attempting to write the pointer for the update buffer to the global array. The array slot may be selected randomly or by use of a hash function. When the writing fails due to a non-null slot, the method includes operating the application thread to add the filled update buffer to the global update buffer queue. The method includes, with a garbage collector thread, inspecting the global array for non-null entries and, upon locating a pointer, claiming the filled update buffer. The method includes using the garbage collector thread to claim and process buffers added to the global update buffer queue.
    Type: Application
    Filed: May 29, 2014
    Publication date: September 18, 2014
    Applicant: Oracle America
    Inventors: ANTONIOS PRINTEZIS, PAUL H. HOHENSEE