Abstract: A semiconductor integrated circuit includes a register, a first interface circuit, an oscillation circuit that generates a first clock, a pll circuit, a control circuit, and a second interface circuit. The register stores numerical information representing a data size. The first interface circuit receives, from a first device, a first timing signal for data transfer. Responding to receipt of the first timing signal, the control circuit inputs the first timing signal to the pll circuit and counts the number of toggles of the first timing signal. When a counted number of toggles of the first timing signal matches a value corresponding to the numerical information, the control circuit inputs the first clock to the pll circuit. The second interface circuit transmits, to a second device, the first timing signal or a second timing signal, which corresponds to a second clock generated based on the first clock by the pll circuit.

Abstract: The concepts and technologies disclosed herein are directed to zero day attack detection. A system can monitor, by a sequence manager, a sequence of transaction requests. The sequence manager can determine whether a transaction request in the sequence is anomalous. In response to determining that the transaction request is anomalous, and before the allowing the system to process the transaction request, the sequence manager can provide the sequence of transaction requests to a sequence emulator. The sequence emulator can attempt to verify an output of the sequence of transaction requests. The sequence manager can receive a notification from the sequence emulator. The notification can indicate whether the output of the sequence of transaction requests can be verified. In response, the sequence manager can instruct the system to deny (if the output cannot be verified) or allow (if the output can be verified) processing of the sequence of transaction requests.

Abstract: Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.

Abstract: A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.

Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.

Abstract: A method for transmitting a data packet based on a virtual machine is provided. A direct through-connection is established between the virtual machine and a network interface card. A data packet transmitted by a driver layer of the virtual machine is detected. An encapsulation parameter obtaining request is transmitted to a virtual machine monitor corresponding to the virtual machine, and encapsulation information and an encapsulation parameter are received in response to the encapsulation parameter obtaining request. The data packet is encapsulated according to the encapsulation information and the encapsulation parameter, and the encapsulated data packet is added to a hardware transmitting queue of the network interface card by using the direct through-connection to transmit the encapsulated data packet.

Abstract: Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.

Abstract: One or more blocks of dynamic random access memory are embedded together with a processor and a data bus on an integrated circuit. The data bus has a bandwidth b for general operation including memory access, the block of dynamic random access memory further requiring data refresh at a refresh rate r. The block thus forms an eDRAM on the integrated circuit, typically an ASIC. A refresh controller embedded with the eDRAM may control refresh by clocking the data bus at a rate higher than the rate of the data bus to accommodate both the required memory access and the required data refresh.

Abstract: A system and method for handling file system quotas are disclosed. In one implementation, a processing device receives a first command to disable a quota capability of a file system. In response, one or more instructions are initiated to delete a first association of a quota attribute with a directory, where the first association assigns a first value to a first string comprising a combination (e.g., concatenation, etc.) of an attribute name and a first symbol. Prior to completion of the execution of the one or more instructions, one or more commands are received to enable the quota capability and assign a second value of the quota attribute to the directory. In response, a second association of the quota attribute with the directory is generated, the second association assigning a second value of the quota attribute to a second string comprising a combination of the attribute name and a second symbol.

Abstract: A smart interface circuit includes: a first protocol processing circuit receiving several first protocol commands including a first command and a second command from a first device, storing the commands in an instruction register that is accessible to a second protocol processing circuit, and outputting first data and second data stored in a data buffer to the first device according to the first command and the second command respectively; and the second protocol processing circuit generating X second protocol command(s) according to the first command to request a second device to output the first data to the data buffer, and before the first protocol processing circuit finishes outputting the first data to the first device, the second protocol processing circuit generating Y second protocol command(s) according to the second command to request the second device to output the second data to the data buffer.

Abstract: A computer system architecture including a first buffer, a second buffer, a sub-system and a CPU is provided. The sub-system carries out a first task to obtain first returned information, stores the first returned information in the first buffer and sets up a first occupancy flag to the first buffer. Next, the sub-system carries out a second task to obtain second returned information, stores the second returned information in the second buffer, and sets up a second occupancy flag to the second buffer. The CPU reads the first returned information and eliminates the first occupancy flag. After the second returned information is stored in the second buffer and the first occupancy flag is eliminated, the sub-system continuously carries out a third task to obtain third returned information, stores the third returned information in the first buffer, and sets up the first occupancy flag to the first buffer.

Abstract: An apparatus comprises control circuitry to control access to a memory implemented using a memory technology providing variable access latency. The control circuitry has request handling circuitry to identify an execution context switch comprising a transition from servicing memory access requests associated with a first execution context to servicing memory access requests associated with a second execution context. At least when the execution context switch meets a predetermined condition, a delay masking action is triggered to control subsequent memory access requests associated with the second execution context, for which the required data is already stored in the memory, to be serviced with a response delay which is independent of which addresses were accessed by the memory access requests associated with the first execution context. This can help guard against attacks which aim to exploit variation in response latency to gain insight into the addresses accessed by a victim execution context.

Abstract: A method for a dispersed storage network (DSN) begins by determining an I/O (input/output) capacity of a storage level of DSN memory. The method continues by determining a required performance level to meet operational demands of services operating at the storage level. The method continues by setting a storage level throttle rate based on the I/O capacity and the required performance level and determining a remaining I/O performance of the DSN memory to be allocated to a higher storage level.

Abstract: In an example, a computing system is configured to detect data to temporarily store in a group of buffers using an in-memory buffer service; correlate, to the detected data, one or more identifiers of a plurality of identifiers based on a characteristic of the detected data, wherein a first identifier of the plurality corresponds to a first buffer type and a second different identifier of the plurality corresponds to a second buffer type; in response to the data correlated to a single identifier of the identifiers, create a first data object and place the first data object in one of the buffers of the corresponding buffer type; and in response to the data correlated to more than one of the identifiers, create a second data object for each one of the identifiers and place the second data objects in ones of the buffers of the corresponding buffer types, respectively.

Abstract: A method and system for improving audio and video multimedia modification and presentation is provided. The method includes receiving an audio/video stream and analyzing objects of the audio/video stream for generating predictions with respect to the objects. Component analysis code is executed with respect to the audio/video stream and an object is removed from the audio/video stream resulting in a modified audio/video stream being generated thereby reducing hardware storage and transfer size requirements of the audio/video stream. The modified audio/video stream is presented to a user via a graphical user interface.

Abstract: A method and apparatus are provided. The apparatus comprises an input for receiving a plurality of data streams carrying misaligned common content. The apparatus further comprises a plurality of buffers configured to delay one or more of the data streams to align the common content, each buffer for storing data blocks of a respective one of the plurality of data streams. The apparatus comprises an output for selecting a data block from the plurality of buffers to form a next data block in an output packet stream comprising the common content. Each data block is stored in a respective buffer along with quality information corresponding to said data block and selecting a data block from the plurality of buffers is carried out in dependence on the quality information.

Abstract: Encoding a file into a plurality of chunks, wherein a subset of the plurality of chunks may be used to create a functional equivalent of the file. At least one additional chunk is created from the plurality of chunks. The at least one additional chunk is directed to be stored in a cache memory and the plurality of chunks are directed to be stored on at least one storage node. Upon demand for the file, at least one additional chunk is cased to be retrieved from the cache and at least a portion of the plurality of chunks are caused to be retrieved from the at least one storage node and the functional equivalent of the file is constructed through utilization of the at least one additional chunk and the portion of the plurality of chunks.

Abstract: A direct memory access (DMA) engine may be responsible to enable and control DMA data flow within a computing system. The DMA engine moves blocks of data, associated with descriptors in a plurality of queues, from a source to a destination memory location or address, autonomously from control by a computer system's processor. Based on analysis of the data blocks linked to the descriptors in the queues, the DMA engine and its associated DMA fragmenter ensure that data blocks stored linked to descriptors in the queues do not remain idle for an exorbitant period of time. The DMA fragmenter may divide large data blocks into smaller data blocks to ensure that the processing of large data blocks does not preclude the timely processing of smaller data blocks associated with one or more descriptors in the queues. The data blocks stored may be two-dimensional data blocks.

Abstract: An interface controller coupling the main body of an external electronic device to a host, and the electronic device using the interface controller and a control method for the external electronic controller are disclosed. The interface controller has a control unit and a non-volatile memory. The control unit is configured to transmit a termination-on signal to the host when link information retrieved from the main body has been written into the non-volatile memory. When the host issues a link information request in response to the termination-on signal, the control unit uses the link information stored in the non-volatile memory to respond to the link information request.

Abstract: A method, hardware system, and/or computer program product controls message delivery from a publisher application to one or more subscriber applications in a publish/subscribe messaging mechanism. The one or more subscriber applications have a plurality of subscriptions registered with a broker application of the publish/subscribe messaging mechanism. A unified subscription description representing the plurality of subscriptions registered with the broker application is generated, and is then communicated to the publisher application.

Abstract: Various devices, methods, systems, and computer readable storage are provided for tokenizing data. In some examples, credit card numbers are tokenized using a pre-generated token map and absent the use of a networked database that stores a relatively large quantity of credit card numbers in a central location. The token map may be generated by a token map generator such that the token map can be used by a tokenizer to replace a portion of an account number with a token, and by a detokenizer to replace the token with the original portion of the account number. A pre-parser and parser may also be used to locate an account number and/or token in a message received over a network.

Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.

Abstract: A method begins by determining to rebuild one or more encoded data slices to a dispersed storage network (DSN) memory unit. The method continues by determining a rebuild rate of the DSN memory unit. The method continues by determining, based on the rebuild rate, a rebuild rate status of the DSN memory unit. The method continues by when the rebuild rate status is a high rebuild rate status, reducing the rebuild rate to the DSN memory unit. The method continues by rebuilding, when the rebuild rate is not zero, the one or more encoded data slices in the DSN memory unit.

Abstract: Client side stream switching enables substantially uninterrupted transmission of a highest compatible bit rate of a stream of media to a client via a network connection. The client may include one or more buffers for receiving the stream of media. Attributes including the buffer activity and a bandwidth of the network connection may be monitored by a streaming module to determine an alternative bit rate of the stream of media. The stream of media may be transitioned from the first bit rate to the alternative bit rate without an interruption of the stream of media to provide the client with the highest compatible bit rate based on the monitored attributes.

Abstract: An image processing apparatus for storing, in an intermediate data memory, intermediate data generated from print data, and processing the intermediate data is provided. The image processing apparatus has a configuration in which, in a case where it is determined that a size of a work memory exceeds a block size after processing for creating a first bit map is started, and where the processing for creating the first bit map is switched to processing for creating a second bit map, when the processing for creating the first bit map is started, processing for creating a bit map is started without delay by using a bit map memory in advance from the work memory.

Abstract: A method begins by a dispersed storage (DS) processing module identifying an encoded slice requiring rebuilding. The method continues by the DS processing module determining whether the encoded data slice is part of a fan-out encoded data slice group and, when it is part of a fan-out encoded data slice group determining by the DS processing module whether a valid encoded data slice of the fan-out data slice group is available. When a copy of the encoded data slice of the fan-out encoded data slice group is not available, the method continues by the DS processing module rebuilding the encoded data slice. A storage unit then stores the rebuilt encoded data slice and creates copies of the rebuilt encoded data slice to produce a rebuilt fan-out encoded data slice group.

Abstract: A system and method for recording video that combines video capture, touch-screen and voice-control technologies into an integrated system that produces cleanly edited, short-duration, compliant video files that exactly capture a moment after it has actually occurred The present invention maintains the device in a ready state that is always ready to capture video up to N seconds or minutes in the past (where N depends on available system memory). This enables the user to run the system indefinitely without having to worry about running out of storage. Touch gestures and voice commands actually initiate captures without having to actually monitor the system itself thereby allowing for complete focus on the live action itself. When the user sees something happen, he or she can use an appropriate voice or touch command to cause the system to create a video media file based on time points derived from the user's commands.

Abstract: An apparatus for managing data queues is disclosed. The apparatus includes at least one sensor for collecting data, a data interface for receiving data from the sensor(s) and for placing the collected data in a set of data queues, and a priority sieve for organizing the set of data queues according to data priority of a specific task. The priority sieve includes a scoreboard for identifying queue priority and a system timer for synchronization.

Abstract: A system is provided that includes a remote device and bus controller coupled to the remote device via a digital network bus. The remote device includes one or more data channels for respective one or more peripherals, and includes volatile channel-based memory for each data channel and non-volatile device-based memory for the remote device. The bus controller is and configured to send a command across the network bus to the remote device, and in response thereto, the remote device is configured to acquire data from a designated data channel or command the designated data channel to perform a conversion. The command is from a communication protocol with which the remote device is compatible, and includes a set of channel commands for accessing the channel-based memory, and a different, distinct set of device-memory commands for accessing the device-based memory. The channel commands and device-memory commands have different timing requirements.

Abstract: A first entry is received at an event log interface. The event log interface is configured to store received entries in an event log. It is determined that there is not enough storage space to store the first entry in the event log. A second entry is identified. The second entry is the oldest entry in the event log based on when the second entry was written to the event log. It is determined that the second entry contains an indicator to preserve. A copy of the second entry is sent to the event log interface to be written to the event log. One or more entries are deleted from the event log. The one or more entries includes the second entry. The first entry is written to the event log. The copy of the second entry is written to the event log.

Abstract: A data storage system and methods for managing data to be transferred between a host and a data volume distributed across solid state storage modules are disclosed. A storage controller couples the host to the data volume and manages data transfers to and from the logical volume. The storage controller receives a set of parameters that define how an array of blocks and chunks of buffered data will be distributed across solid state storage modules. The storage controller receives and buffers data to be stored and transfers the same when the capacity of the buffered data will fill a set of arranged stripes in the defined array in a single write operation.

Abstract: This disclosure describes techniques to improve a user experience in a Wireless Display (WD) system. The WD system includes a source device that provides media data to one or more sink devices. The techniques are directed toward reducing end-to-end latency in the WD system while improving video playback quality at the sink devices. More specifically, the techniques include low latency screen capture and buffering at the source device. For example, a processing pipeline of the source device may be configured to include minimum-size buffers between processing steps to reduce latency. The techniques include buffering a most recent frame update captured from the media data in the minimum-size buffers and dropping older frame updates when the minimum-size buffers are full. In addition, the processing pipeline may be configured to use hardware acceleration to retrieve the frame updates from the buffers for processing.

Abstract: Embodiments of the invention provide parity logs for raid systems with variable-capacity media. In one embodiment, a system includes a first set of data storage media devices having variable capacity. The storage devices include a data portion of a parity data set for storing write data being striped to the first. The system further includes a second set of data storage media devices having variable capacity. The second set includes a linear address space of blocks for storing a parity portion of the parity data set. The linear address space is written in a log form. The first and second sets comprise at least one array in a RAID configuration. The system writes the parity portion of the parity data set to the second set, which enables each storage device among the first set to be written to full capacity.

Abstract: A system and method of parallel processing includes a computer system including a first processor, the first processor being a control flow type processor, a second processor, the second processor being a data flow type processor. The second processor is coupled to a second memory system, the second memory system including instructions stored therein in an order of execution and corresponding events data stored therein in the order of execution. A first one of the instructions are stored at a predefined location in the second memory system. The system also includes a run time events insertion and control unit coupled to the first processor and the second processor. The first processor, the second processor and the run time events insertion and control unit are on a common integrated circuit.

Abstract: A client device presents streaming media and includes a stream manager, a request accelerator, and a source component coupled to the stream manager and the request accelerator for determining which requests to make. A rate selection process can make rate decisions so that the buffer is filled when it is low, avoiding erratically changing rates and can choose the correct steady rate quickly. Multimedia download strategies can be used for HTTP that allow for accurate rate estimations, achieving link capacity even if network delays and packet loss rates are high, achieving timely delivery of the stream, and achieving relatively steady download rates with little short term variability. A receiver might use multiple HTTP connections, decompose media requests into smaller chunk requests, synchronize the connections using TCP flow control mechanisms, and request data in bursts. In addition, the receiver might use an HTTP pipelining process to keep the connections busy.

Abstract: A storage virtualization apparatus includes: a first storing unit to store, with respect to each storage port, a process incomplete command count defined as number of commands not yet processed by the storage device having each storage port; a control unit to obtain process incomplete command counts accumulated by other storage virtualization apparatuses, and stores into a second storing unit a process incomplete command total count that is a total of the process incomplete command counts obtained from the other storage virtualization apparatuses and the first storing unit; and an access request responding unit to, when receiving an access request, obtain the process incomplete command total count about a storage port corresponding to the received access request, and to, when the obtained process incomplete command total count is larger than a prescribed number, cause completion timing of an access responding process to the access request to be delayed.

Abstract: An implementation, as described herein, facilitates fast start-up of a new media stream while avoiding temporal interruption (i.e., “hiccups”) of the presentation of that new media stream. At least one implementation, described herein, coordinates the delivery of multiple simultaneous media streams on a media-stream network. Its coordination accounts for traversal of bandwidth-restricted chokepoints; quickly stopping delivery of one or more media streams from the set of streams; quickly initiating delivery and presentation of one or more new media streams not previously in the set (i.e., a “channel chlangee”): and producing clean playback of all of the streams in the set, despite their different timelines. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

Abstract: Provided are a data management apparatus and a data management method for a surveillance system. The data management apparatus includes: a first storage unit configured to store therein data provided from a data input unit; a second storage unit configured to store therein a copy of the data; and a control unit configured to control the first storage unit to store the data therein on a real time basis, and if the data stored in the first storage unit is equal to or larger than a predetermined threshold amount, generate the copy and control the second storage unit to store the copy in the second storage unit as much as a given amount.

Abstract: A data storage apparatus includes: a memory configured to store data; an input delay circuit configured to input a set of data of a plurality of bits into the memory at different timings between the plurality of bits by adding different delays to the plurality of bits in the set of data or by adding different delays to bits in bit groups obtained by grouping the plurality of bits in units of a consecutive bits; and an output delay circuit configured to obtain an original set of data, which is the set of data before the input delay circuit adds the different delays, by adding, to the plurality of bits in the set of data output from the memory, delays having a pattern opposite that of the delays added by the input delay circuit.

Abstract: Write operations are scheduled for multiple nodes in a shared storage cluster that supports volume replication. Requests are received from nodes for allocation of space for write operations in a replication log. In response to a received request, the current capacity of the requesting node to manage a backlog can be determined. The amount of space in the replication log allocated to the node is then calibrated to the node's capacity, thereby preventing self-throttling. A separate priority can be assigned to each volume, and space in the replication log assigned to each volume based on its priority. Nodes can target synchronous and other latency sensitive operations to higher priority volumes. A single global queue can be maintained to schedule write operations for all nodes, thereby providing a fair scheduling. A separate local queue can be maintained for each node, thereby providing specific levels of preference to specific nodes.

Abstract: A method and system for routing frames based on a port's speed using a switch element. The method includes receiving a portion of a frame in a receive buffer of a port; determining a frame length threshold value; and setting up a status bit based on the port's speed, the frame length threshold value and an amount of the frame received. The status bit is sent to a transmit segment of the switch element and the frame length threshold value is proportional to the port's speed. Also, if the receive buffer is almost full when the frame arrives at the receive port, then a cut status is based on the frame's end of frame (“EOF”) value.

Abstract: A transfer control circuit stores data in a FIFO memory, outputs data in the FIFO memory in response to a data request signal, and outputs a state signal in accordance with an amount of stored data in the FIFO memory. An output data generating unit outputs image data having a horizontal image size in accordance with a horizontal count value and a horizontal synchronizing signal, and thereafter, outputs blank data. When the state signal indicates that the FIFO memory is in a “EMPTY” or “MODERATE” storage state, a blank control unit outputs a blank addition signal until the FIFO memory changes to a “FULL” storage state.

Abstract: A monitoring server receives the latest monitored data and corresponding monitoring time from monitoring devices connected to the server at a specified time interval. The monitoring server records monitored data of each monitoring item and the corresponding monitoring time to a pointed node of a device data list, and adds the monitored data and the corresponding monitoring time, which are recorded in the pointed node of the device data list, into a monitored data list. When a web server requests real-time monitored data, corresponding monitored data is read from the device data list and sent to the web server. When the web server requests historical monitored data of an designated period, corresponding monitored data of the designated period is read from the monitored data list and sent to the web server.

Abstract: The invention relates to an access controller which comprises a module (24) for managing writing in a circular buffer (16), means (38) for storing a first read pointer (PL) and a second write pointer (PE), a module (30) for managing reading in the circular buffer (16), means (24, 30, 40) for blocking reading, respectively writing, means (38) for storing a read or write work pointer (PT) which is different from the first and second pointers (PL; PE), and means (24, 30, 40) for updating the wo: pointer (PT) according to a predetermined update logic. The predetermined update logic comprises forward or backward movements of the work pointer (PT) inside the circular buffer (16), and the controller includes means for blocking the read or write work pointer if the read work pointer (PT) points outside a memory space reserved for reading or, respectively, if the write work pointer (PT) points outside a free memory space for writing.

Abstract: An asymmetrical processing multi-core system used in a network device is provided. A sub processing core within the asymmetrical processing multi-core system facilitates a main processing core of the asymmetrical processing multi-core system in processing tasks, thereby improving an overall performance of the entire network device and causing the network device to operate more facilely. Different from a conventional processing method, the asymmetrical processing multi-core system does not require moving or copying a large amount of processed packet data, and thus a large amount of memory bandwidth is saved and the power consumption is reduced.

Abstract: A data processing apparatus may include a data acquisition unit, a buffer unit that includes a plurality of division buffers, a valid data area determination unit that calculates an area of valid data, a buffer state management unit that manages whether or not the data is stored in the division buffer, a data write control unit that writes data of a unit of the storage capacity of the division buffer, which at least includes data indicated to be valid data by the valid data information within the data, to the division buffer in which no data is stored, the division buffer being selected based on the management information, and a data read control unit that reads data indicated to be valid data by the valid data information from the division buffer in which data is stored, the division buffer being selected based on the management information.

Abstract: Methods and systems for acquiring and batching sensor data using a mobile device are described. In one example, a system in a mobile device is provided. The system includes one or more sensors, a memory, a sensor processor, and a main application processor. The sensor processor is configured to determine sensor data using the one or more sensors on an interval basis and store the sensor data into one or more first-in, first-out (FIFO) queues. Additionally, the sensor processor is configured to replace at least a portion of the stored sensor data if a main application processor of the mobile device does not request the stored sensor data within a certain amount of time. The main application processor is configured to receive data indicating a request for sensor data for a recent time period and, in response, to retrieve the sensor data from the one or more FIFO queues.

Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.

Abstract: Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on (i) partial match results determined from walking segments of a payload of a flow through a first finite automation and (ii) a historical search context associated with the flow. The search context may be modified via push or pop operations to direct at least one processor to walk segments of the payload through the at least one second finite automation. The search context may be maintained in a manner that obviates overflow of the search context and obviating stalling of the push or pop operations to increase match performance.