Abstract: A bit stream processing device may include a virtual division memory, a stream shift buffer, a decoder circuit, and a controller. The virtual division memory may be divided into a plurality of group memory regions configured to store a plurality of stream groups in the respective group memory regions and to output a memory bit stream. The stream groups may be included in an input bit stream. The stream shift buffer is configured to receive and store the memory bit stream and output a buffer bit stream. The decoder circuit is configured to perform a decoding operation on the buffer bit stream from the stream shift buffer. The controller is configured to control operations of the virtual division memory, the stream shift buffer, and the decoder circuit.

Abstract: In one embodiment, a network device is disclosed. For example, in one embodiment of the present invention, the device comprises a processor and a core memory having a receive buffer and a transmit buffer. The device comprises a bus coupled to the processor and the core memory. The device comprises at least one co-processor coupled to the core memory via a direct link, wherein the at least one co-processor is capable of accessing at least one of: the receive buffer, or the transmit buffer, without assistance from the processor.

Abstract: The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device comprising: a memory core, a shared data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer that delivers the data onto the shared data bus with pre-determined timing. The present invention can also be viewed as providing methods for controlling moving data entries in a hierarchical buffer system. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a shared data bus with pre-determined timing.

Abstract: A communication control device includes reception controllers capable of receiving data in a burst transfer mode in which packets are continuously transferred as one burst. There are dedicated buffers having a capacity of one packet for each of a plurality of endpoints and common buffers shared by the endpoints; a first packet of a burst transfer is stored in the dedicated buffer; and a common buffer is secured at the same time. The dedicated buffers and common buffers are controlled according to a transfer status.

Abstract: Various embodiments of the present invention are related to memory buffers, and in particular to a multi-write bit-fill FIFO to which multiple addresses may be written simultaneously and which fills in bit spaces as data blocks are written.

Abstract: A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).

Abstract: A method of transmitting data is described comprising selecting a transmission mode from at least a first and a second transmission mode, wherein according to the first transmission mode data is transmitted in at least two first time periods using first communication resources wherein the at least two first time periods are separated by a first time interval, wherein according to the second transmission mode data is transmitted in at least two second time periods using second communication resources wherein the at least two second time periods are separated by a second time interval, and wherein the first time interval is longer than the second and the first communication resources allow the transmission of a higher amount of data than the second communication resources; and transmitting data according to the selected transmission mode.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A data communication control device. The data communication control device includes, a controller comprising a first data storing part, the first data storing part including multiple channels, each channel being applied to store a command for data transfer based on a destination of data, the controller executing the command stored in the channel from the head to transfer data and, an overall controller storing the command in the channel of the first data storing part when the number of commands in a certain channel is not over a upper limit, and stopping to store the command in the channel of the first data storing part and creating a second data storing part and storing the command in the second data storing part when the number of commands in a certain channel is over the upper limit.

Abstract: Methods for controlling read data buffering are disclosed. In one of the methods core operations are performed in response to a receipt of a read command from a master controller and an internal or external communication buffer of a data storage node is selected to forward information to the master controller. The data storage node is selected based upon constraints and contents of one or more communication buffers. Information is forwarded from the selected internal or external communication buffer to the master controller.

Abstract: A data transfer unit includes: a collection-interval storage unit that storing therein a collection interval set by the host computer; a data collection unit reading a collection interval stored in the collection-interval storage unit and collecting device data at the read collection interval; a transfer-interval storage unit storing therein a transfer interval set by the host computer, which is equal to or larger than the collection interval; a ring buffer accumulating and storing therein device data that are collected by the data collection unit and have not been transferred to the host computer by a data transferring unit; and a data transferring unit reading a transfer interval stored in the transfer-interval storage unit, and collectively transfers device data accumulated and stored in the ring buffer to the host computer at the read transfer interval.

Abstract: Method and system for replicating a storage volume is provided. Information is adaptively replicated in a swap mode or a copy mode. When information is copied from a storage volume to a memory buffer, an application determines if another information transfer from the same source volume is pending. If a transfer from the same source is pending, then information is copied from the memory buffer to a stolen buffer in a copy mode. If a transfer from the same source is not pending, then instead of copying the information, the application enables a swap mode. During the swap mode, an operating system for a storage system swaps a pointer from the stolen buffer to information stored in the memory buffer. The memory buffer itself is invalidated so that no other module can access the memory buffer. Because the pointers are swapped, the application accesses information directly from the memory buffer.

Abstract: A data writing apparatus includes a tape drive, a buffer and non-volatile memory. When a synchronization request is received from a device sending data to be written to a tape, the apparatus is operable to copy data corresponding to the synchronization request from the buffer to the non-volatile memory. The data may be stored in the non-volatile memory until at least the time when the data which it is a copy of is written to the tape from the buffer.

Abstract: An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred. Many alternatives, variations, and modifications are possible.

Abstract: In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

Abstract: A predictive resampler scheduler algorithm may be provided. An audio frame may be received from a producer. The audio frame may be transmitted to a consumer and a delay between receiving the audio frame and transmitting the audio frame may be calculated. In response to determining that the delay comprises a value not within a threshold time range, the size of the audio frame may be modified prior to transmitting the frame to the consumer.

Abstract: Disclosed herein is a method of accessing a slave device from a circuit including a central processing unit, a data transfer engine, and an interface to the slave device. In one embodiment, the method includes: executing code on the central processing unit to set up the data transfer engine to access the slave device; and based on the set-up, operating the data transfer engine to supply a read request word to a transmit buffer of the interface for transmission to the slave device, and, after return of a corresponding response word to a first-in-first-out receive buffer of the interface, to disable the first-in-first-out receive buffer from receiving any further data such that the last word therein is assured to be the response word. The method further includes using an underflow mechanism of the first-in-first-out receive buffer to determine the last word therein and hence determine the response word.

Abstract: A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.

Abstract: Herein described are at least a system and a method for regulating data flow in a data pipeline that may be used in a video processing system. The system comprises a processor, one or more data buffers, and one or more processing stations. The one or more data buffers may be used to buffer corresponding processing stations. Each of the one or more processing stations may comprise a switching circuitry that is used to inhibit data transmission when a hold signal is received from the processor. The processor may send the signal in response to a feedback control signal generated by the one or more processing stations. The method may comprise determining if the processing time of a processing station exceeds a specified time. The method further comprises generating a feedback control signal to a processor if the specified time is exceeded.

Abstract: A communication processing device includes a communication data processing circuit that (i) issues an access request for a buffer specified by a descriptor, among a plurality of buffers in a first memory, and (ii) outputs a predetermined switching permission signal at a time when a data access for one of the plurality of buffers is completed. The communication processing device also includes a second memory and a transmission destination switching circuit. The second memory includes a plurality of alternative buffers corresponding to the plurality of buffers. The transmission destination switching circuit switches a transmission destination of the access request from one of the plurality of buffers in the first memory to one of the plurality of alternative buffers in the second memory, based on the switching permission signal.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: An image scanning device includes a scanning unit configured to execute image scanning of a document and thereby generate image data, at least one processing unit configured to successively process the image data outputted from the scanning unit, a transmission unit configured to transmit the image data outputted from the processing unit, a storage unit, in which multiple buffer areas to be used for transferring the image data among the scanning unit, the at least one processing unit and the transmission unit are allocated, an acquisition unit configured to acquire information on usage status of each of the buffer areas, and a changing unit configured to change storage area allocation at least between two of the buffer areas based on the usage status acquired by the acquisition unit.

Abstract: A data processing apparatus is provided comprising a buffer for buffering data contained in a data stream generated by a data stream generator and received by a data stream receptor. Buffer occupancy tracking circuitry is provided and configured to maintain a high buffer utilisation value providing an indication of a high buffer occupation level for a given time period during utilisation of the buffer. Alternatively, in an apparatus where the buffer is implemented in dedicated memory, the buffer occupancy tracking circuitry is configured to store a programmable buffer size limit controlling a maximum allowable buffer storage capacity.

Abstract: Embodiments of the present invention provide a buffer manager and a buffer management method based on an address pointer linked list. In the embodiments, address pointers of all buffer blocks in a buffer are divided into several groups, lower bits of address pointers in each group are used to record a linked list between the address pointers in the same group, and an address pointer which is pointed by one predetermined address pointer of each group and is in a different group is further recorded to upbuild a linked list between the groups. Thereby, an address linked list can still be stored without a RAM with a width equal to a pointer depth and with a depth equal to the total number of buffer blocks in the buffer as required by the conventional art, which greatly reduces hardware resources required.

Abstract: A method for sending buffer status information includes checking if a quality of service (QoS) parameter is defined for a first logical channel and at least one condition of the set of predetermined conditions associated with a logical channel group is fulfilled. If the QoS parameter is defined and at least one condition of the set is fulfilled, the method includes setting a number of bits in a media access control header according to a first semantic. The bits carry buffer status information, and the first semantic—is based on the QoS parameter of the first logical channel. Otherwise, the method includes setting the number of bits carrying the buffer status information according to a second semantic that is based on an amount of data available for transmission across the logical channel group.

Abstract: Disclosed is an electronic device featuring a multi buffer scheme for processing incoming signals. For example, two buffers can be used. A processor can read and process stored signals from a first buffer while an incoming data module can concurrently store signals in a second buffer. Once, the processor is done, it can move on to the second buffer and process signals stored therein while the incoming data module stores signals in the first buffer. Also provided is a flagging scheme for allowing the processor and the incoming data module to control their respective access to the various buffers, so that only one of them accesses a single buffer at any time.

Abstract: A computer implemented method, data processing system, and apparatus for hardware resource arbitration in a data processing environment having a plurality of logical partitions. A hypervisor receives a request for a hardware resource from a first logical partition, wherein the request corresponds to an operation. The hypervisor determines the hardware resource is free from contention by a second logical partition. The hypervisor writes the hardware resource to a hardware resource pool data structure, as associated with the first logical partition, in response to a determination the hardware resource is free. The hypervisor presents the hardware resource to the first logical partition. The hypervisor determines that the operation is complete. The hypervisor release the hardware resource from a hardware resource pool, responsive to the determination that the operation is complete.

Abstract: A method and system for processing buffer status reports (BSRs) such that when BSR triggering is performed, the size(s) of the necessary sub-header(s) are also to be considered together in addition to the BSR size. The steps of checking whether any padding region is available in a MAC PDU that was constructed, comparing the number of padding bits with the size of the BSR plus its sub-header, and if the number of padding bits is larger than the size of the BSR plus its sub-header, triggering BSR are performed. Doing so allows the sub-header(s) to be inserted or included into the MAC PDU or transport block (TB) or other type of data unit.

Abstract: Methods and systems for conducting a transaction between a USB device and a virtual USB device driver are provided. A client USB manager stores in a buffer one or more data packets associated with the virtual USB device driver. The client USB manager dequeues one of the one or more data packets from the buffer. The client USB manager transmits the dequeued data packet to the USB device for processing. The client USB manager re-fills completed data packets from the buffer and queues the data packets for transmitting to the USB device without waiting for the virtual USB device driver.

Abstract: First k log buffers, in a data storage application including a plurality of log buffers are each loaded with exactly one transaction. Each log buffer is written to one of a plurality of log partitions. Thereafter, each of the log buffers is sent to an input/output (I/O) subsystem when they are respectively loaded with a single transaction. Transactions are subsequently accumulated in respective new current log buffers after sending the k log buffers to the I/O subsystem. The accumulated transactions are sent to the I/O subsystem when the earlier occurs of (i) the respective current log buffer being full or (ii) a number of incomplete input/output requests handled by the I/O subsystem falls below k. Related apparatus, systems, techniques and articles are also described.

Abstract: A circuit including a first memory and a processor. The processor is configured to receive data from a host device and transfer the data from the circuit to a storage drive. The processor is configured to receive the data back from the storage drive when a second memory in the storage drive does not have available space for the data, and prior to the data being transferred from the second memory to a third memory in the storage drive. The processor is configured to: store the data received from the storage drive in the first memory or transfer the data received from the storage drive back to the host device; and based on a request received from the storage drive, transfer the data from the first memory or the host device back to the storage drive. The request indicates that space is available in the second memory for the data.

Abstract: Inter-processor communication (IPC) apparatus and a method for providing communication between two processors having a shared memory, the IPC apparatus including an arbitrated bus coupling the processors to one another and to the memory, a buffer in the shared memory associated with each processor, and at least one pair of First In First Out hardware units (FIFOs) coupled to each processor, the FIFOs holding pointers to addresses in the buffer associated with that processor, wherein a first of the pair of FIFOs (an empty buffer FIFO) is configured to hold pointers to empty portions of the buffer while the second of the pair of FIFOs (a message FIFO) is configured to hold pointers to portions of the buffer having data therein.

Abstract: A space switch includes a buffer having a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, a plurality n of buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-nth that of the input data and a switch fabric connected to the buffers for matching buffer data throughput with switch data throughput. Preferably the buffer is a bifurcate buffer. This space switch described ensures matching of buffer and switch fabric throughput.

Abstract: The invention provides a method for handling data read out from a memory. In one embodiment, a controller corresponding to the memory comprises a ping-pong buffer. First, a first sector read time period required by the memory to read and output a data sector to the ping-pong buffer is calculated. A second sector read time period required by a host to read a data sector from the ping-pong buffer is calculated. A page switch time period required by the memory to switch a target read page is obtained. A total sector number is determined according to the first sector read time period, the second sector read time period, and the page switch time period. When the memory outputs data to the ping-pong buffer, a first buffer and a second buffer of the ping-pong buffer are switched to receive the data output by the memory according to the total sector number.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.

Abstract: An approach for improving input/output control and efficiency in an encrypted file system (EFS) is provided. In this approach, a software application writes data to a first buffer and then requests that an encrypted file system save the data onto a nonvolatile storage device. The encrypted file system encrypts the data and stores the encrypted data in a second buffer and then writes the encrypted data from the second buffer to the nonvolatile storage area. Meanwhile, the software application is able to resume writing additional data to the buffer after the data has been copied to the second buffer even if the data has not yet been written to the nonvolatile storage area.

Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.

Abstract: An embodiment of a method for credit-based flow control is disclosed. For this embodiment of the method, a first transaction layer packet from a sending device is loaded into a receiver buffer of a receiving device. A second transaction layer packet is loaded into the receiver buffer, where the second transaction layer packet is of a different packet type than the first transaction layer packet. The first transaction layer packet is unloaded from the receiver buffer without return of a credit for the unloading of the first transaction layer packet from the receiver buffer. The first transaction layer packet is loaded into a side buffer, and the credit for the first transaction layer packet is sent to the sending device responsive to unloading or anticipated unloading of the first transaction layer packet from the side buffer.

Abstract: Provided is a serial control device that makes the length of data transferred as one frame variable. The serial control device transfers serial data having an arbitrary length, and uses end information indicating inclusion or non-inclusion of end data of the serial data. The serial control device transfers data having a transfer unit length in the serial data when the end information indicates non-inclusion of the end data, and transfers an untransferred part of the serial data when the end information indicates inclusion of the end data.

Abstract: A system selectively drops data from queues. The system includes a drop table that stores drop probabilities. The system selects one of the queues to examine and generates an index into the drop table to identify one of the drop probabilities for the examined queue. The system then determines whether to drop data from the examined queue based on the identified drop probability.

Abstract: A data-buffering apparatus (100) having two buffers (206,200) and configured to conserve power is disclosed. When a block of data (202) having a short block length (406?) is to be buffered, the block of data (202) is buffered by a small primary buffer (206) and a large secondary buffer (200) is deactivated. When a block of data (202) having a long block length (406?) is to be buffered, the large secondary buffer (200) is activated and the block of data (202) is buffered by both buffers (206,200). As there are typically many more blocks of data (202) having short block lengths (406?) than long block lengths (406?), the secondary buffer (200) is activated only a small fraction of the time.

Abstract: Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.

Abstract: In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

Abstract: Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive comprises a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further comprises a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.

Abstract: A method for buffering monitored data received from a monitoring device. The received monitored data is buffered into a buffer area and all of the monitored data from the buffer area is stored to a database server when a current count of data in the buffer area equals a recycling predetermined count N. An address of the received monitored data is recorded in a data list. When a monitoring server receives request for monitored data from a client server, the required one or more items of monitored data is read from the buffer area and sent to the client server.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: A method of buffered reading of data is provided. A read request for data is received by a buffered reader, and in response to the read request, a main memory input buffer is partially filled with the data by the buffered reader to a predetermined amount that is less than a fill capacity of the input buffer. Corresponding computer system and program products are also provided.