Abstract: A method of buffered reading of data is provided. A read request for data is received by a buffered reader, and in response to the read request, a main memory input buffer is partially filled with the data by the buffered reader to a predetermined amount that is less than a fill capacity of the input buffer. Corresponding computer system and program products are also provided.

Abstract: DMA transfer completion notification includes: inserting, by an origin DMA engine on an origin node in an injection first-in-first-out (‘FIFO’) buffer, a data descriptor for an application message to be transferred to a target node on behalf of an application on the origin node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying a packet header for a completion notification packet; transferring, by the origin DMA engine to the target node, the message in dependence upon the data descriptor; sending, by the origin DMA engine, the completion notification packet to a local reception FIFO buffer using a local memory FIFO transfer operation; and notifying, by the origin DMA engine, the application that transfer of the message is complete in response to receiving the completion notification packet in the local reception FIFO buffer.

Abstract: The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.

Abstract: A method for managing under-runs and a device having under-run management capabilities. The method includes retrieving packets from multiple buffers, monitoring a state of a multiple buffers, determining whether an under-run associated with a transmission attempt of a certain information frame from a certain buffer occurs; if an under-run occurs, requesting a certain information frame transmitter to transmit predefined packets while ignoring packets that are retrieved from the certain buffer, until a last packet of the information frame is retrieved from the certain buffer; and notifying a processor that an under-run occurred after at least one predefined packet was transmitted; wherein each buffer out of the multiple buffers is adapted to store a fraction of a maximal sized information frame.

Abstract: A resending control circuit for controlling resending of data to be sent to a sending destination, includes: a writing unit for writing resending information generated corresponding to each of data to be resent and including the resending point-in-time of the data in memory; a reading unit for reading out the resending information from the memory; and a control unit for comparing resending point-in-time included in the oldest resending information of resending information stored in the memory with current point-in-time, and executing resending processing of data corresponding to the resending information according to the comparison result.

Abstract: A system manages a buffer having a group of entries. The system receives information relating to a read request for a memory. The system determines whether an entry in the buffer contains valid information. If the entry is determined to contain valid information, the system transmits the information in the entry in an error message. The system may then store the received information in the entry. In another implementation, the system stores data in one of the entries of the buffer, removes an address corresponding to the one entry from an address list, and starts a timer associated with the one entry. The system also determines whether the timer has exceeded a predetermined value, transferring the data from the one entry when the timer has exceeded the predetermined value, and adds the address back to the address list.

Abstract: An apparatus such as a Device Wire Adapter (DWA) with improved buffer management and packaging of Wireless Universal Serial Bus (WUSB) isochronous packets for transmission to a host. The apparatus includes an isochronous IN endpoint that receives data segments from a device function. Memory is associated with the endpoint and includes an endpoint buffer configured in a loop and a plurality of registers. The apparatus includes an endpoint controller that stores the received data segments sequentially in the loop buffer, assigns a set of the registers to each of the stored data segments, and stores additional packet information in the registers for each of the data segments rather than in the endpoint buffer. The additional packet information includes presentation time for the stored data segment derived from a sample time of a last segment in the buffer and a time interval between two consecutive data segments in the buffer.

Abstract: A transaction stack for devices with a limited writing cycle memory slides in a transaction buffer. Following any Commit Transaction or, alternatively, any Begin Transaction, the transaction stack is reallocated inside the transaction buffer. Consequently, some memory locations in the transaction buffer are released. The writing accesses to the non-volatile area memory of the transaction buffer are not concentrated in the first address, as in a standard implementation of a transaction stack, but they are spread over the locations of the transaction buffer.

Abstract: An execution queue stores a write command from the host in response to issuance of the write command from the host, and is removed from the execution queue in response to a signal indicating that data designated by the write command has been written to the hard disk. A holding queue stores the write command removed from the execution queue. In response to the command being stored in the holding queue, a request is issued for an acknowledgment from the host. The write command is removed from the holding queue in response to the acknowledgment being received from the host. An outgoing queue stores the write command removed from the holding queue for deletion. The queues are controlled by queue management hardware, the request is issued by the queue management hardware, and the signal and acknowledgment are received by the queue management hardware.

Abstract: Management of requests from a host to an external storage medium. An execution queue stores commands to be executed, and each command corresponds to a request from the host for data. A holding queue stores executed commands until receipt of an acknowledgment from the host that the host has, e.g., received the data corresponding to the command from the external storage medium. An outgoing queue stores acknowledged commands and has a maximum storage limit. A counter is provided, and a separate logic block increments the counter when a command is stored in the execution queue and decrements the counter when an acknowledged command is deleted from the outgoing queue. The separate logic disables execution of commands stored in the execution queue when the value of the counter equals the maximum storage limit of the outgoing queue.

Abstract: Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the host when it has completed processing of data buffers. Each of the completion event descriptors notify the host of completion of data transfer between the NIC and one or more of the data buffers, and can also embed a queue empty notification inside the completion event.

Abstract: A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. The processing unit dispatches a first set of instructions in order from a first buffer for execution. The processing unit receives updated results from the execution of the first set of instructions. The processing unit updates, in a first register, at least one register entry associated with each instruction in the first set of instructions, with the updated results. The processing unit determines if the first set of instructions from the first buffer have completed execution. Responsive to the completed execution of the first set of instructions from the first buffer, the processing unit copies the set of entries from the first register to a second register.

Abstract: A bridge capable of preventing data inconsistency is provided, in which a first master device outputs a flush request, a buffering unit buffers data or instructions, and a flush request control circuit records a buffer write pointer of the buffer according to the flush request and outputs a flush acknowledgement signal to the first master device in response of that a buffer read pointer of the buffering unit is identical to the recorded buffer write pointer.

Abstract: A system and method for sharing peripheral first-in-first-out (FIFO) resources is disclosed. In one embodiment, a system for utilizing peripheral FIFO resources includes a processor, a first peripheral FIFO controller and a second peripheral FIFO controller coupled to the processor for controlling buffering of first data and second data associated with the processor respectively. Further, the system includes a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller for merging a first FIFO channel associated with the first peripheral FIFO controller and a second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel respectively. Also, the system includes a first FIFO and a second FIFO coupled to the merge module via the first FIFO channel and the second FIFO channel respectively.

Abstract: A processing of consistent data sets by asynchronous application of a subscriber in an isochronous, cyclical communication system is provided. Accordingly, by connecting a communication memory and a consistency, transmission and reception buffer, copying processes leading delay can be kept to a minimum.

Abstract: A dummy node is enqueued to a concurrent, non-blocking, lock-free FIFO queue only when necessary to prevent the queue from becoming empty. The dummy node is only enqueued during a dequeue operation and only when the queue contains a single user node during the dequeue operation. This reduces overhead relative to conventional mechanisms that always keep a dummy node in the queue. User nodes are enqueued directly to the queue and can be immediately dequeued on-demand by any thread. Preferably, the enqueueing and dequeueing operations include the use of load-linked/store conditional (LL/SC) synchronization primitives. This solves the ABA problem without requiring the use a unique number, such as a queue-specific number, and contrasts with conventional mechanisms that include the use of compare-and-swap (CAS) synchronization primitives and address the ABA problem through the use of a unique number.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: A communication device having a plurality of processor units is disclosed. Each processor unit has a buffer for buffering packets, a receiving processor, and a transmitting processor. Upon receipt of a reception token, the receiving processor receives packets from the outside. Then, if the buffer is empty, the receiving processor buffers the received packets in the buffer. If the buffer is not empty, the receiving processor discards the received packets, increments the number of discarded packets, and passes the reception token to another processor unit for circulation. Upon receipt of a transmission token, the transmitting processor transmits the packets in the buffer to the outside based on the number of discarded packets.

Abstract: One aspect of the invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The media access control system comprises one or more local buffers and is adapted to read a second data frame from the memory system while a first data frame is being transmitted to the network. The invention is particularly useful when the memory system has a single memory sharing several clients. When a memory has several clients, there can be instances where a read of the memory by the media access control system is delayed because the memory is busy with a request from another client. The invention helps ensure that such delays do not result in transmission errors and reduces the effect of such delays on overall transmission speed.

Abstract: A computer program product and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation.

Abstract: A file allocation system for a hard disk drive includes a memory with driver logic and a processor configured with the driver logic to receive a request to allocate hard disk space of a defined size for a buffer file. In some embodiments, the processor is configured with the driver logic to allocate clusters for the buffer file from a plurality of clusters on the hard disk, wherein the clusters for the buffer file store media content instances. In some embodiments, the processor is configured with the driver logic to designate a portion of the clusters of the buffer file for at least one non-buffer file such that the non-buffer file is permitted to share the portion of the clusters of the buffer file with the buffer file.

Abstract: A method, system, and computer program product for safeguarding nonvolatile storage (NVS) data by a processor in communication with a memory device following a power loss event is provided. A first portion of the NVS data is encrypted using a first buffer module. Subsequently the first portion of the NVS data is transferred to at least one shared storage device, while a second portion of the NVS data is simultaneously encrypted using a second buffer module. The second portion of the NVS data is subsequently transferred to the at least one shared storage device.

Abstract: The present disclosure includes systems and techniques relating to a non-volatile memory that includes an internal data source. In some implementations, a device includes a buffer, a memory cell array, and processing circuitry coupled with the buffer and the memory cell array, and configured to selectively fill the buffer with auxiliary data from the internal data source specified by the controller and user data received from an external source, in response to instructions from the controller.

Abstract: Provided is a substrate processing system configured to provide proper data. The substrate processing system comprises a substrate processing apparatus comprising a plurality of components, a controller configured to control the substrate processing apparatus by setting a sequence prescribing time and components, and a collection unit configured to collect data from the components. The collection unit is configured to match data collected from the components via the controller with data collected directly from the components.

Abstract: A method for providing a buffer status report in a mobile communication network is implemented between a base station and a user equipment. When data arrives to buffers of the user equipment and the priority of a logical channel for the data is higher than those of other logical channels for existing data in the buffers, a short buffer status report associated with the buffer of a logical channel group corresponding to the arrival data is triggered. The user equipment is based on obtained resources allocated by the base station to fill all data of the buffer of the logical channel group in a Protocol Data Unit. If all data of the buffer of the logical channel group corresponding to the arrival data can be completely filled in the Protocol Data Unit, the short buffer status report is canceled. Otherwise, the user equipment transmits the short buffer status report.

Abstract: A file allocation system for a hard disk drive includes a memory with driver logic and a processor configured with the driver logic to receive a request to allocate hard disk space of a defined size for a buffer file. In some embodiments, the processor is configured with the driver logic to allocate clusters for the buffer file from a plurality of clusters on the hard disk, wherein the clusters for the buffer file store media content instances. In some embodiments, the processor is configured with the driver logic to designate a portion of the clusters of the buffer file for at least one non-buffer file such that the non-buffer file is permitted to share the portion of the clusters of the buffer file with the buffer file.

Abstract: A communication system complying with SPI-4 Phase 2 standard includes a local device, an opposing device, a first data channel to transfer payload data from the local to the opposing device, a second data channel opposed to the first data channel, and a first status channel to be able to transfer data from the local to the opposing device. The local device periodically outputs buffer status information of a data buffer for storing payload data received over the second data channel to the first status channel. Further, the local device inserts the buffer status information between the payload data according to a priority of the buffer status information in order to output the buffer status information to the first data channel. The opposing device controls to output payload data to the second data channel according to the buffer status information received over the first status channel and the first data channel.

Abstract: Certain embodiments of the invention may be found in a method and system for handling data in port bypass controllers for storage systems and may comprise receiving a data stream from a receive port bypass controller's port and buffering at least a portion of the received data stream in at least one EFIFO buffer integrated within the port bypass controller. A data rate or frequency of the received data stream may be changed by inserting at least one extended fill word in the buffered portion of the received data stream or by deleting at least one fill word from the received data stream buffered in the EFIFO buffer. The extended fill word may comprise a loop initialization primitive (LIP), a loop port bypass (LPB), a loop port enable (LPE), a not operation state (NOS), an offline state (OLS), a link reset response (LRR) and/or a link reset (LR).

Abstract: A method for processing using a shared file that includes allocating a first working buffer between the shared file and a plurality of address spaces, wherein each of the plurality of address spaces is associated with one of a plurality of processors, copying first data from the shared file to the first working buffer by a first aggregator copying the first data from the first working buffer to the plurality of address spaces by the first aggregator, processing the first data, in parallel, by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.

Abstract: A semiconductor memory device includes a plurality of output buffer units connected to a plurality of terminals. Each of the output buffer units includes a first high speed data output (HSDO) buffer adapted to buffer even-numbered data of a corresponding data row among a plurality of data rows and to output the even-numbered data to a corresponding terminal among the plurality of terminals, a second HSDO buffer adapted to buffer odd-numbered data of the corresponding data row and to output the odd-numbered data to the corresponding terminal, and a buffer selector adapted to select and activate the first HSDO buffer and/or the second HSDO buffer in response to a corresponding control signal out of at least one control signal during a HSDO test.

Abstract: Method and apparatus for synchronizing a software buffer index with an unknown hardware buffer index. Specifically, a method of processing data is disclosed comprising synchronizing a software buffer index to a hardware buffer index. The method sequentially searches through a plurality of buffers containing data to find a second buffer with unprocessed data. The method is implemented when the software buffer index points to a first buffer containing processed data. Thereafter, the software buffer index is reset to the next available buffer having processed data following the second buffer.

Abstract: An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Abstract: A processing engine includes descriptor transfer logic that receives descriptors generated by a software controlled general purpose processing element. The descriptor transfer logic manages transactions that send the descriptors to resources for execution and receive responses back from the resources in response to the sent descriptors. The descriptor transfer logic can manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources all on behalf of the general purpose processing element.

Abstract: An apparatus and method is provided to facilitate Input/Output (I/O) transfer in resource limited storage environment. Scatter gather list, segment and memory data buffer allocation are dynamically managed. I/O transfer performance is increased through the use of a data cut-through buffer mechanism.

Abstract: Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

Abstract: A receive virtual concatenation processor (processor) is adapted to receive time-slot interleaved data carried over SONET/SDH frames. The processor first generates per time-slot data and subsequently generates per channel data. The processor supports virtual concatenation, contiguous concatenation as well as mixed concatenation in which some channels are contiguously concatenated and others are virtually concatenated. The processor supports virtual concatenation at both STS-1 and STS-3c granularities and with arbitrary differential delay among constituent time-slots. The processor supports contiguous concatenation with any multiple of STS-3c granularity. The processor is highly scalable to support multiple channels and different frame sizes such as STS-12, STS-48, STS-192, etc.

Abstract: An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.

Abstract: A method for remotely communicating with a computer system in a headless environment is provided. The system includes a service processor in communication with a computer through a UART communication channel and in communication with a remote console through a communication connection. The service processor manages communication commands between the computer and the remote console. The service processor transmits data communication received from the remote console to the computer through the UART channel, and the service processor transmits data communication received from the computer to the remote console through the UART channel. In addition, a multiplexer may be employed to direct communication between one of a plurality of computers and the service processor in combination with a multiplexer control to select one of the computers for communication with the service processor. The multiplexer directs the communication through the UART channel.

Abstract: A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein the first read latch signal does not change the pointer location of the read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.

Abstract: In a circuit coupled to a port of a network having a loop architecture, a read/write pointer controller provides a read and a write pointer to track transmission words stored in a FIFO array. The read/write pointer controller also provides a FIFO level indicator to track the total number of transmission words in the FIFO array. A dynamic threshold controller tracks transmission word insertions and deletions in the FIFO array for a predetermined period of time and provides a threshold level adjustment signal based on the tracked transmission word insertions and deletions and a transmission word threshold level. A FIFO level adjuster provides transmission word insert and delete commands and adjusts the threshold level of the FIFO array in response to the threshold level adjustment signal.

Abstract: Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.

Abstract: Methods and systems are provided for reducing partial cache writes in transferring incoming data status entries from a peripheral device to a host. The methods comprise determining a lower limit on a number of available incoming data status entry positions in an incoming data status ring in the host system memory, and selectively transferring a current incoming data status entry to the host system memory using a full cache line write if the lower limit is greater than or equal to a first value. Peripheral systems are provided for providing an interface between a host computer and an external device or network, which comprise a descriptor management system adapted to determine a lower limit on a number of available incoming data status entry positions in an incoming data status ring in a host system memory, and to selectively transfer a current incoming data status entry to the host system memory using a full cache line write if the lower limit is greater than or equal to a first value.

Abstract: The present disclosure provides a management system and method for data storage. A storage management system comprising a plurality of data output units, a plurality of buffers, a memory, and a processor. The plurality of buffers correspond to the data output units is coupled to the data output units respectively and configured for storing data outputted from the data output units temporarily. The processor comprises a selecting module, a memory apportioning module, a copy module, and a writing module. The selecting module is electrically coupled to the plurality of buffers, and is configured for selecting a buffer from the plurality of buffers as a combined buffer. The memory apportioning module is electrically coupled to the combined buffer, and is configured for leaving out a memory paragraph in the combined buffer. The copy module is electrically coupled to the plurality of buffers, and configured for copying the data in the rest of the buffers into the memory paragraph of the combined buffer.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: A low latency peripheral device sharing system has a host computer with an operating system, a kernel memory buffer, applications, device specific drivers, and a peripheral server driver. The server driver intercepts function calls invoking the local serial ports, and passes standard serial data from the application to a local area network. A device server on the local area network reads the data using a hybrid read block (semi-blocking read), and writes the data to the FIFO registers of the serial device and the remaining data to a queue for the serial device. Finally, the device server times the serial data and returns an intercharacter interval timer flag to the host computer to terminate a read operation.

Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.

Abstract: An integrated circuit includes a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; a first buffer that stores data from the switch; a memory accessible to the processor; a second buffer that stores a plurality of data words retrieved from the memory; and a multiplexer that selectively provides data to the processor from the first buffer or the second buffer based on a refill signal.

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.

Abstract: A data transfer control device, which transfers a large capacity of data speedily and sequentially, has three buffers that are used as a WR (write) buffer, an intermediate buffer, and an RD (read) buffer. To send data sequentially, the data transfer control device switches-over the buffers in one of the following three ways (A), (B), and (C), using determination flags indicating whether the buffers store effective data (data not yet referenced). A buffer control device switches-over (A) the WR buffer and RD buffer if a WR buffer effective flag 33 is on and an intermediate buffer effective flag 34 and an RD buffer effective flag 35 are off, (B) the WR buffer and the intermediate buffer if the WR buffer effective flag 33 and the RD buffer effective flag 35 are on and the intermediate buffer effective flag 34 is off, and (C) the intermediate buffer and the RD buffer if the intermediate buffer effective flag 34 is on and the RD buffer effective flag 35 is off.

Abstract: A data storage apparatus having improved data transfer performance. The storage apparatus has: plural controllers connected to each other by first data transfer paths; plural processors controlling the controllers; and second data transfer paths through which the controllers send data to various devices. Each of the controllers has a data-processing portion for transferring data to the first and second data transfer paths. The data-processing portion has a header detection portion for detecting first header information constituting data, a selection portion for selecting data sets having continuous addresses of transfer destination and using the same data transfer path from plural data sets such that a coupled data set is created from the selected data sets, a header creation portion for creating second header information about the coupled data set, and coupled data creation means for creating the coupled data set from the selected data sets and from the second header information.