Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.

Abstract: A method for exchanging message data in a distributed computer system between a sending and a receiving hardware system. The sending hardware system includes a first memory system and a receiving hardware system which includes a second memory system with a second data buffer and a second memory region. The sending hardware system and the receiving hardware system are coupled via a non-transparent bridge unit. The method includes allocating empty memory, writing information about the empty memory, copying payload data directly from the sending hardware system to the empty memory locations, and writing information about the copied payload data to the second data buffer of the second memory system inside the receiving hardware system. A system and computer program product for carrying out the method are also provided.

Abstract: Various embodiments writing data are provided. In one embodiment, the data arranged in a plurality of write intervals is loaded into a plurality of buffers, the totality of the plurality of buffers configured as a sliding write window mechanism adapted for movement to accommodate the write intervals. The data may reach the storage system out of a sequential order, and by loading it appropriately into the said buffers the data is ordered sequentially before it is written to the storage media. When a commencing section of the sliding write window is filled up with written data, this section is flushed to the storage media, and the window slides forward, to accommodate further data written by the writers. The writers are synchronized with the interval reflected by the current position of the sliding write window, and they send data to be written only where this data fits into the current interval of the window.

Abstract: A data processing apparatus may include a data acquisition unit, a buffer unit that includes a plurality of division buffers, a valid data area determination unit that calculates an area of valid data, a buffer state management unit that manages whether or not the data is stored in the division buffer, a data write control unit that writes data of a unit of the storage capacity of the division buffer, which at least includes data indicated to be valid data by the valid data information within the data, to the division buffer in which no data is stored, the division buffer being selected based on the management information, and a data read control unit that reads data indicated to be valid data by the valid data information from the division buffer in which data is stored, the division buffer being selected based on the management information.

Abstract: An apparatus for sorting items has a buffer device with a multiplicity of buffer storage locations, filled by a loading device, and an intermediate store with a multiplicity of intermediate storage locations. The intermediate store and the buffer device are arranged such that items stored at a buffer storage location can be transferred into an intermediate storage location. The intermediate storage locations are movable at a relative speed with respect to the buffer storage locations and are suitable for receiving more than one item, for presorting. The buffer device is arranged over the intermediate store such that an item located in a buffer storage location can fall into an intermediate storage location. The apparatus has a multiplicity of collecting containers, arranged under the intermediate store, and are at rest during the sorting operation and are filled during the sorting operation with items contained in the intermediate storage locations.

Abstract: A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from which data should be read, and a write pointer to indicate a particular one of the plurality of buffers to which data should be written. The write pointer points at least one buffer ahead of the buffer to which the read pointer is pointing. An electronic system and a telecommunications system are further disclosed.

Abstract: Provided is a serial control device that makes the length of data transferred as one frame variable. The serial control device transfers serial data having an arbitrary length, and uses end information indicating inclusion or non-inclusion of end data of the serial data. The serial control device transfers data having a transfer unit length in the serial data when the end information indicates non-inclusion of the end data, and transfers an untransferred part of the serial data when the end information indicates inclusion of the end data.

Abstract: Various embodiments writing data are provided. In one embodiment, the data arranged in a plurality of write intervals is loaded into a plurality of buffers, the totality of the plurality of buffers configured as a sliding write window mechanism adapted for movement to accommodate the write intervals. The data may reach the storage system out of a sequential order, and by loading it appropriately into the said buffers the data is ordered sequentially before it is written to the storage media. When a commencing section of the sliding write window is filled up with written data, this section is flushed to the storage media, and the window slides forward, to accommodate further data written by the writers. The writers are synchronized with the interval reflected by the current position of the sliding write window, and they send data to be written only where this data fits into the current interval of the window.

Abstract: A plurality of registers may function as both the control and status registers. Each bit location of the registers is writable to set a value on a control signal and readable to read a current value on a status signal. A multiplexer provides readability of the current value of each of the registers.

Abstract: An audio system communicates with an aggregate device that includes multiple audio devices. When providing audio data for playback, the system compensates for presentation latency differences between the various audio devices. In addition, the system adjusts for device clock drift by selecting a master device and resampling the audio data provided to the other devices based on the difference between the device clock of the master device and the device clocks of the other devices.

Abstract: The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device with a memory core, a high speed upstream data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer spanning a plurality of asynchronous timing domains that delivers the data onto the upstream data bus to minimize gaps in a data transfer. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a high speed data bus with pre-determined timing in a manner which minimizes latency to the extent that the returning read data beats are always transmitted contiguously with no intervening gaps.

Abstract: A storage management system and a storage management method are provided. The storage management system includes a host, a memory buffer, a plurality of storage blocks, and an input/output bus to perform an interface function among the host, the memory buffer, and the plurality of storage blocks, wherein each of the plurality of storage blocks is connected with the input/output bus via a corresponding channel, and the plurality of storage blocks is managed for each channel group generated by grouping at least one channel.

Abstract: In the method, data are transmitted between a first memory allocated to a source computer and a second memory allocated to a target computer via a network by remote direct memory access. On the source computer side, a predetermined number of directly consecutive transmission buffers is selected from a continuous buffer memory area and transmitted in a single RDMA transmission process to the target computer. On the target computer side, an RDMA data transfer is executed over the entire continuous buffer memory area and a buffer sequence procedure. The buffer sequence procedure causes the received buffers to be supplied to the target application in the transmitted sequence.

Abstract: Method and system for efficient buffer management for layer 2 through layer 5 network interface controller applications are provided. Aspects of the method may comprise determining whether an active NIC connection is an L2 type, an L4 type, or an L5 type. At least one buffer descriptor may be cached locally on a network interface controller (NIC) managed by a NIC application. The buffer descriptor is associated with the determined type of the active NIC connection. If the at least one active NIC connection is of the L2 or L4 type, the buffer descriptor may comprise at least one of a receive (RX) buffer descriptor and a transmit (TX) buffer descriptor. If the NIC connection is of the L5 type, the buffer descriptor may comprise at least one of a upper translation page table (TPT) entry and a lower TPT entry.

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN/OUT bulk transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. In a bulk-IN transaction, before the host sends an IN packet, the controller pre-fetches data and stores the data in the buffers until all the buffers are full or a requested data length has been achieved; the pre-fetched data are then sent to the host after the host sends the IN packet. In a bulk-OUT transaction, the controller stores the data sent from the host in the buffers, and the data are then post-written to the device.

Abstract: Disclosed is a technique for flow control. It is detected that a work request is being transferred to an in-memory structure. A maximum limit is compared with a number of work requests stored in the in-memory structure. If the number of work requests stored in the in-memory structure equals the maximum limit, a notification is sent that indicates that additional work requests are not to be sent.

Abstract: An information processing apparatus includes a communication processing unit configured to communicate with an external communication device and a data processing unit configured to communicate with the communication processing unit via a wired data communication path. The data processing unit is configured to interpret address information received from the external communication device. The communication processing unit includes a memory where data transmitted and received between the external communication device and the data processing unit is temporarily stored. The communication processing unit further includes a control unit configured to control data writing in and data reading from the memory, perform an error check process by a code included in a received data from the external communication device, and transmit the address information received from the external communication device to the data processing unit without interpreting the address information.

Abstract: The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device comprising: a memory core, a shared data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer that delivers the data onto the shared data bus with pre-determined timing. The present invention can also be viewed as providing methods for controlling moving data entries in a hierarchical buffer system. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a shared data bus with pre-determined timing.

Abstract: A data transfer control device including: a link controller which analyzes a packet received through a serial bus; a packet detection circuit which detects completion or start of packet reception based on analysis result of the received packet; first and second packet buffers into which the packet received through the serial bus is written; and a switch circuit which switches a write destination of the received packet. When a Kth packet has been written into one of the first and second packet buffers and completion of reception of the Kth packet or start of reception of a (K+1)th packet subsequent to the Kth packet has been detected, the switch circuit switching the write destination of the (K+1)th packet to the other of the first and second packet buffers.

Abstract: In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

Abstract: The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.

Abstract: Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability of the storage buffer slot for the cache index as specified by the request. Upon determining the storage buffer slot is not available, the dynamic allocation of cache buffer slots includes evicting data stored in the storage buffer slot, and reserving the storage buffer slot for data associated with the request.

Abstract: A data processing apparatus is provided comprising a buffer for buffering data contained in a data stream generated by a data stream generator and received by a data stream receptor. Buffer occupancy tracking circuitry is provided and configured to maintain a high buffer utilisation value providing an indication of a high buffer occupation level for a given time period during utilisation of the buffer. Alternatively, in an apparatus where the buffer is implemented in dedicated memory, the buffer occupancy tracking circuitry is configured to store a programmable buffer size limit controlling a maximum allowable buffer storage capacity.

Abstract: A computer implemented method, data processing system, and computer program product for detecting circular buffer overflow. When an entry in the circular buffer is read, a valid mark bit in the entry is set to an inactive state and the location of the entry is stored as an entry previously processed. A valid mark bit of a next entry and the valid mark bit in the entry previously processed are read. Responsive to determining that the valid mark bit in the entry previously processed is in the inactive state and the valid mark bit in the next entry is in an active state, the next entry is read, the valid mark bit in the next entry is set to an incactive state, and the location of the next entry is stored as the entry previously processed. Responsive to determining that the valid mark bit in the entry previously processed is in the active state, a determination is made that a circular buffer overflow has occurred.

Abstract: An information processing apparatus includes a communication processing unit configured to communicate with an external communication device; and a data processing unit configured to communicate with the communication processing unit and carry out data processing. The communication processing unit includes a memory where data transmitted and received between a communication device and the data processing unit is temporarily stored, and a control unit configured to control data writing and data reading. When a command packet received from the communication device is a data reading request, the control unit acquires data from the memory and transmits the data to the communication device. When the command packet received from the communication device is a data writing request, the control unit stores data in the memory, acquires data from the memory in response to the request from the data processing unit, and outputs the data to the data processing unit.

Abstract: One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to destination components within the computer system. The control information may belong to various traffic paradigms, such as short-latency data traffic, narrow-width data traffic or broadcast data traffic. The physical connections within the control crossbar unit are categorized based on the different types of control information being transmitted through the control crossbar unit. The physical connections belong to the following categories: one-to-one (OTO) connections, one-to-many (OTM) connections, valid-to-one (VTO) connections, valid-to-many (VTM) connections wire-to-one (WTO) connections and wire-to-many (WTM) connections.

Abstract: In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffer during one monitor cycle when the frame data is to be read without fail from the shared buffer, an address space where the frame data has not been read from the shared buffer is detected during a next monitor cycle, and an address space where not a read but a write of the frame data has been performed at least during the monitor cycle is detected. In the next monitor cycle, the address space is released as a free address of the shared buffer.

Abstract: A data acquisition service on a network node is disclosed for forwarding received process data to a process history database over a potentially slow and/or intermittent network connection. A store and forward functionality within the networked node receives incoming process data via a first network interface and forwards outgoing process data via a second network interface. The disclosed store and forward functionality includes an immediate transmission cache and a store and forward storage. The store control enters, in response to detecting an entry condition, an activated mode wherein incoming process data is directed to the store and forward storage. A read control forwards outgoing process data to the second network interface from the immediate transmission cache and store and forward storage. The read control includes at least a first configurable parameter that constrains a rate at which data retrieved from the store and forward storage is forwarded via the second network interface.

Abstract: A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.

Abstract: A method is provided for generating a control vector. The method comprising: providing a circular buffer having a plurality of storage elements that are arranged sequentially from a designated first storage element to a designated last storage element, and when the designated last storage element of the plurality of storage elements is accessed, the access continuing in a sequential order continuing with the designated first storage element; determining a beginning storage element of the plurality of storage elements to be accessed; and generating a control vector, the control vector comprising a plurality of index values, each of the plurality of index values corresponding to one of the plurality of storage elements of the circular buffer to be accessed in the sequential order from the beginning storage element to an ending storage element.

Abstract: A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.

Abstract: An audio system communicates with an aggregate device that includes multiple audio devices. When providing audio data for playback, the system compensates for presentation latency differences between the various audio devices. In addition, the system adjusts for device clock drift by selecting a master device and resampling the audio data provided to the other devices based on the difference between the device clock of the master device and the device clocks of the other devices.

Abstract: A method for maintaining flow control in a buffer memory coupled to a storage controller is provided. The storage controller includes, first and second counters that are used to monitor when data is read from a buffer memory and when data is transferred from the buffer memory to the host. The method includes, incrementing first and second counter values when data is placed in the buffer memory; decrementing a first counter value when data is read from the buffer memory; and decrementing the second counter value when data is sent to a host. The method further includes, pausing a first channel logic between a transport module and a storage disk when there is no data in the buffer memory; and pausing a second channel logic between a disk and the buffer if there is no space in the buffer memory.

Abstract: This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices.

Abstract: Various embodiments for writing received synchronized data to magnetic tape having a plurality of wraps using a magnetic tape drive adapted for performing the writing according to an available plurality of predefined tape speeds are provided. In one such embodiment, for each of the available plurality of predefined tape speeds, an average overhead per synchronized command for performing a recursively accumulated backhitchless flush (RABF) cycle is calculated. One of the available plurality of predefined tape speeds having a lowest calculated average overhead is selected. The RABF cycle is performed using the selected one of the available plurality of predefined tape speeds.

Abstract: A method for queuing thread update buffers to enhance garbage collection. The method includes providing a global update buffer queue and a global array with slots for storing pointers to filled update buffers. The method includes with an application thread writing to the update buffer and, when filled, attempting to write the pointer for the update buffer to the global array. The array slot may be selected randomly or by use of a hash function. When the writing fails due to a non-null slot, the method includes operating the application thread to add the filled update buffer to the global update buffer queue. The method includes, with a garbage collector thread, inspecting the global array for non-null entries and, upon locating a pointer, claiming the filled update buffer. The method includes using the garbage collector thread to claim and process buffers added to the global update buffer queue.

Abstract: The disclosed embodiments relate to a system for controlling accesses to one or more memory devices. This system includes one or more write queues configured to store entries for write requests, wherein a given entry for a write request includes an address and write data to be written to the address. The system also includes a search mechanism configured to receive a read request which includes an address, and to search the one or more write queues for an entry with a matching address. If a matching address is found in an entry in a write queue, the search mechanism is configured to retrieve the write data from the entry and to cancel the associated write request, whereby the read request can be satisfied without accessing the one or more memory devices.

Abstract: A system and method for sharing peripheral first-in-first-out (FIFO) resources is disclosed. In one embodiment, a system for utilizing peripheral FIFO resources includes a processor, a first peripheral FIFO controller and a second peripheral FIFO controller coupled to the processor for controlling buffering of first data and second data associated with the processor respectively. Further, the system includes a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller for merging a first FIFO channel associated with the first peripheral FIFO controller and a second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel respectively. Also, the system includes a first FIFO and a second FIFO coupled to the merge module via the first FIFO channel and the second FIFO channel respectively.

Abstract: Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into a transmit buffer allowing the transmitting device to begin transmitting packets with the sequence count expected by the receiving device.

Abstract: A remote copy method for copying data within a first storage apparatus to a second storage apparatus via a network, includes transmitting data from the first storage apparatus in units of first buffer sets each formed by a plurality of first recording exclusive buffers within the first storage apparatus, and receiving the data by the second storage apparatus in units of second buffer sets each formed by a plurality of second recording exclusive buffers within the second storage apparatus, so as to maintain a sequence guarantee with respect to the data that is copied.

Abstract: An apparatus for sorting items has a buffer device with a multiplicity of buffer storage locations, filled by a loading device, and an intermediate store with a multiplicity of intermediate storage locations. The intermediate store and the buffer device are arranged such that items stored at a buffer storage location can be transferred into an intermediate storage location. The intermediate storage locations are movable at a relative speed with respect to the buffer storage locations and are suitable for receiving more than one item, for presorting. The buffer device is arranged over the intermediate store such that an item located in a buffer storage location can fall into an intermediate storage location. The apparatus has a multiplicity of collecting containers, arranged under the intermediate store, and are at rest during the sorting operation and are filled during the sorting operation with items contained in the intermediate storage locations.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: A device for data packet processing is disclosed. In one embodiment, the device includes a processor implemented on a chip, an on-chip internal segment memory accessible by the processor, an off-chip external segment memory and a data transfer channel between the internal segment memory and the external segment memory. The external segment memory comprises first and second memory segments wherein the first and second memory segments are different in size.

Abstract: The present invention discloses a method of editing a multi-media playing schedule for a digital photo frame, a system and a computer readable storage medium thereof, which are characterized in that users can edit a multi-media playing schedule on the data processing apparatus when the digital photo frame is electrically connected to the data processing apparatus, and after editing of the multi-media playing schedule is finished, the multi-media playing schedule is transmitted to the digital photo frame and stored in the digital photo frame. Therefore, the problem of being unable to edit complicated multi-media playing schedules due to simple operation interface of digital photo frames can be solved.

Abstract: In a circuit coupled to a port of a network having a loop architecture, a read/write pointer controller provides a read and a write pointer to track transmission words stored in a FIFO array. The read/write pointer controller also provides a FIFO level indicator to track the total number of transmission words in the FIFO array. A dynamic threshold controller tracks transmission word insertions and deletions in the FIFO array for a predetermined period of time and provides a threshold level adjustment signal based on the tracked transmission word insertions and deletions and a transmission word threshold level. A FIFO level adjuster provides transmission word insert and delete commands and adjusts the threshold level of the FIFO array in response to the threshold level adjustment signal.

Abstract: A buffering apparatus to process digital communication signals includes a plurality of buffers, a processing unit, and programmed memory. The programmed memory has instructions directing the processing unit to process the digital samples corresponding to a group of symbols to be processed in a plurality of buffers. The digital samples start in a first buffer of the plurality of buffers and end in a second buffer of the plurality of buffers. The digital samples are received at a third buffer of the plurality of buffers during the processing of the digital samples.

Abstract: A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a pointer location of a read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.

Abstract: A multimedia data processing apparatus with reduced buffer size includes an accessing unit and a data processing module. The accessing unit has a plurality of buffers therein. The data processing module includes a processing unit and a real-time buffer. The processing unit processes the data temporarily stored in the accessing unit and the real-time buffer. By adding the real-time buffer, the size of the buffer in the accessing unit and the maximum bandwidth requirement can be reduced thereby increasing the system performance.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: A software layer for boosting the throughput of a computer file server by reducing the number of required mechanical accesses to the physical storage is provided. The throughput boost is achieved through the combination of extending the data requests along the file path and inserting double-buffered paths in front of each file accessed. The software layer resides on top of the file system, where it can extend requests along the file path, work with network requests arriving over any network using any protocol, and work with any storage system attached to the server. The software layer can also be used in a server to accelerate requests made by local applications in the server or it may be used in any other computer to accelerate requests made by local applications that require data from local storage.