Abstract: The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit resolves the overflow by suspending operation of the stack cache and spilling a plurality of data words from the stack cache to the stack and equating the bottom pointer to the optop pointer. Typically, the overflow/underflow unit spills all valid data words from the stack cache during an overflow.

Abstract: The invention includes an apparatus and method for buffering data transmitted by a processor and received by an I/O device via a memory and buses. The memory arranged at a plurality of levels includes a lower level of the memory operating faster than a higher level of the memory. A plurality of ring buffers are allocated at different levels of the memory and available buffers at a lowest possible level of the memory are preferentially selected as write buffers to store data transmitted by the processor. The apparatus includes a first level of the memory arranged on an integrated circuit with the processor, a second level of the memory arranged in an off-chip cache, and a third level of the memory arranged in a dynamic random access memory. Read buffers are selected to store data to be received by the I/O device. Stored control values indicate the order for selecting the read buffers and are used by the processor to select the write buffer.

Abstract: A method and apparatus of interfacing data between a microprocessor and a memory, in which the microprocessor accesses data temporarily stored in the memory. The microprocessor controls a read timing according to an interrupt signal so as to generate a transmission request signal, the data being read according to the transmission request signal, and the interrupt signal being generated when a predetermined amount of data is stored in the memory.

Abstract: Multiple nodes can concurrently gain membership in a cluster of nodes of a distributed computer system by broadcasting reconfiguration messages to all nodes of the distributed computer system. In response to a reconfiguration request resulting from a node petitioning to join a cluster or a node leaving the cluster, each node determines to which nodes of the distributed computer system the node is connected, i.e., which are sending reconfiguration messages which the node receives. In addition, if multiple nodes fail substantially simultaneously, each node which continues to operate does not receive a reconfiguration message from each of the failed nodes and the failed nodes are omitted from the proposed new cluster. Thus, multiple simultaneous failures are processed in a single reconfiguration. Each of the member nodes of the proposed cluster determine the membership of the proposed cluster and broadcast a reconfiguration message to all proposed member nodes and collects similar messages.

Abstract: A data communication circuit buffers data between a shared resource and a plurality of data communication interfaces through a plurality of respective first-in-first-out ("FIFO") buffers. The data is divided into multiple-bit data frames having a start and an end. The circuit maintains a priority level for each FIFO buffer and initializes the priority level of each FIFO buffer to a first priority level. The circuit passes bits of the multiple-bit data frames from the shared resource to respective ones of the FIFO buffers in a buffer order which is based on the priority level of each FIFO buffer. The circuit passes the bits from the FIFO buffers to the respective data communication interfaces and selectively increases the priority level of each FIFO buffer to a second, higher priority level as a function of a level the bits within the FIFO buffer and whether the end of at least one data frame is stored in the FIFO buffer.

Abstract: A method and apparatus for processing and transferring frames of data in a computer data link that maps incoming frames to a specific buffer ring in host memory based on routing control and type fields in each frame. More particularly, a Fibre Channel link port contains receiver routing code (RRCode) registers that allow host software to set up routing control (R.sub.-- CTL) match and mask fields, and TYPE match and mask fields. The link port uses these registers to match and mask against corresponding R.sub.-- CTL/TYPE fields in a received frame to determine which of several R.sub.-- CTL/TYPE host memory buffer rings should be used to store the received frame. The link port places a code (RRCode) in a start of frame (SOF) status word associated with a frame. The RRCode indicates a specific R.sub.-- CTL/TYPE host memory buffer ring, or indicates that no match was found or that multiple matches were found.

Abstract: A method of improving storage system performance is provided. The method includes queuing asynchronous requests for data stored in physically disparate storage locations. The queue is then examined in order find those requests for data which has an acceptable level of physical proximity. Those requests having acceptable physical proximity are then bundled and transmitted as a single request a storage controller which activates the storage device and retrieves the data associated with the requests bundled into the single request.

Abstract: A three port FIFO buffer circuit uses off the shelf static RAM and dedicated shallow, e.g. 16 word, FIFOs in a multi-level caching scheme. The circuit results in multiple, reconfigurable, deep (e.g. up to 32k word) FIFO buffers. The preferred embodiment of the invention provides a buffer that comprises a bank of 32k word RAM, six dual port 16-word FIFOs, and associated sequencing logic. The sequencing logic includes RAM address registers/counter associated with each of the six FIFOs, and manages the movement of data into and out of the RAM.

Abstract: An apparatus for processing transfer data to be transferred in synchronism with one of an external write signal and an external read signal, includes a plurality of memories for storing the transfer data. A plurality of sync signal generators are provided in association with the memories, to generate one of a sync write signal and a sync read signal, which determine write and read timings for the memories, in response to one of the external write signal and the external read signal and an internal clock having a longer period than the one of said external write signal and the external read signal. A distribution circuit is connected to the plurality of sync signal generators, for receiving one of the external write signal and the external read signal and sequentially distributing the one of the external write signal and the external read signal to the sync signal generators.

Abstract: In a digital system having a host, a controller device and at least one flash memory integrated circuit, a method and apparatus for storing location identification information regarding blocks of information within at least one of the flash memory integrated circuits wherein at least two buffers within the at least one of the flash memory integrated circuits are designated as primary and secondary buffers for storing the identification information in the primary buffer until the primary buffer is effectively full and storing additional identification information in the secondary buffer until it is effectively full, swapping buffer designation so that the primary buffer becomes the secondary buffer and the secondary buffer becomes the primary buffer, erasing the effectively-full buffer for re-use and in this manner, continuously swapping storage of identification information between the two buffers.

Abstract: An apparatus and method for write posting in a universal serial bus (USB) system includes a host computer connected to USB devices via a USB. The host computer generates requests to write data to memory within the USB device. The host computer includes a queue for posting the write requests on generation thereof. The write requests are posted in the queue until the host computer transmits a single data packet generated from the posted write requests. The Data packet is generated in response to the host computer generating a request to read data from the USB device, the host computer determining that the most recently posted write request is directed to a memory location within the USB device which is nonpostable, or an indication that the queue lacks storage space for subsequent write requests. The USB device receives the transmitted Data packet from the host computer and writes data to internal memory locations in accordance with the received Data packet.

Abstract: A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

Abstract: A memory control device having a plurality of data transfer paths including a storage device group comprising a plurality of storage devices for storing data and a buffer memory group comprising multiple buffer memories for storing transferred data, dividing files into multiple blocks for storing blocks in multiple storage devices on different data transfer paths, and executing control to read data from the storage device to be output with a request from a connected terminal to the buffer memory wherein storage devices on different paths create multiple virtual storage device groups, and buffer memories create virtual buffer memory groups. The memory control device comprises a data output control for executing control in a first cycle, the data being temporarily dividedly stored in a prescribed virtual storage device group.

Abstract: In an audio/video server blocks of data are read from a storage medium by a reader and supplied to users in the form of data streams. The storage medium comprises a plurality of record-carrier based storage units. A reader reads a batch of data units from a storage unit in a single relative movement of a reading head of the storage unit with respect to the record-carrier of the storage unit. A scheduler controls reading of blocks from the storage medium by determining from which storage unit(s) data unit(s) need to be read for the block and placing a corresponding carrier access request in a read queue. The scheduler extracts for each of the storage units a batch of carrier access requests from the queue and issues the batch to the reader in an asynchronous manner, in response to the reader having substantially completed reading data units for a previous batch for the storage unit.

Abstract: A data processing system comprising a first circuit block 6 and a second circuit block 8 linked via an asynchronous first-in-first-out buffer circuit 12 is provided with a burst marker that identifies the first word in a burst transfer or an empty stage. The second circuit block 8 uses the burst marker to identify the last data word in a burst as being that word which immediately precedes such a burst marker.

Abstract: An improved multi-stage synchronizer. The inventive synchronizer includes a first memory for storing data, a second memory means connected to the output of said first memory means for storing data, and a third memory for storing data connected to the output of said second memory means. The second memory includes a plurality of multi-stage first-in, first-out memory devices. In a particular embodiment, the first and third memories are implemented with synchronous single stage first-in, first-out memories. In a preferred embodiment, the first-in, first-out memories are designed to allow data to be read and written during a single clock cycle after the memory is full. This is achieved by adding an external read signal to the `not full` signal generated by the device. The provision of single stage FIFO memories on either side of a multi-stage FIFO memory allows for lower set up time and output delay at higher operational speeds.

Abstract: A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing transmit frame data received from a host bus into the random access memory, and generating tracking information based on transfer status signals corresponding to the transfer of the data frame from either a master transfer mode or a slave transfer mode. Hence, the amount of logic associated with generating the tracking, control and/or status information is independent of the nature of the transfer from the host bus. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller to access the status information and the corresponding data frame as a single data unit.

Abstract: The present invention relates to a method and apparatus for buffering data. The apparatus stores information in a buffer. When the buffer is full, overflow data is stored in an overflow memory. As data is removed from the buffer, the overflow data is transferred from overflow memory to the buffer.

Abstract: A first-in first-out (FIFO) memory interface is provided by coupling an input register and an output register to a conventional static random access memory (SRAM). The registers and SRAM are coupled to control logic that controls the timing of shift-in (write) and shift-out (read) operations. Upon receipt of a write request signal, input data is received from the requesting device and buffered within the input register. The buffered data is then stored in the SRAM during a write operation. Upon receipt of a read request signal, the data previously buffered in the output register is provided to the requesting device and during an associated read operation the next stored data in the SRAM is retrieved and buffered within the output register. The control logic is programmable and is therefore capable of supporting different SRAM configurations. The control logic can also be implemented in a conventional programmable logic device.

Abstract: An improved diagnosis test apparatus and test method for a small computer system interface (SCSI) that are capable of controlling the input/output of SCSI test data and SCSI signal data which are generated by a host computer without using a peripheral SCSI device. The apparatus includes a host computer for inputting/outputting SCSI control data and SCSI test data, and a controller for receiving and temporarily storing the SCSI control data and SCSI test data from the host computer and for outputting the data to the host computer, for thus testing the SCSI.

Abstract: A computer system includes a first device on the first data bus, a second device on the second data bus, and a bridge device that delivers requests for data from the first device to the second device and returns the requested data to the first device. The bridge device includes a first data storage buffer that stores data requested by the first device during the first request, and a second data buffer that simultaneously stores data requested by the first device during a second request.

Abstract: A method for passing data of an external memory device through a buffer to a data processor is provided. The method divides the storage region of the buffer into two subregions, and passes a first data set read from the external memory device through one of the two subregions to the data processor in response to a first instruction of the data processor. When a second data set required by said data processor is the same as the first data set, the data stored in the one subregion is passed directly to the data processor instead of retrieving the same from the external memory device. When the second data is different from the first data, it is read from the external memory device and passed through the other allocated subregion to the data processor.

Abstract: A method and apparatus for storing data values received within respective cycle periods of a clock signal are disclosed. Data values are alternately stored in first and second data hold registers and then output by each data hold register for a time greater than a cycle period of the clock signal. Address values at which the incoming data values are to be written are alternately stored in first and second address hold registers. Data stored in the first data hold register is written to a latch-based memory element in a first memory bank indicated by an address value stored in the first address hold register. Data stored in the second data hold register is written to a latch-based memory element in a second memory bank indicated by an address value stored in the second address hold register.

Abstract: An apparatus for improving I/O pin interfaces for serial data communications is disclosed. In accordance with a preferred embodiment of the present invention, an improved serial interface is provided, which comprises an oscillator input, a signal input, a counter, a register, and a data output. The counter is utilized to count the number of cycles of the oscillator input for which the signal input is asserted. The register is utilized to receive a value from the counter when the signal input is next de-asserted. The data output is at a first logical state when the signal input is asserted for fewer oscillation cycles than the value stored in the register and the data output is at a second logical state otherwise, such that only one I/O pin is required for serial communications.

Abstract: Method and apparatus for wavetable style playback of audio data received from a bursty source is disclosed. Incoming audio data is directed to one buffer while another buffer is available for playback to permit simultaneous buffer filling and playback. When a buffer becomes full of newly received data, the buffers exchange roles. Methods and apparatus for efficiently and accurately controlling addressing of the buffers for playback are disclosed.

Abstract: An arrangement and a method respectively for handling or getting access to a digital buffer in a digital buffer memory where to each digital buffer a set of pointers is arranged in a reference memory. The arrangement includes a register arrangement defining the position of a digital buffer in the digital buffer memory, an offset value, an address calculation arrangement and an operating address register. For each of the pointers in a set relating to a digital buffer, a separate pointer register is provided and address data is input and stored substantially at the same time in each pointer register corresponding to a set of pointers. The subsequent address for reading/writing in the digital buffer memory is calculated and stored in at least the operating address register.

Abstract: The communication control device allows a plurality of data items to be transferred to and from external devices, such as a CPU and a memory, via an external bus having a different data bus width in DMA (direct memory access) transfer mode. DMA transfer is controlled by the DMA controller provided in the communication control device. The DMA controller produces a signal indicating that a plurality of data items are continual.

Abstract: A versatile USB controller comprises a serial interface engine (SIE) for connection with a host. The SIE is capable of simulating a disconnect/connect sequence in situations where a reboot of the device is appropriate. The controller further includes a control store for keeping track of multiple endpoints of a device. A FIFO provides data transfer between each of the endpoints and the host. A state machine provides transaction sequencing with the host for each endpoint. In a variation of the preferred embodiment, a second FIFO is included to provide additional buffering capability.

Abstract: The present invention reduces the delay in the completion of transferring data from a data channel to an input/output device and the time a host unit is released from performing the data transfer function. A time reduction is realized by monitoring the current data transfer between the data channel and a buffer device to establish a transfer rate. The transfer rate is used to anticipate and coordinate the transfer of the last bit of data from the data channel to coincide with the receipt of the data by the input/output (I/O) unit, effectively eliminating buffer device delay and allowing the host unit to be released from performing the data transfer. In the preferred embodiment, the transfer of the last bit of data by the data channel occurs at substantially the same time as the last bit of data is received by the I/O unit.

Abstract: In a buffer management system for managing a buffer pool, which is divided into a plurality of buffer areas, in response to an acquisition request sent from a processing apparatus, the buffer management system according to the present invention includes: a buffer managing unit for calculating and supervising the number of remaining vacant buffer areas before and after use of the buffer area; a buffer supervising unit operatively connected to the buffer managing unit for supervising a vacant state of each buffer area; and a holding unit operatively connected to the buffer managing unit for holding the number of remaining vacant buffer areas.

Abstract: A plurality of channel data groups and a coupling data group are supplied to a data input port of a data buffering apparatus so as to be temporarily stored in a buffering memory having a first memory area assigned to a non-coupled channel data group, a second memory area assigned to a coupled channel data group and a third memory area assigned to the coupling data group, and the data buffering apparatus outputs the channel data group from the first memory area or the channel data group and the coupling data group from the second and third memory areas before the next channel data group arrives at the data input port so as to decrease the memory areas of the buffer memory.

Abstract: A data transfer mechanism for a serial interface is provided whereby data transfer may be precisely controlled, eliminating the need for significant buffering. The data transfer mechanism also provides for flexible data transfer in either a byte mode or a burst mode so as to accommodate any of various telecommunications devices having a range of capabilities and data rates, and minimizes host involvement in the data transfer operation.

Abstract: A method for queuing hardware control blocks, such as SCBs, for a system including a system processor coupled to a plurality of host adapter devices and a buffer memory controller device by an I/O bus is based on use of an endless new hardware command block queue, and an endless done hardware command block queue. The hardware command blocks for a plurality of devices, where each device includes a device processor, are managed by forming an endless queue for a device in a memory external to the device. A first pointer to the endless queue is maintained in a memory that is not within the memory space of the device processor. A second pointer to the endless queue is maintained in a memory addressable by the device processor. The first and second pointers address the head and tail hardware command block array sites of the endless queue.

Abstract: The present invention includes a method of providing data to a memory device to be read at a first frequency comprising the steps of writing data to a memory device at a second frequency; blocking the writing of data after a predetermined amount of data is written; and writing data to the memory device in response to an address. Also included is a monitor circuit comprising a monitor state machine coupled to receive inputs including a comparison result, count signals and a load enable, and configured to output a data enable signal in response to the inputs.

Abstract: Buffers are provided in a computer system to allow posting data to the buffers, followed by concurrent operation by different portions of the computer system. A CPU buffer is provided to buffer CPU accesses, a CPU-to-PCI buffer is provided to buffer CPU accesses to the PCI local bus, and a memory buffer is provided to buffer CPU accesses to main memory. This configuration allows the CPU-to-PCI buffer to write data concurrently with the memory buffer accessing data from main memory.

Abstract: A method and apparatus for dynamically switching the relative priorities of the load buffer and store buffer with respect to external memory resources in a superscalar processor. According to a first embodiment, a protocol dictates that the load buffer always prevails until the store buffer reaches a certain "high water mark," (an upper threshold) at which time the store buffer gains priority. After the store buffer has gained priority, it continues to access the memory until it is depleted to a "low water mark," (a lower threshold) at which time the load buffer regains priority. Whenever the store buffer reaches the high water mark, it gains priority until it drains down to the low water mark. This reduces the tendency for the store buffer to become full and block the processor. According to a second embodiment, the load buffer prevails if it is above its high water mark.