Abstract: An audio record/playback system is configured using a RAM containing PC buffers and a sound input/output board which is equipped with another RAM containing P buffers and R buffers as well as a digital audio circuit. At a playback mode, waveform sample data consisting of waveform samples are subjected to burst transfer using a PCI bus from the PC buffer to the P buffer in a first half duration of each sampling period with respect to one channel. In a second half duration, one of the waveform samples is transferred from the P buffer to the digital audio circuit, wherein it is subjected to digital audio processing. Thus, the waveform sample data are played back in response to prescribed timings synchronized with sampling periods. At a record mode, waveform sample data corresponding to sounds to be picked up are supplied to the digital audio circuit, from which they are transferred to the R buffer. Then, the waveform sample data are transferred to the PC buffer.

Abstract: A system for handling write requests is described. The system uses two queues for storing posted write requests. When a posted write error results, software handles the posted write error using information stored in a first queue of the two queues. The write request producing the posted write error is cleared from the second queue which continues to handle physical packets containing write requests.

Abstract: A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store operations. Each of the plurality of store operations is to at least a part of a cache line, and the write combining buffer can be snooped in response to requests initiated external to the apparatus.

Abstract: A direct memory access (DMA) controller is provided for a computer system having a processor and a command buffer. The command buffer can be defined, for example, as a ring buffer in the main processor memory and can be directly accessible by the processor, for example over a bus. The DMA controller provides a head register and a tail register operable to hold a head pointer and a tail pointer for addressing the head and tail, respectively, of a sequence of direct memory access commands in the command buffer. The processor is able to store DMA commands in the command buffer. Subsequently, the DMA controller is able to access those DMA commands using the DMA tail pointer held locally in the DMA controller. The DMA controller is operable to compare the head and tail pointers, and to respond to non-equivalence thereof to use the tail pointer value to access direct memory access commands from the command buffer.

Abstract: The operation of a shadow processor for a system having redundant controllers is arranged so that it receives a FIFO fill indicator from another shadow processor associated with that one of the controllers that is in a standby mode, and, if the value of the indicator reaches a predetermined value, then the shadow processor throttles the data writing activity of the active controller for an amount of time sufficient to allow the other shadow processor time to unload the FIFO below a particular fill level.

Abstract: A dual system has system buses that are connected to each other through bus interchange apparatuses and a cross bus to transfer information between the system buses. Each of the bus interchange apparatuses has a first bus controller (1) having a reception controller (6) and a transmission controller (8) that are connected to one (10) of the system buses, a second bus controller (2) having a reception controller (7) and a transmission controller (9) that are connected to the cross bus (11), buffers (3, 4) for relaying information between the first and second bus controllers (1, 2), and a register (5) directly accessible from the first and second bus controllers (1, 2) to write fault information thereto.

Abstract: A queuing method and apparatus for transfer or incoming and outgoing data in a network environment having a main storage is presented. A plurality of queue sets are provided in the main storage with at least one or more sets being dedicated for input and output. The queues can share access to a plurality of devices in the network across a plurality of communication stacks. Various network resources are mapped to the queues in order to facilitate resource allocation and dynamic configuration by providing initialization of a plurality of configuration parameters. In this way dynamic expanding and contracting of the number of queues in each set as dictated by traffic patterns and feedback indicators is provided.

Abstract: A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.

Abstract: A system and method of increasing the efficiency of a data processing system by alternately streaming portions of a large block of data from a large memory area into two memory banks within a smaller memory area using consecutive DMA transactions. Each streaming DMA transaction is entered in a DMA transaction queue and once it becomes active, transfers a block of data, the same size as one of the two memory banks, into one of the memory banks, after which it becomes inactive and is re-entered in the queue. When the streaming DMA transaction becomes active again, it switches to a different memory bank address and continues in the large data block where it stopped last time it was active. The streaming DMA transaction continues to be circulated in the queue until a total number of transaction iterations is reached, at which point the streaming DMA transaction is complete and is removed from the queue.

Abstract: A static random access memory device used in a system having a data clock includes a recirculating counter producing a pair of clocking signals and n data latches each connected to a source of data chunks. Logic receiving a strobe signal, inverse strobe signal, and the clocking signals, successively latches serial data chunks into n data latches, respectively, such that a data chunk is latched one per each cycle of the data clock and so that every n data chunks form a group of parallel data. A delay circuit delaying certain ones of the data chunks latched into the input data latches long enough to permit all data chunks in a group to be transferred in parallel to further memory circuit, wherein the parallel transfer takes place once every n cycles of the data clock.

Abstract: An audio record/playback system is configured using a RAM containing PC buffers and a sound input/output board which is equipped with another RAM containing P buffers and R buffers as well as a digital audio circuit. At a playback mode, waveform sample data consisting of waveform samples are subjected to burst transfer using a PCI bus from the PC buffer to the P buffer in a first half duration of each sampling period with respect to one channel. In a second half duration, one of the waveform samples is transferred from the P buffer to the digital audio circuit, wherein it is subjected to digital audio processing. Thus, the waveform sample data are played back in response to prescribed timings synchronized with sampling periods. At a record mode, waveform sample data corresponding to sounds to be picked up are supplied to the digital audio circuit, from which they are transferred to the R buffer. Then, the waveform sample data are transferred to the PC buffer.

Abstract: In a digital system having a host, a controller device and at least one flash memory integrated circuit, a method and apparatus for storing location identification information regarding blocks of information within at least one of the flash memory integrated circuits wherein at least two buffers within the at least one of the flash memory integrated circuits are designated as primary and secondary buffers for storing the identification information in the primary buffer until the primary buffer is effectively full and storing additional identification information in the secondary buffer until it is effectively full, swapping buffer designation so that the primary buffer becomes the secondary buffer and the secondary buffer becomes the primary buffer, erasing the effectively-full buffer for re-use and in this manner, continuously swapping storage of identification information between the two buffers.

Abstract: A CPU has an execution unit for operating on data under instruction control. A cache and a buffer register are coupled in parallel to an input of the execution unit. The buffer register supplies an information item, such as data or an instruction, to the execution unit upon the cache having completed a refill process.

Abstract: A method and apparatus schedule transfer of information packets, each information packet switch inlet port being associated with a packet transfer scheduler for scheduling transfer of information packets. A cell is sorted into a first queue structure according to its information packet switch outlet port, and for each outlet port, according to its logical channel.

Abstract: Access to memory is facilitated by a cache memory access system that includes individual buffers for storing and processing data access commands asynchronously, while also assuring data coherency and avoiding deadlock. Data access commands are placed in discrete buffers, in dependence upon their type: read and write to and from a client process, fill from memory, and flush to memory. To maintain data coherency, the read and write commands are processed substantially sequentially. To optimize memory access, fills are processed as soon as they are submitted, and flushes may be given lower priority than fills. To avoid deadlock, fills are generated so as to be independent of all other commands. The use of discrete buffers for cache memory access is particularly well suited to pipeline processes.

Abstract: A data input/output means comprises memories, each having two banks for storing a volume of data good for predetermined cycled period in an own time slot allocated to it and a control means accesses a recording medium in an own time slot to read out a volume of data for the first predetermined cycle period and store it in the first bank of the date input/output means and also read out a volume of data for the next predetermined cycle period on the way of reading out said data for the first predetermined cycle period and store it in the second bank of said data input/output means before starting the data output from the first bank after the elapse of a predetermined period of time, the switching from said first bank to said second bank being so controlled as to take place at a predetermined timing.

Abstract: A microprocessor having a built-in DRAM performs following processes: data stored in the buffer 14a is transferred to the DRAM 16 through the internal bus 15 whose data transfer speed is higher than that of the system bus 13a, the transferring occurring when the number of data input operations by the bus interface unit 14 reaches a predetermined number “p”, and an operation result obtained by execution of the CPU 17 and then stored in the DRAM 16 is read through the internal bus 15 and then output to the system bus 13b.

Abstract: Video assets are fetched from a data storage device and buffered based on the video rate associated with the video assets. The arrival deadline for each buffer is tracked. As the contents of a buffer are consumed by the video decoder, the buffering plan is computed. The intent of the buffering plan is to maintain enough buffering in prefetched buffers to cover a data storage device underflow. The proper amount of buffering to cover an underflow is computed by subtracting both the arrival deadline and buffer time of the next buffer to be consumed from the arrival deadline of subsequent future buffers. This computation must be performed for each future buffer until the difference is greater than or equal to the maximum storage device underflow period. If the difference is less than the storage device underflow period, then a fetch of the buffer from the data storage device must be performed.

Abstract: A multiple logical FIFO system uses a single main register file to store payload data in association with link data so as to form one linked list data structure for each logical FIFO in the system. A write pointer register file stores one write pointer for each logical FIFO. A read pointer register file stores one read pointer for each logical FIFO. A free register identifier indicates a free register address at all times unless the overall system is full. The free register address corresponds to one free register within the main register file. In a first embodiment, the free register identifier is implemented using a priority encoder. In a second embodiment, the free register identifier is implemented using a conventional FIFO buffer. In a third embodiment, the free register identifier is implemented using one of the logical FIFO buffers stored in the main register file.

Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

Abstract: A universal serial bus (USB) device or host provides a universal serial bus (USB) controller with a direct memory access (DMA) mode. In a DMA mode, a universal serial bus (USB) transmit endpoint may be programmed for a direct memory access (DMA) transmit channel, or a universal serial bus (USB) receive endpoint may be programmed for a direct memory access (DMA) receive channel. For a USB device, a DMA transmit channel performs data transfer to a universal serial bus (USB) host, and a DMA receive channel handles data transfer from the USB host. For a USB host, a DMA transmit channel performs data transfer to the USB device, and a DMA receive channel handles data transfer from the USB device. A universal serial bus transmit protocol and a universal serial bus receive protocol for the DMA mode of the USB controller permit a maximum packet size of universal serial bus (USB) data to be programmed to a value greater than the physical size of a USB transmit or receive buffer of a USB transmit or receive endpoint.

Abstract: A virtual transmission system comprises a first and second virtual serial ports; a first transmission/reception buffer region set with the first virtual serial port as a write port and the second virtual serial port as a read out port; a second transmission/reception buffer region set with the first virtual serial port as a read out port and the second virtual serial port as a write port; and a control portion for writing data outputted from the first virtual serial port into the first transmission/reception buffer region, for outputting data written in the first transmission/reception buffer region to the second virtual serial port, for writing data outputted from the second virtual serial port into the second transmission/reception buffer region, and for outputting data written in the second virtual serial port to the first transmission/reception buffer region.

Abstract: The present invention is directed to a method and apparatus for managing data flow between a serial bus device which operates at a first data rate and a parallel port device which operates at a second data rate. A serial bus receiver receives data from the serial bus device at the first data rate. A buffer unit is coupled to the serial bus receiver and the parallel port device. The buffer unit stores the received data at the first data rate and transfers the stored data to the parallel port device at the second data rate.

Abstract: Apparatus and methods for matching data rates is useful for a receiver receiving real-time data over a medium. Implementations feature a process establishing a buffer in a receiver; receiving source data from a source having a nominal source data rate, the received source data arriving at an incoming data rate that differs from time-to-time from the nominal source data rate; filling the buffer with source data as it is received at the incoming data rate and emptying the buffer to provide data for consumption in real time at a consumption data rate; setting a rate-matching factor M, the factor M affecting the rate at which the buffer is emptied; and tracking the level of data in the buffer and resetting the value of M to increase the rate at which the buffer is emptied when the buffer fills above a target range, and resetting the value of M to decrease the rate at which the buffer is emptied when the buffer empties below a target range.

Abstract: A network device receives packets from a first network segment, time stamps the packets as they arrive, and transmits the packets to a second network segment. By time stamping packets as they arrive, stale packets can be identified and discarded. A stale packet is a packet that has been pending in the network device longer than an active timeout interval, which may be varied based on network traffic levels to conserve network bandwidth. Packets may also be discarded to conserve packet buffer memory in the network device. For example, when an incoming packet arrives and an output buffer in which the packet must be stored is full, the output buffer is scanned to identify and discard packets that have exceeded a minimum timeout interval, thereby allowing the incoming packet to be stored in the output buffer. Many network protocols initiate the retransmission of packets after a timeout interval has expired and an acknowledge packet has not been received.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.

Abstract: A Universal Serial Bus to parallel bus bridge includes a Universal Serial Bus port that receives a serial bit stream of data and commands in a Universal Serial Bus protocol from a USB host computer. A parallel bus port on the bridge includes parallel port registers and state machines coupled to a peripheral device. A USB controller core is coupled between the Universal Serial Bus port and the parallel bus port and converts data and commands between the Universal Serial Bus protocol and the parallel bus protocol. A sequencer is coupled between the USB controller core and the parallel bus port. A sequence of sequencer commands is loaded into memory in the USB bridge and used by the sequencer to perform a sequence of parallel port operations. The sequencer performs the commands autonomously without intervention from the USB host computer.

Abstract: An access control apparatus, method, and recording medium for storing a program, provides equal input/output (IO) opportunities to auxiliary memory units for all users by attaching priority information for each user to user-entered IO commands. The prioritized IO commands are stored in an IO queue corresponding to a particular one of the auxiliary memory units, and physical IO is performed on each of the auxiliary memory units in the sequence of priority information attached to the prioritized IO commands in each IO queue irrespective of who the entrant users are.

Abstract: A system for allocating shared memory resources among a plurality of queues and discarding incoming data as necessary. The shared memory resources are monitored to determine a number of available memory buffers in the shared memory. A threshold value is generated for each queue indicating a maximum amount of data to be stored in the associated queue. Threshold values are updated in response to changes in the number of available memory buffers.

Abstract: A method of dynamically changing draining priority in a first-in/first out (“FIFO”) device to prevent over-run errors is described. The method includes the steps of detecting data received in the FIFO, asserting a request to drain the FIFO, detecting when an amount of data received in the FIFO has reached a predetermined high watermark value, and asserting a higher priority request to drain the FIFO. The method further includes the steps of detecting when the amount of data received in the FIFO has fallen below the predetermined high watermark value, maintaining assertion of the higher priority request, detecting when the amount of data in the FIFO has fallen below a predetermined hysteresis value, and deasserting the higher priority request to drain the FIFO.

Abstract: A full duplex repeater for collision-free transmission of data packets between node of a local area network. The repeater includes a multiple of ports, a signal path for communicating data between the ports, and an arbitration mechanism. Each of the ports has an input and output buffer. The mechanism routes data through the repeater by activating each of the ports one port at a time, such as with a round robin algorithm, to transmit stored data from the input buffer of an activated port through the signal path to the other ports. The repeater has a congestion control mechanism that includes level indicators and preset high and low threshold levels for the input buffers and a flow control device. The flow control device monitors the level indicators to determine if the amount of data in a buffer exceeds the high threshold level.

Abstract: A multiple-user processing system exchanges data elements with a central memory by a request system managed by a management circuit. The system furthermore has available a buffer memory to regulate the flow of information from the central memory.

Abstract: A media server system and method for reducing the probability of data starvation or underflow in a media server system. The media server system preferably comprises a video server computer system which stores a plurality of encoded data streams, wherein the computer system is coupled through a SCSI (Small Computer Systems Interface) bus to one or more MPEG decoder blocks. The media server system thus utilizes a single control channel for multiple video channels. The present invention operates to fill the FIFO buffer of a channel to a higher level during startup, thus reducing the probability of data underflow. In one embodiment, the host computer or server begins data transmission prior to sending the “play” function or play command in order to pre-fill or pre-load the buffer. In another embodiment where the host server is not configured to pre-load the buffer prior to issuing the play command, the MPEG decoder block disables the FIFO buffer when the play command is received.

Abstract: Methods and arrangements are provided for a block decoder in the form of a single integrated circuit (IC) for use in a variety of data storage devices. The block decoder is configured to transfer streaming data from the storage medium to an external device, such as a host computer's processor, without introducing any significant overhead induced latency into the data transfer. This is accomplished by employing a purely hardware-based logic and substantially minimizing the amount of buffering of data that is required within the storage device. The resulting block decoder can be integrated into a single IC because the amount of buffering memory that is required can be economically fabricated using conventional logic fabrication processes, such as complementary metal oxide semiconductor (CMOS) processes.

Abstract: A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.

Abstract: The circular queue invention herein provides a mechanism and method for producers of fixed-size data items to deliver those items to consumers even under circumstances in which multiple producers and multiple consumers share the same queue. Any producer or consumer can be permitted to preempt any producer or consumer at any time without interfering with the correctness of the queue.

Abstract: The present invention provides a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit suspends operation of the stack cache and causes the spill control unit to store the valid data words in the slow memory unit or data cache unit. After the valid data in the stack cache are saved, the overflow/underflow unit equates the cache bottom pointer to the optop pointer.

Abstract: One embodiment of the present invention provides an apparatus for receiving data from a synchronous random access memory. This apparatus receives a stream of data along with a data clock signal from the synchronous random access memory. This stream of data is alternately clocked into a first memory register and a second memory register using the data clock signal. At the same time, data is alternately clocked from the first memory register into a first system register, and from the second memory register into a second system register using a slower-speed system clock. These data transfers are coordinated by a controller, which ensures that data transfers from the synchronous random access memory into the memory registers do not interfere with data transfers from the memory registers into the system registers.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The read and write controllers output status information corresponding to the reading or writing of a stored data frame in the receive buffer. The memory management unit includes a synchronization circuit, which arbitrates updates to the holding registers by the read and write controllers based on the asynchronously determined presence of at least one stored data frame.

Abstract: A plurality of transmitters are multiplexed to a hub through clocked serial links. Timing problems that may arise when switching between links are eliminated with a system including a group serial receiver for each link for performing serial to parallel conversion of data sent over the serial link, outputing a group clock signal based on the serial clock signal, outputing parallel data clocked by the group clock signal, and determining a data enable signal from the serial link. A select signal for determining the serial link being read by the hub selects the corresponding group clock, parallel data, and data enable. A load control clocks the selected parallel data into a first-in, first-out buffer using the selected group clock when the selected data enable is asserted. When the selected data enable is not asserted, the load control is held in reset and, hence, is insensitive to irregularities in the selected clock signal due to switching between links. Data is clocked from the buffer by a local clock.

Abstract: A protocol controller connected between a SCSI device and a DMA controller. The SCSI device is connected to the protocol controller with a first bus and the DMA controller is connected to the protocol controller with a second bus having a width less than a width of the first bus. The protocol controller communicates with the SCSI device so that it transfers data having a width equivalent to the width of the second bus. Other data concurrently transferred by the SCSI device over the first data bus is ignored and not transferred to the DMA controller.

Abstract: Method and apparatus for accelerating write operations logging write requests in a log structured cache and by expanding the log structured cache using a cache-extension disk region. The log structured cache include a cache memory region partitioned into one or more write cache segments and one or more redundancy-data (parity) cache segments. The cache-extension disk region is a portion of a disk array separate from a main disk region. The cache-extension disk region is also partitioned into segments and is used to extend the size of the log structured cache. The main disk region is instead managed in accordance with storage management techniques (e.g., RAID storage management). The write cache segment is partitioned into multiple write cache segments so that when one is full another can be used to handle new write requests. When one of these multiple write cache segments is filled, it is moved to the cache-extension disk region thereby freeing the write cache segment for reuse.

Abstract: In accordance with the preferred embodiment of the present invention, a first-in-first out queue includes a buffer for storing data. A write pointer indicates a next position for data to be written into the buffer from an external interface. An input pointer indicates a next position for data to be read out to processing circuitry. An output pointer indicates a next position for data which has been processed by the processing circuitry to be returned to the buffer. A read pointer indicates a next position for data to be read out of the buffer to the external interface.

Abstract: A display FIFO module is used in a DRAM interface. A low priority request and high priority request are both issued when the FIFO must receive new data or FIFO underrun will occur. This is determined by comparing the FIFO data level against a predetermined high threshold value. After a predetermined number of addresses have been latched by a DRAM controller sequencer to the DRAM for transferring data to the FIFO because of either the low or high priority request, or both, the display FIFO module reevaluates the FIFO data level to determine whether the FIFO data level is still below or is equal to either the low or high threshold value. If the FIFO data level is still below or equal to the low threshold value, the low priority request remains active; otherwise, the low priority request will be removed by the display FIFO module.

Abstract: A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.

Abstract: A network interface transmits data packets between a host computer and a network and includes a first in first out (FIFO) buffer memory with an adaptive transmit start point determined for each data packet. The network interface receives data packets from the host computer via a peripheral component interconnect (PCI) bus. A FIFO control determines the byte length of each data packet based on the header information contained in the first few received bytes of the packet. The FIFO control also measures a minimum fill time indicating the time necessary to fill the FIFO buffer memory with a predetermined minimum amount of data necessary before transmission by the FIFO buffer memory. The FIFO control calculates the time to fill the FIFO buffer memory with each packet based on the determined length and the measured minimum fill time. The time to empty the packet from the FIFO buffer memory is also calculated based upon the length of the packet and predetermined network transmission rates.

Abstract: A system for managing burst data transfers from a sending device to the buffer memory of a receiving device and for managing read operations upon the buffer memory after receiving data. In one arrangement, the system includes data management apparatus that is used in a tape storage device. The data management apparatus uses a Start of Burst pointer, a Current Position pointer and a Tape Mechanism pointer to simplify several functions. These functions include the determination of whether to enable a burst from a sending device and the determination of whether to perform a series of read operations upon the buffer memory. In addition, the Start of Burst pointer and the Current Position pointer are used to re-write a burst into the buffer memory if a previously received burst is determined to be invalid.

Abstract: A method in a symmetric multi-processor computer system for increasing database transaction log performance by pipelining transaction log buffers. The method includes the steps of inserting a log record into a log buffer stored in a volatile memory of the computer system. Next, the log buffer is queued for eventual delivery to a persistent storage device. Then the log buffer is dequeued from the queue set in the previous step. Following this, a transfer of the contents of the log buffer to the persistent storage device is initiated. A wait is imposed on the process for the completion of the transfer of the contents of the log buffer to the persistent storage device in order to guarantee that the contents are safely stored in the persistent storage device in the original serial order as received.

Abstract: The present invention provides an improved disc drive. In one embodiment of the present invention a disc drive capable of spinning a disc, which contains more than one type of data is disclosed. A first type of data is associated with a first speed, and a second type of data is associated with a second speed that is faster than the first speed. The disc drive includes a drive mechanism, which may spin the compact disc at the first and second speeds and retrieve data from the compact disc at either speed. The disc drive also includes an elastic buffer, which is in communication with the drive mechanism. The buffer receives data from the drive mechanism at a variable input data rate and outputs data at a variable output data rate. Whereby when the drive mechanism spins the compact disc at the second speed the buffer may receive the first type of data without causing the drive mechanism to slow down to the first speed, and the buffer may output the first type of data at the variable output data rate.