Abstract: According to the invention, systems, apparatus and methods are disclosed for throttling commands to a storage device is disclosed. This method comprises sending a write request to a disk, receiving a queue full signal from the disk if the disk queue is full, and responsive to receiving the queue full signal setting a throttle value.

Abstract: In one embodiment of the present invention, an output device sends a spurious data sample in place of a first data sample to be sent from a queue if the queue is in a state of underflow during which the first data sample is not available to be sent. The buffer is to store data samples for an isochronous data transmission. Circuitry skips the first data sample when the first data sample becomes available in the queue so that synchronization for subsequent data samples sent from the queue is preserved. In another embodiment of the present invention, an input device advances an input buffer pointer to point to a next location in a memory in response to receiving a data sample at a queue during a state of overflow. The input buffer pointer indicates a location in the memory to which a next data sample is to be sent from the queue. The queue stores data samples for an isochronous data transmission. By advancing the input buffer pointer, synchronization for subsequent data samples is preserved.

Abstract: An interface apparatus provides a connection between a host having an IEEE 1394 input/output port and a mass storage device having an ATA input/output port. A receive FIFO and a transmit FIFO within the interface apparatus operates to store small-size packets, or operates to store the buffer address of large-size packets, as the small and large size packets are respectively received from the host or transmitted to the host. In both the host receive and host transmit modes of operation of the interface apparatus, the small-size packets are found in the receive FIFO or the transmit FIFO, whereas the data content of large-size packets is stored in the buffer as the corresponding buffer address is stored in the receive FIFO or the transmit FIFO.

Abstract: A method and apparatus is presented providing high-performance lossless data compression implemented in hardware for improving network communications. A compression module useful in a switching platform is also presented capable of compressing data stored in buffer memory. Instructions for a compression task are assigned to the compression module by a microprocessor writing a control block to a queue in stored local memory. The control block informs the compression module of the size and location of the unprocessed data, as well as a location in the buffer memory for storing the processed data and the maximum allowed size for the compressed data. Using this technique, the microprocessor can limit the compression of data to those data streams allowing compression, to those segments that are susceptible to compression, and to those segments that are large enough to show a transmission speed improvement via compression.

Abstract: A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue.

Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: A recording/reproducing apparatus using an IC memory includes an IC memory to/from which writing/reading of an audio signal is performed; and a control circuit for controlling writing/reading of the audio signal to/from this IC memory, and its address, and for controlling, on writing and reading the audio signal to and from the IC memory, so that its address becomes ring-shaped, writing, of when a recording key is pressed, the audio signal from contiguous address to an area, within the IC memory where the writing, which has never been read is performed, and reading, of when a reproduction key is pressed, the audio signal from the head of an area within the IC memory where the writing, which has never been read, is performed.

Abstract: A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

Abstract: A controller for a memory partitioned into a plurality of banks and divided into addresses that are accessed by a plurality of row access strobe signals and a plurality of column access strobe signals. The controller generally comprising a queue state machine, a plurality of transaction state machines and an arbitor. The queue snare machine may be configured to allocate a plurality of memory commands received by the controller among a plurality transaction state machines. A first of the transaction state machines may be configured to issue a first strobe request to assert one among the row access strobe signals and the column access strobe signals in response to receiving a first of the memory commands. A second of the transaction state machines may be configured to issue a second strobe request to assert one among the row access strobe signals and the column access strobe signals in response to receiving a second of the memory commands.

Abstract: A network interface device and a method of transferring data between a host and a network medium employs transmit descriptors that do not contain transmit status information. Upon fetching a transmit data frame from a host system memory at a location pointed to by a transmit descriptor, the network interface device immediately generates an interrupt to the CPU to allow the CPU to re-use the buffers in which the data frame was stored. At the same time, the network interface device attempts transmissions of the data frame to the network medium. Transmit status information is kept in statistics counters on the network interface device.

Abstract: A communication interface is described to align at a destination data transmitted through different channels before that data is read out. The communication interface includes a receiver circuit that has a plurality of buffers. Each buffer is coupled to a corresponding channel to receive data therethrough. The communication interface also includes a control circuit, coupled to the plurality of buffers, to enable reading of data from the plurality of buffers when each of the plurality of buffers has received at least one unit of data.

Abstract: A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a plurality of paths that exchange data between neighboring places. The bifurcator circuit generally comprises a control FIFO, two subordinate FIFOs and a bifurcation path coupled to all three FIFOs. The bifurcator circuit further comprises a chain of data latches coupled to all three FIFOs at the bifurcation path. A data value carried in the control FIFO determines which of the subordinate FIFOs exchanges data with the control FIFO. Each place in the FIFOs contains a set reset flip-flop in which the state of each place is held by a single wire and stabilized by a keeper. A single transistor sets or resets the state of the place. The pulse that changes the state of the control flip-flops also makes the data latches momentarily transparent. The bifurcator circuit is generally capable of a branch or join operations.

Abstract: A method of deadlock-free, automatic configuration and reconfiguration of modules having a two- or multidimensional cell arrangement, in which a unit for controlling the configuration and reconfiguration manages a set of associated configurable elements, the set being a subset or the total set of all configurable elements, and the management takes place as follows: reconfiguration requests from the associated configurable elements are sent to the unit; the unit processes the requests; the unit processes the configuration data of the command sequence; and after the configuration data has been fully processed, new requests are accepted again, the configuration data still to be loaded of the existing previous requests being loaded from a buffer memory (FILMO) into the configurable elements until a new request occurs.

Abstract: A magnetic tape cartridge includes a non-volatile semiconductor memory storing either a portion of the same data as that to be written to the tape or at least control data sufficient to recover from a delaying tape drive operation or from a mechanical failure in the tape drive thereby permitting signaling to a central processing unit an assurance that the data transferring by the CPU will be correctly written onto the tape. The host data can be directly transferred to the cartridge memory if the cartridge memory is fast enough and large enough to handle the transfer. An intermediate high speed non-volatile memory in the drive is necessary if the cartridge memory is too slow to handle the direct transfer or too small to handle the data transferred by the CPU. The cartridge memory then will contain command data sufficient to control the transfer of the data from the non-volatile drive memory to the tape.

Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Abstract: A system and method for controlling peripheral devices wherein at least one command is written to a location in a system memory and a write pointer is advanced. A peripheral device then reads the at least one command from that location in memory, increments a read pointer and executes the at least one command.

Abstract: The present invention relates to a queuing system, implemented in the memory of a computer by the execution of a program element. The queuing system includes a queue with a plurality of memory slots, a write pointer and a read pointer. The write pointer permits to enqueue data elements in successive memory slots of the queue. The read pointer permits to dequeue data elements from the queue memory slots for processing, where these data elements are potentially non-dequeuable. Upon identifying a non-dequeuable data element in a particular memory slot of the queue, the read pointer is capable to skip over the particular memory slot and move on to a successive memory slot.

Abstract: Methods and system for a message resource pool with asynchronous and synchronous modes of operation. One or more buffers, descriptors, and message elements are allocated for a user. Each element is associated with one descriptor and at least one buffer. The allocation is performed by the message resource pool. The buffers and the descriptors are registered with a unit management function by the message resource pool. Control of an element and associated descriptor and at least one buffer is passed from the message resource pool to the user upon request by the user. The control of the element and associated descriptor and at least one buffer is returned from the user to the message resource pool once use of the element and associated descriptor and at least one buffer by the user has completed.

Abstract: An audio record/playback system is configured using a RAM containing PC buffers and a sound input/output board which is equipped with another RAM containing P buffers and R buffers as well as a digital audio circuit. At a playback mode, waveform sample data consisting of waveform samples are subjected to burst transfer using a PCI bus from the PC buffer to the P buffer in a first half duration of each sampling period with respect to one channel. In a second half duration, one of the waveform samples is transferred from the P buffer to the digital audio circuit, wherein it is subjected to digital audio processing. Thus, the waveform sample data are played back in response to prescribed timings synchronized with sampling periods. At a record mode, waveform sample data corresponding to sounds to be picked up are supplied to the digital audio circuit, from which they are transferred to the R buffer. Then, the waveform sample data are transferred to the PC buffer.

Abstract: A serial data routing device for use in routing serial data between a computer and a peripheral device. The data routing device includes a computer data converter which communicates data under the USB protocol with a computer and which converts data received from the computer into converted computer data. A peripheral data converter is also included which communicates data under the USB protocol with the peripheral device and which converts data received from the peripheral device into converted peripheral data. A data router is provided in communication with the computer data converter and the peripheral data converter and transfers converted computer data and converted peripheral data between them. It includes a data routing controller which controls the routing of the converted computer data and the converted peripheral data between the computer data converter and the peripheral data converter such that the computer and peripheral device operate as though directly connected by a USB bus.

Abstract: A method and apparatus is for buffering data cells in a queuing element is presented. Each queuing element includes a partitioned buffer, where the partitioned buffer includes a plurality of partitions. Each of the partitions stores data cells received by the queuing element. Storage of the data cells into the partitions is accomplished by using an array of logical queues. Each logical queue of the array of logical queues maps data cells corresponding to that logical queue to a particular partition of the plurality of partitions. More than one logical queue may map data cells to a particular partition. Each partition may include a reserved portion, where each logical queue that maps to the partition may map a portion of its data cells to the reserved portion. The resources of the reserved portion to which a logical queue maps data cells are reserved to that specific logical queue and cannot be utilized by other logical queues.

Abstract: A stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the steps of: 1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device; 2) receiving a signal in the controller from the I/O device at any time during the sending step, to terminate the transmission burst; 3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent; 4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and, 5) repeating the above steps until the stream of data is received in its entirety by the I/O device.

Abstract: A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

Abstract: According to one embodiment of the present invention a method of operating a data network loop having at least two nodes includes monitoring deletions in an adaptive elasticity first-in, first-out (FIFO) buffer in each node, identifying each adaptive elasticity FIFO buffer that is a deleter, the deleter being an adaptive elasticity FIFO buffer for which information is deleted more often than information is inserted, and reducing a deletion threshold for each adaptive elasticity FIFO buffer that is a deleter. According to another embodiment of the present invention a buffer includes an adaptive elasticity FIFO buffer and a control circuit operatively configured to monitor deletions in the adaptive elasticity FIFO buffer, determine if the adaptive elasticity FIFO buffer is a deleter, and reduce a deletion threshold for the adaptive elasticity FIFO buffer if the adaptive elasticity FIFO buffer is a deleter.

Abstract: A method for recording data about internal and external messages in a software system which is, in particular, part of a digital telecommunications switching center. Within a software system which, as a rule, comprises a number of components, the components interchange internal messages with one another and/or receive/transmit external messages to and from the outside world via an interface. Such messages are registered at so-called trace points (TP1, . . . , TPn) defined in the software system, and are transmitted without any delay to a FIFO buffer store (ZS), without any acknowledgment from the receiver, and are stored there until they are read after a request from a data-processing system (PC), which is connected to the software system, for the purpose of processing them further.

Abstract: Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

Abstract: A need to store data between a producing stage and a consuming stage commonly arises in digital processing applications. However, factors such as fabrication process limitations and circuit area constraints may restrict the amount of available storage. A novel method and apparatus for data buffering are disclosed which use less data storage than would be required by double buffering techniques.

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: A single contiguous memory buffer is disclosed having at least first and second memory spaces in the memory buffer each functioning as a FIFO. When operating the memory buffer in a first mode, the first memory space functions as an input structure for loading of the one or more words, and the second memory space functions as an output structure for unloading of the one or more words. When operating the memory buffer in a second mode, the first memory space functions as the output structure for unloading of the one or more words, and the second memory space functions as the input structure for loading of the one or more words. A flip signal is used to toggle between the first and second modes to operate the first and second memory spaces. The respective sizes of the memory spaces vary dynamically according to whether the buffer memory is operating in the first mode or the second mode.

Abstract: A computer system having bus controller operating code stored in a non operating system managed, extended portion of system memory. In one example, the operating code is executed by a bus controller for a computer bus conforming to the Universal Serial Bus (USB) specification. In one example, the bus controller operating code is stored in a portion of system memory that is located above the top system memory address reported to the operating system, thereby hiding the stored code from the operating system. In one example, the bus controller operating code is constructed during the startup of the computer system with a code construction routine. Storing bus controller operating code in a non operating system managed, extended portion of system memory provides a computer system greater flexibility in system memory usage.

Abstract: A Universal Serial Bus to parallel bus bridge includes a Universal Serial Bus port that receives a serial bit stream of data and commands in a Universal Serial Bus protocol from a USB host computer. A parallel bus port on the bridge includes parallel port registers and state machines coupled to a peripheral device. A USB controller core is coupled between the Universal Serial Bus port and the parallel bus port and converts data and commands between the Universal Serial Bus protocol and the parallel bus protocol. A sequencer is coupled between the USB controller core and the parallel bus port. A sequence of sequencer commands is loaded into memory in the USB bridge and used by the sequencer to perform a sequence of parallel port operations. The sequencer performs the commands autonomously without intervention from the USB host computer.

Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: A system for handling write requests is described. The system uses two queues for storing posted write requests. When a posted write error results, software handles the posted write error using information stored in a first queue of the two queues. The write request producing the posted write error is cleared from the second queue which continues to handle physical packets containing write requests.

Abstract: A first-in first-out (FIFO) memory device includes a plurality of memory locations having sequential binary addresses, a write address pointer for sequentially accessing the memory locations to write data therein, and a read address pointer for sequentially accessing the memory locations for reading data therefrom. The method and apparatus add an inverted write binary address of the write address pointer to a read binary address of the read address pointer, add one, and discard the most significant bit (MSB) to define the number of empty memory locations.

Abstract: A method of insuring continuous processing of messages from a Work FIFO in a message passing interface between a requesting module and a receiving module. Each module has access to two queues in the message passing interface, and each queue has a Work FIFO for containing message frames to be processed and a Free FIFO for containing empty message frames. The method includes a step of monitoring the number of free messages in the Free FIFO of the receiving module. When that number falls below a selectable early warning level, the receiving module is alerted. The receiving module then sends an early warning level signal to the requesting module, and additional free messages are posted to the Free FIFO of the receiving module. This posting of additional free messages allows the continued processing, by the receiving module, of messages from the receiving module work FIFO.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: A system and method of buffering data of a wireless communication system. The system and method maintain synchronization, end-to-end signaling and coding overhead bits needed to encapsulate data frames sent over wireless media. Additionally, the system and method compensate for transmitting and receiving clock variations. In one embodiment, the system uses framing of data with preamble, stuffing and signaling bits transmitted synchronously at a high data rate in the Industrial, Scientific and Medical (ISM) bands.

Abstract: One embodiment of the present invention provides a method for synchronizing a data signal and a data strobe signal received from a random access memory. The method operates by initiating a read operation by sending a target address to the random access memory. Next, the method receives a data signal from the random access memory containing data retrieved from the target address. This data signal is passed through an input driver into a register. by asserting an enable signal on the input driver. This enable signal passes through a first programmable delay circuit that has been programmed with a first delay value before feeding into the input driver. At the same time, the method receives a data strobe signal from the random access memory. This data strobe signal is passed through a second programmable delay circuit that has been programmed with a second delay value and is then used to latch the data signal into the register.

Abstract: A digital signal processing system has a control processor, a signal processor, and a plurality of memories. A signal processor carries out signal processing under control of the control processor. A connecting device connects each of the memories selectively to one of the control processor and the signal processor in response to an instruction from the control processor.

Abstract: A serial communication circuit sends or receives a large amount of data speedily. A buffer 2a is connected to a serial interface circuit 1a, and a buffer 2b is connected to a serial interface circuit 1b. One end of a switch 4 is connected to the serial interface circuit 1a or the serial interface circuit 1b, and another end to a serial port 3. Switching the switch 4 sequentially to the serial interface circuit 1a and to the serial interface circuit 1b makes it possible to use the two buffers for sending data to, or receiving data from, one serial port 3.

Abstract: An output FIFO data transfer control device can comprise a geometric arithmetic core including one integer processing unit or IPU and a plurality of floating-point processing units or FPUs. Each processing unit includes an intermediate buffer or data output buffer for storing a data on an arithmetic result. When an instruction of data transfer from at least one of the plurality of processing units to one output FIFO is issued, a write/read pointer generating unit generates a write pointer identifying a specific location where data on an arithmetic result associated with the instruction is to be stored in the intermediate buffer of at least one of the plurality of processing units. The write/read pointer generating unit also generates a read pointer identifying a specific location where data is to be read out of the intermediate buffer of at least one of the plurality of processing units.

Abstract: A digital video network interface for transferring isochronous video data over an asynchronous local area network, including an isochronous interface for transmitting digital video data isochronously, a memory comprising first and second buffers for storing the isochronous video data, a network interface for transmitting video data from either the first or second buffers over the asynchronous local area network, and a memory buffer manager for controlling the output of the video data over the asynchronous local area network and for controlling the input/output of video data into/from the first or second buffers, wherein, when either the first or second buffers is filled with video data, the memory buffer manager shifts the input of data into an empty buffer and begins outputting video data to the asynchronous local area network from a filled buffer, upon receiving access to the local area network.

Abstract: A device and associated methods for the storage and retrieval of data elements in a buffer circuit include each data element being transmitted to the buffer circuit through a transmission bus and a bus interface. A data element is stored in a memory when a first register is not empty. Additionally, when the first register is not empty, a data element is also stored in an additional register directly accessible by a decoding interface. The time of access to the data elements in the buffer circuit may be reduced.

Abstract: A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: The data processor contains a memory and a data prefetch unit. The data prefetch unit contains a respective FIFO queue for storing prefetched data from each of a number of address streams respectively. The data prefetch unit uses programmable information to generate addresses from a plurality of address streams and prefetches data from addresses successively addressed by a present address for the data stream in response to progress of execution of a program by the processor. The processor has an instruction which causes the data prefetch unit to extract an oldest data from the FIFO queue for an address stream and which causes the data processor to use the oldest data in the manner of operand data of the instruction.

Abstract: A method and apparatus is presented for combining multiple data elements to produce resultant data elements, where the data elements used for combination are reused after being loaded into memory on an integrated circuit. The apparatus includes a memory, where the memory stores a plurality of lines of data. The apparatus further includes a circular line buffer operably coupled to the memory, where the circular line buffer stores a plurality of line elements from a portion of the plurality of lines of data. A read addressing block operably coupled to the circular line buffer generates a number of read pointers corresponding to the circular line buffer. Each of the read pointers is used to address the circular line buffer to retrieve one of the data elements from a different line stored in the circular line buffer. A combination block combines the line elements selected by the read pointers to produce a result element.

Abstract: Device and method for controlling a PCI ethernet in data transmission between a host computer and various media, is disclosed, the method including the steps of (1) storing data to be transmitted in a memory in succession until an amount of the data becomes greater than a threshold value when the data is transmitted in succession, (2) keeping the data stored in the memory as they are and storing data in the memory again starting from data which is not stored in the memory yet if an underrun occurs in the middle of data transmission and storing data in the memory again from beginning of the data if an error other than the underrun is occurred, and (3) determining completion of transmission of one full packet of data if no error is occurred, whereby shortening a time period required for transmission of data from a host computer to various media.

Abstract: One embodiment of the present invention provides an apparatus for receiving data from a synchronous random access memory. This apparatus receives a stream of data along with a data clock signal from the synchronous random access memory. This stream of data is alternately clocked into a first memory register and a second memory register using the data clock signal. At the same time, data is alternately clocked from the first memory register into a first system register, and from the second memory register into a second system register using a slower-speed system clock. These data transfers are coordinated by a controller, which ensures that data transfers from the synchronous random access memory into the memory registers do not interfere with data transfers from the memory registers into the system registers.

Abstract: A circuit for a use in a control system of a peripheral device that is dedicated to tasks related to communication with a host computer via a universal serial bus (USB). The invention affords a USB dedicated circuit that is configured to allow a host computer to recognize and enumerate a device as a USB configured device without the use of the device's micro-controller. In another aspect of the invention a USB dedicated circuit that is configured to perform other USB related tasks in conjunction with the device's micro-controller in a more efficient manner than a device operating solely with a micro-controller.

Abstract: A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between adjacent data blocks. The FIFO buffer has a read-pointer address register and a write-pointer address register and a bank of write-capture registers including at least a first pair and a second pair. The first pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a first data block written to the FIFO buffer register while the second pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a second data block written to the FIFO buffer. The first pair and second pair alternate in capturing and saving beginning and ending addresses of a plurality of data blocks written to the FIFO buffer.