Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

Abstract: Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.

Abstract: The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

Abstract: A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail FIFO and output the stored data at a memory output. A multiplexer is included having first and second multiplexer inputs coupled to the tail FIFO and the memory, respectively. The multiplexer has a control input to select one of the multiplexer inputs to coupled to a multiplexer output. A head FIFO memory receives data from the multiplexer output, and outputs the data on an output data path. A controller is operable to transfer one or more blocks data having a selected block size from the tail FIFO to the memory and from the memory to the head FIFO, to achieve a selected efficiency level.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: A system and method is disclosed for preventing the loss of event messages due to message buffer overruns. A fixed vendor-specific buffer pool is loaded with log messages by firmware in an adapter. A service application periodically polls a device driver for messages in the buffer pool. The device driver responds with the number of messages stored in the buffer pool and the total number of buffers in the buffer pool. The service application then issues “get next message” requests to receive the stored messages. Once the buffer pool has been emptied, the service application writes the messages to a disk file. The service application then computes a percent utilization of the buffer pool, and if the percent utilization exceeds a predetermined threshold, an algorithm is employed for increasing the polling frequency. If the percent utilization is below the threshold, an algorithm is employed for decreasing the polling frequency.

Abstract: A recording method for improving interrupted interferences, for use in a recording apparatus. First, a buffer is allocated, and then, the size of the buffer is checked. If the size of the buffer is smaller than a minimum recording segment, an alternative buffer is allocated; otherwise, data is recorded to the buffer. Then the data is recorded to the alternative buffer, the data in the alternative buffer is interpolated to the buffer.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. In one embodiment a non-volatile synchronous memory device includes an array of memory cells arranged in a plurality of addressable banks. A bank buffer circuit is coupled to each of the banks. Each of the buffers can store data from a row of memory cells contained in a corresponding bank. A method of operating a synchronous flash memory includes storing instruction code in each array block and copying the instruction code from a first array block to a buffer circuit, during a write operation, so that the instruction code can be read from the buffer circuit during the write operation.

Abstract: The present invention comprises a dual bank FIFO memory buffer operable to buffer read data from memory and thereby compensate for specific timing problems in certain computerized systems. One embodiment of the invention includes a dual bank FIFO that comprises a first bank of memory elements operable to buffer memory data and a second bank of memory elements operable to buffer memory data. Write control address logic is operable to store selected memory data in memory elements with selected addresses within a bank of memory elements, and write control timing logic is operable to selectively grant write access to the banks of memory elements at predetermined time. Also, read control logic operable to read data stored in the first and second banks.

Abstract: A control system includes a nonvolatile memory chip and a controller. The controller transfers a group of data from exterior to the nonvolatile memory chip based on the capacity of the nonvolatile memory, and enables the programming of the transferred data in the nonvolatile memory chip while transferring a new group of data. When transferring the group of data to the memory chip, the controller determines whether all the data are transferred from the exterior to the controller, and, if the all the data are transferred to the controller, transfers the group of data to the memory chip. Also, the controller controls the period of the data programming according to the capacity of the nonvolatile memory. Thus, data transfer and program operations are performed at the same time regardless of the memory capacity.

Abstract: An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.

Abstract: A method of transferring at least two data streams in a medical device is provided. First data stream data is collected into a first intermediate register. Additional data stream data is collected into an additional intermediate register. First intermediate register contents are stored in at least one first output register. Systems and devices for using the method are also provided.

Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.

Abstract: A data transfer control device using USB (a first bus), the end of a data phase (data transport: transfer of all the data) during an OUT transaction is determined on condition that data transmission (DMA transfer) through EBUS (a second bus) has ended, and the end of a data phase during an IN transaction is determined on condition that data reception through EBUS has ended and also an Empty signal has gone active, indicating that a data storage area has become empty. A counter that counts the data size is provided on the EBUS side. If data reception through EBUS ends and the size of data remaining in the data storage area is less than the maximum packet size, a short packet in the data storage area is transmitted automatically through USB and an interrupt is used to notify the firmware of the presence of the short packet.

Abstract: An image processing apparatus, method and computer readable recording medium provided with a primary memory device and a secondary memory device both having image data memorized therein, in which said image data are input to said primary memory device, and including an external input data amount acquisition device acquiring the amount of said image data input to said primary memory device; an internal output data amount acquisition device acquiring the amount of said image data output from said primary memory device and input to said secondary memory device; a first difference data amount calculation device subtracting the amount of the data acquired by said internal output data amount acquisition device from the amount of the data acquired by said external input data amount acquisition device, and calculating first difference data amount by the subtraction; a memory access control device practicing the inputting and outputting of said image data with time sharing in said primary memory device, comparing said

Abstract: A system for prefetching information from a computer storage includes a central processing unit operable to transmit to a transfer bus a memory transfer request containing a desired memory address. The system also includes a system controller operable to receive the memory transfer request from the transfer bus and to retrieve a prefetch block of data from the computer storage in response to determining that a stream buffer local to the system controller does not contain a copy of data stored at the desired memory address. The system controller is further operable to retrieve the data from the stream buffer and communicate the data to the central processing unit in response to determining that the stream buffer contains a copy of the data stored at the desired memory address.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: An apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system. The apparatus includes a data buffer and a control unit. The data buffer includes a first plurality of storage locations each corresponding to one of a plurality of tag values. The data buffer may receive a plurality of data packets associated with the graphics transactions. The data buffer may also store the data packets in the storage locations according to tag values. The control unit includes a storage unit having a second plurality of locations. Each of the locations in the storage unit corresponds to one of the tag values and may provide an indication of whether a given data packet has been stored in the data buffer. The control unit may further determine an order in which the plurality of data packets is read from the data buffer.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. In one embodiment a non-volatile synchronous memory device includes an array of memory cells arranged in a plurality of addressable banks. A bank buffer circuit is coupled to each of the banks. Each of the buffers can store data from a row of memory cells contained in a corresponding bank. A method of operating a synchronous flash memory includes storing instruction code in each array block and copying the instruction code from a first array block to a buffer circuit, during a write operation, so that the instruction code can be read from the buffer circuit during the write operation.

Abstract: An integrated data controller that utilizes a first-in first-out (FIFO) management system that compensates for the unpredictable nature of latency associated with requesting data from memory and enables the timing of data requests to be determined based on the number of pending requests and the amount of data currently residing in the buffer. The FIFO management system includes a FIFO controller and a FIFO buffer that monitor a credit value and a trigger value to determine when to make data request bursts upon a memory unit. The trigger value is an indication of whether there is a sufficient amount of free space for it to be beneficial to make a data request burst and the credit value is a number that indicates the number of a data blocks that should be requested in the data request burst.

Abstract: A direct memory access (DMA) first-in-first-out (FIFO) buffer includes two FIFO devices connected in parallel. An output multiplexer is controlled by a controller to pass to its output data provided by a selected one of the FIFO devices. Data is clocked into one FIFO device until it is full, after which data may be written from it. When data is written from a FIFO device, the FIFO device is emptied before data is again read into it. Using this arrangement, data can be read into one FIFO device while data is written from the other FIFO device.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: Systems and methods to regulate real-time data capture rates to match processor-bounded data consumption operations are described. In one aspect, a computer system is connected to a data source. A first transition time is determined for the data source to change from a first mode to a second mode. A second transition time is determined for the data source to change from the second mode to the first mode. Based on the first and second transition times, the data source is set into respective ones of the first and second modes. This is performed such that real-time capture of data from the data source is regulated by the computer system to substantially match processor-bound data consumption rates of an application consuming the data.

Abstract: A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART.

Abstract: A device for interfacing asynchronous data, and more particularly, a device for interfacing asynchronous data using a first-in-first-out (FIFO) for preventing cutoff in data transfer by transferring the asynchronous data in accordance with a data transfer information signal while best satisfying a transfer request from a host between two devices that transfer the bi-directional asynchronous data. The provided device prevents control problems caused by the asynchronous data, so that the selected data is precisely and stably transferred even if the transfer speed is increased to equal that of an inner system clock. In addition, the output speed of a flag signal is faster than that of an existing method in which read and write addresses are compared, so that the remaining amount of data in the FIFO is precisely measured. As a result, asynchronous data is stably interfaced at a high speed.

Abstract: Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Abstract: A DMA transfer device has stream inputting means for receiving an encoded first stream; first stream storing means for storing the first stream; a main storage unit which stores the stream of said first stream storing means; first DMA transfer executing means for executing a first DMA transfer from said first stream storing means to said main storage unit; first DMA transfer controlling means for controlling said first DMA transfer executing means on the basis of an amount of data which are stored in said first stream storing means or a free capacity; a processing unit which produces a second stream from the first stream that is read out from said main storage unit, and which writes the second stream into said main storage unit; second stream storing means for storing the second stream of said main storage unit; second DMA transfer executing means for executing a second DMA transfer from said main storage unit to said second stream storing means; and second DMA transfer controlling means for controlling said

Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

Abstract: A method for managing a memory pool containing memory blocks between a producer thread and a consumer thread running in parallel within a process is disclosed. The method places free memory blocks in a first group in the memory pool and allocates on demand a memory block from the first group to the producer thread. The allocated memory block is shared between the producer thread and the consumer thread. Once the allocated memory block is no longer required, the consumer thread deallocates the allocated memory block by placing the deallocated memory block in a second group of the memory pool. Deallocated memory blocks in the second group are moved to a third group only when the third group is empty. Memory blocks in the third group are moved to the first group only when the third group is non-empty. A locking mechanism is not required in such a multi-threaded environment.

Abstract: An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: The present invention provides a throttling system that can throttle incoming requests to a server that includes a variable sized buffer for holding incoming calls prior to processing by the server. The number of requests that are held in a queue by the buffer can be dependent on the overload status of the server. If the server is not overloaded, the number of requests that are held in the buffer can be large, such as the full capacity of the buffer. Alternatively, if the server is overloaded for a predetermined amount of time, then the number of requests that are held in the buffer can be decreased, such as to only a portion of the full capacity of the buffer. Any requests that arrive at the buffer once the buffer is at its capacity can be discarded or blocked. Accordingly, a reduction of the buffer size in a overloaded state results in a superior delay performance without increased request blocking of the processor.

Abstract: A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.

Abstract: A USB device controller is applied to a peripheral device that performs data communications with a host by using a transmission endpoint and a reception endpoint via a USB interface. Herein, a USB endpoint controller performs data transmission and data reception by using the reduced number of memories, which contribute to downsizing of the circuit scale of the USB device controller. The USB endpoint controller contains a transmission control block, a reception control block and a buffer switch control block as well as the memories. The buffer switch control block controls allocation of the memories to a transmission endpoint and a reception endpoint respectively in response to a type of a token issued from the host. In response to an OUT token, the data transmission is performed on the transmission endpoint that actualizes a double buffer configuration while the reception endpoint is also available in data reception by a single buffer configuration.

Abstract: A motion pictures sending apparatus has a camera interface for receiving an image signal from a camera, a frame conversion unit for carrying out coordinates conversion on the received image signal and generating image data, a memory for storing the image data, an image processing unit for processing the image data from the memory and providing processed data, an output interface for transferring the processed data to a communication interface unit, and a memory control unit for stopping the updating of image data to the memory in response to an input signal. When required, the apparatus keeps the same image in the memory and continuously sends the image so that the quality and clarity of the sent image may gradually improve.

Abstract: A video game system includes a game program executing system executing a game program and one or more controllers supplying user inputs to the game program executing system. An interface between the controllers and the game program executing system is programmable to periodically poll the controller without involvement of the game program executing system.

Abstract: When users simultaneously play the same game with interconnected game machines, processing delays would conventionally cause inconsistencies in game content between different game machines. To solve this problem, the game machines are not synchronized with one another, but each game machine outputs operation key status data representing the state of a set of number of operation controls to the other game machines in accordance with predetermined data communication timing. A received FIFO data buffer in each game machine, sequentially stores operation key status data received from the other game machines. Only valid operation control status data is transferred to an operation data buffer for use in game processing. Inconsistencies in game content between different game machines are prevented through software-based synchronization which does not require hardware-based synchronization.

Abstract: A control unit has a main microprocessor and processor interface to a bus transceiving unit, which has at least one transmit memory, one receive memory and one bus controller. Devices are provided by which the data content of the transmit memory and/or of the receive memory is reset to a defined status after each output and/or reading-in of the data stored in either memory, and before the main microprocessor outputs and/or reads in new data.

Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Abstract: A circular buffer for use in a telecommunications system is described as well as a method of operating the same in which data is protected during wraparound procedures. In the operation of the circular buffer at least four reference values are stored to enable address calculations: a first reference value representative of a begin address of the circular buffer; a second reference value representative of an end address of the circular buffer; a third reference value representative of a current write address of the circular buffer; and a fourth reference value representative of a current read address of the circular buffer. The cyclic state of the buffer is also monitored in order to protect the data after a wraparound or when the buffer is full. The buffer is able to accommodate multirate data arrival.

Abstract: A system, method and article of manufacture are provided for storing an incoming datagram in a switch matrix of a switch fabric. The switch matrix has a pair of buffers with each buffer having a pair of portions. Data of a datagram is received and the buffer portions are sequentially filled with the data. Periodically, transfer of data is allowed from the buffers into the switch matrix. At each period where transfer of data is allowed in the sequence that the buffer portions were filled, the data in one of the buffer portions may be transferred into the switch matrix.

Abstract: A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

Abstract: There is provided a data transfer apparatus for transferring data from a main memory coupled to a main bus to a local memory coupled to a local bus. The data transfer apparatus includes: a first-in-first-out buffer having a data region for storing one or more words of CPU access data which is accessed by a CPU coupled to the main bus, and a plurality of words of DMA access data which is accessed by a DMA controller coupled to the main bus; and a controller for controlling the first-in-first-out buffer. When the local bus is available, the controller controls the first-in-first-out buffer so as to consecutively transfer the one or more words of CPU access data stored in the data region to the local memory, and to burst transfer the plurality of words of DMA access data stored in the data region to the local memory.

Abstract: A first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupled to the first FIFO (A) and an output terminal of the second multiplexer (14) is coupled to the second FIFO (B). In response to the data being one data type, write control logic (90, 95, 100) is used to cause the data to be alternately written to the first and second FIFOs (A, B). In response to the data being a second data type, write control logic (90, 95, 100) is used to cause the data to be simultaneously written to the first and second FIFOs (A, B).

Abstract: The present invention provides an improved method and system for link detection and handling. The method includes detecting one of the plurality of link sectors; generating an interrupt signal; determining a buffer method selection; buffering the plurality of data sectors only, if a link skip buffer method is selected; and buffering the plurality of data sectors and the plurality of link sectors, except for a link block, and allocating a sector in a buffer for the link block, if a link buffer method is selected. The present invention provides a hardware approach to link sector detection and handling. Instead of passing the data to a system software prior to link sector detection, the method and system in accordance with the present invention performs the link sector detection in the controller hardware. When the controller detects the link sectors, it automatically either skips or buffers the link sectors depending upon the configuration of the controller.

Abstract: An architecture for data retrieval from a plurality of coupling queues. At least first and second data queues are provided for receiving data thereinto. The data is read from the at least first and second data queues with reading logic, the reading logic reading the data according to a predetermined queue selection algorithm. The data read from by reading logic and forwarded to an output queue.