Abstract: The present invention relates to a communication device using three-step communication buffers which temporarily stores received data or data to be transmitted between a serial communication device and a central processing unit. To prevent an error resulted from that the serial communication device and the central processing unit simultaneously access to the communication buffer, the access to the communication buffer is allowed at different edges of the system clock signal, thereby having a time difference of the access.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: An a backpressure-type cell flow control for a square-grid expanded ATM switch achieving fair cell flow control between input port lines is disclosed. In a square-grid expanded switch, a backpressure controller generates a backpressure control signal when an amount of data stored in an output buffer exceeds a predetermined threshold, to avoid an overflow of the output buffer. When a backpressure control signal is generated by at least one of backpressure controllers belonging to a corresponding column, a common backpressure control signal is output to a plurality of input buffers storing data to be forwarded to an output port associated with the output buffer.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: In order to enable interfacing of a microprocessor (1) with a peripheral (3) consisting of a device operating according to high-speed communication specifications (for example, IEEE 1394), it is envisaged that the interface (4) should contain a dedicated memory (40) designed to smooth the delays in communication between the main memory (2) and the peripheral (3). The memory (40) has a trigger (10) that is programmable via software to start a communication when a fraction of the memory (40) or the entire memory (40) is full. When a multiple packet starts to be transferred, a signal is generated to alert the microprocessor (1) of the fact that a transfer is almost completed.

Abstract: A buffer circuit for rotating outstanding transactions. A buffer circuit includes a buffer and a command update circuit. The buffer may be configured to store packet commands that belong to a respective virtual channel of a plurality of virtual channels. The packets may be stored in the buffer to await transmission upon a peripheral bus. Once a given packet is selected for transmission, a peripheral bus cycle corresponding to the given packet command may be generated upon the peripheral bus. The command update circuit may be configured to generate a modified packet command in response to receiving a partial completion indication associated with the peripheral bus cycle. The command update circuit may also be configured to cause the modified packet command to be stored within the buffer.

Abstract: A buffer circuit for a peripheral interface circuit in an I/O node of a computer system. A buffer circuit includes a first buffer and a second buffer. The first buffer may be configured to store a plurality of selected packet commands within a plurality of storage locations. The second buffer is coupled to the first buffer and may be configured to store a plurality of index values. Each index value corresponds to one of the storage locations in the first buffer. The buffer circuit further includes a write logic circuit that is coupled between the first buffer and the second buffer. The write logic circuit may be configured to successively read each of the plurality of index values from the second buffer and to cause a selected packet command to be stored in each storage location corresponding to each of the plurality of index values within the first buffer.

Abstract: Autonomous retransmission of data packets onto a network from a Network Interface Card level upon command from a host processor is support. Efficient FIFO buffering in an ASIC is retained. Uses for autonomous retransmission include hardware and software testing and in network management.

Abstract: The present invention relates to a queuing system, implemented in the memory of a computer by the execution of a program element. The queuing system includes a queue with a plurality of memory slots, a write pointer and a read pointer. The write pointer permits to enqueue data elements in successive memory slots of the queue. The read pointer permits to dequeue data elements from the queue memory slots for processing, where these data elements are potentially non-dequeuable. Upon identifying a non-dequeuable data element in a particular memory slot of the queue, the read pointer is capable to skip over the particular memory slot and move on to a successive memory slot.

Abstract: A computer network is provided for handling ordered transactions between a chipset and a memory controller. The chipset provides an interface with a first bus segment and a second bus segment. The chipset may include logic to attach a destination code to ordered transactions transmitted from the chipset. The memory controller may also include logic to parse the destination code from ordered transactions and apply a fence with respect to a first queue and a second queue of the memory controller.

Abstract: The invention proposes an apparatus (and method) for transferring data between a first device (1) and a memory area of memory means (3a; F_REG) of a second device (3), the apparatus comprising buffer registers for temporarily storing the data (DATA) to be transferred and the address (ADDR) of the memory area to and/or from which the data are to be transferred, and a control means (EL, CTRL) for controlling said buffer registers, characterized by at least two groups of buffer registers ([DATA_REG1, ADD_REG1], [DATA_REG2, ADD_REG2]) for storing data and associated addresses transmitted in consecutive data transfer operations, and in that said control means (CTRL) is adapted to generate a control signal (ENABLE) for alternately switching between a first group of buffer registers ([DATA_REG1, ADD_REG1]) and a second group of buffer registers ([DATA_REG2, ADD_REG2]) after each of a respective one of consecutive data transfer operations.

Abstract: A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and response messages or transactions. In particular, instead of simply dedicating a portion of the system resources to requests and the remaining portion to responses, a minimum amount of resources are reserved for responses and a minimum amount for requests, while the remaining resources are dynamically shared between both types of messages. The method and architecture of the present invention allows for more efficient use of system resources, while avoiding deadlock conditions and ensuring a minimum service rate for requests.

Abstract: The invention relates to a buffer memory, method and a buffer controller for queue management usable in an ATM switch. An object of the invention is to achieve a high frequency throughput of data cells in the buffer memory. This object is achieved by using a buffer memory which is organized as 256*(424+8) SRAM-cells. The memory is used for holding ten queues, one for each incoming channel and two free-queues containing idle cells.

Abstract: An interface circuit transmits data via a serial interface to and from a processor. A first-in-first-out memory is disposed between the serial interface and the processor. A suitable method transmits data which are received and read into the memory serially bit by bit and are read out of it byte by byte by the processor, or, respectively, can be written byte by byte into the memory by the processor and can be transmitted from the memory bit by bit.

Abstract: Hardware Description Language (HDL) code is created for an interface controller so that logic requiring device-specific configuration refers to a parameter file. This set of parameters lets components in a bridge circuit provide support for the same configuration. In another aspect of the invention, a control circuit identifies isochronous endpoints and non-isochronous endpoints. A buffer is configured into a first FIFO mode for isochronous endpoints and configured into a second FIFO mode for non-isochronous endpoints.

Abstract: Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a system for transferring data between a host device and a storage medium includes a host interface that receives from a host device a command to transfer data between the host device and the storage medium, a buffer that temporarily stores data that is transferred between the host device and the storage medium, a first register that stores a value for tracking a number of data units that are transferred between the buffer and the storage medium, and a second register that stores a value for tracking a number of data units that are transferred between the host device and the buffer. A data unit is transferred between the buffer and the storage medium if the value in the first register is within a predetermined range. Similarly, a data unit is transferred between the buffer and the host device if the value in the second register is within a predetermined range.

Abstract: In a data processing system, the effective speed of transferring data packets between a data processing unit and various other devices with different performance characteristics is improved by a data transfer method and a packing and buffering device, thus offloading the data processing unit or the various devices. FIFO buffers provide intermediate storage of transfer data, and packing and unpacking modules ensure efficient use of bus widths that are different on the data processing side and the device side. Data packet transfer control is effected using a control and status module with a common byte counter, and a direct transfer is facilitated via a supplementary direct data path between the data processing unit and other devices.

Abstract: An apparatus for effectively and economically receiving packet by eliminating temporal memory and controller is disclosed. The apparatus includes; an inspection logic circuit for inspecting data units as soon as arrived in order to find error included in the packet and generating control signals according to a result of inspecting data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units are arrived; and a plurality of FIFO memories for receiving the data unit, storing the data unit in corresponding one of FIFO memories and deleting or completing to store data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the apparatus by eliminating a temporal memory and a memory controller for the temporal memory and can also reduce a processing time.

Abstract: A method for removing unwanted header information from a frame in a network is disclosed. It includes: storing beginning bytes of the frame in a first buffer and remaining bytes in a second buffer, where a size of the first buffer is smaller than the second buffer; determining that the unwanted header information is stored in the first buffer; copying bytes of the frame after the unwanted header information that are stored in the first buffer over the unwanted header information; reporting a number of bytes of the frame stored in the first buffer to be retrieved; and retrieving the reported number of bytes of the frame stored in the first buffer and the bytes of the frame stored in the second buffer. The copying of bytes occurs exclusively in the first buffer. Thus, removing the unwanted header information requires fewer processor cycles and minimizes latency in the packet receive process.

Abstract: A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein the first read latch signal does not change the pointer location of the read pointer. A dynamic random access memory (DRAM) is also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.

Abstract: A system and method for scheduling packet output according to a quality of service (QoS) action specification. A system is provided with a calendar queue with a plurality of bandwidth timeslots, wherein the bandwidth timeslots are organized into groups. A look-up logic circuitry inspects a group of bandwidth timeslots substantially simultaneously and determines from the group a first unoccupied bandwidth timeslot in which a current packet can be scheduled. The look-up logic circuitry also determines a first occupied bandwidth timeslot that contains a next packet to be transmitted.

Abstract: A bus interface to a split transaction computing bus having separate address and data portions is provided. The bus interface contains separate address and data interfaces for initiating and tracking out-of-order transactions on either or both of the address or data portions of the computing bus. The bus interface includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the computing bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources.

Abstract: An apparatus and method for transferring high speed asynchronous data using a DMA controller. By using a conventional Universal Serial Asynchronous Receiver Transmitter (USART) with a small buffer, high speed asynchronous data can be manipulated by the DMA controller by use by other applications, such as wireless communication applications. The wireless communication applications includes Global System for Mobile communications (GSM), Code Division Multiple Access (CDMA), or Personal Digital Cellular (PDC). These wireless communication applications utilize high asynchronous data rates that would require more expensive USART with additional buffer capacity. In the receive mode, the high speed asynchronous data shifted into a DMA FIFO buffer from the USART. The data is then flushed into a host memory, such as a protocol stack by the DMA controller once the FIFO is full or if a timer expires. The data in the protocol stack is then manipulated by the wireless communication application.

Abstract: Disclosed is method and apparatus (20) for improving the performance of a pipeline system in which a FIFO (24) is incorporated in the pipeline between an upstream processing module (22) and a downstream processing module (26), each of the modules (22, 26) having access to a common external memory (32), this being typical in many ASIC arrangements. The method commences with detecting when the FIFO (24) is substantially full and transferring commands from the upstream module (22) to the external memory (32). Commands received by the downstream module (26) from each of the FIFO (24) and the external memory (32) are interpreted to determine a source of following ones of the commands.

Abstract: A method is provided for avoiding data loss in a data packet switch which utilizes a circular data buffer. If the data is received at a faster rate than it is read out of the buffer the data read-out pointer is adjusted by incrementing it to skip, or drop, the next sample. If the data is received at a slower rate than it is read out of the buffer, then the read-out pointer is adjusted by decrementing it to repeat the previous sample. The method of controlling the buffer read-out pointer according to the present invention, is implemented in hardware thereby reducing system complexity and improving speed relative to prior art software solutions.

Abstract: In data transmission between a host device and a target device connected by a serial bus, when commands and data use the same register area, and only the transmission result of the data is to be returned, any command other than a data transmission command cannot be transmitted for a certain period because the receiving-side register becomes full. In this invention, when a response to a data transmission command from the host device is to be returned from the target device, the host device is notified of the situation of the data receiving buffer. The host device transmits a DUMMY command to the target device in accordance with the free buffer situation and transmits another command to the target device in accordance with the response from the target device. The target device sends a data retransmission request to the host device in accordance with the free buffer situation.

Abstract: The present invention is a shared buffer architecture that dynamically allocates buffer size to each of multiple sources depending on buffer pool utilization, estimated per-connection offered load, and the total number of connection established within a given class of service. When the buffer pool is almost empty, each source is allocated a large buffer space, proportional to its estimated offered load. When the buffer pool is more full each source is allocated a reduced buffer space, while maintaining the proportional weighting relationship. The invention keeps track of the amount of input per source and dynamically allocates a proportionate amount of buffer space in the buffer memory for that source. The dynamic allocation is made as a function of the fullness of the memory allocation for all sources. Additionally, thresholds are modulated dynamically as the number of established connections within a given class modulates, providing a predictive aspect to the system, with respect to congestion control.

Abstract: A flow of data (26) is regulated in a communication system (20). A data rate is established in each of a data source (24) and a data sink (28). The data (26) is transmitted by the data source (24) and written into a buffer (32) at the source data rate, then read from the buffer (32) and received by the data sink (28) at the sink data rate. The level (62) of data (26) in the buffer (32) is monitored, and a rate-control signal (74) is dispatched to either the data source (24) or sink (28) when it is determined the buffer data level (62) is decreasing or increasing while at a lower or upper data-level threshold (66, 68), respectively. One of the data rates is adjusted in response to a rate-control signal (74).

Abstract: An apparatus is described in which the locations of a buffer are used to store a plurality of control packets received in a node, wherein the plurality of control packets belong to a plurality of virtual channels. The number of locations assigned to each virtual channel may be dynamically allocated. The number of locations allocated to each virtual channel may be determined by an update circuit. Count values corresponding to the number of locations allocated to each virtual channel may then be stored within a programmable storage, such as a register, for example. The count values may be subsequently copied into a slave register and incremented and decremented as locations become available and notifications corresponding to the available locations are sent, respectively.

Abstract: System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Abstract: A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

Abstract: An FIFO data transfer control device includes an instruction analyzing portion for analyzing an instruction for data transfer to an FIFO storage device including a plurality of banks, and calculating an amount of data to be transferred; a data count portion for calculating, from the data amount calculated by the instruction analyzing portion, an amount of the data written in the bank being in an outputting state, and issuing a determination flag indicating whether the free space of the bank being in the outputting state satisfies predetermined conditions or not; and a full check portion for inhibiting processing of a next instruction until the determination flag sent from the data count portion or the full flag issued from the FIFO storage device is reset.

Abstract: A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

Abstract: A dynamic queuing system wherein a single memory is shared among a plurality of different queues. A single memory, termed a queue memory, is by ally shared by one or more queue. The queue memory is divided into a plurality of memory blocks that we initially empty. An empty list functions to track which memory blocks are empty and available for use in a queue. Each queue constructed utilizes one or more memory blocks. When a queue becomes full, an additional memory block is allocated to it. Conversely, as memory blocks of a queue are read, i.e. emptied, they are returned to the pool of empty memory blocks for use by other queued.

Abstract: A method and system for increasing read and write performance of flash-based storage systems, by using RAM buffers with multiple accesses. The increase of read and write performance of flash-based storage system is achieved by performing “from RAM” and “to RAM” transfer operations simultaneously. According to the preferred embodiment of the present invention, the invention provides a system for enabling simultaneous data transfer from a host interface to flash media and from flash media to a host interface. It also provides for a system for synchronizing memory-to-host and flash-to-memory transfers, during the host read operation. There is further provided a system of synchronizing host-to-memory and memory-to-flash transfers, during the host write operation.

Abstract: The present invention provides an ATAPI command receiving method in which the CPU 72 can quickly correspond to other processings without expending much time for capturing data, as well as it can be prevented that data which are being captured by the CPU should be destroyed. In this ATAPI command receiving method, when an ATAPI protocol control LSI 71 comprising a shared register storage area 711 (including a data FIFO 7112 for containing command packets) for receiving a command from the host computer via an ATA bus 2, and a buffer memory 712 which can be used as a RAM of a CPU 72 receives a command, shared register values (including a command packet value) are stored at a storage destination address in the buffer memory 712 which is designated by the CPU 72, when the data storage permission is given by the CPU 72.

Abstract: Apparatus and methods, and computer program products are disclosed that accepts time-stamped information and feeds that information to a buffered system that consumes the information. The invention accepts an initial interval of the time-stamped information and when a pre-fill limit is reached, starts consumption of the data. The pre-fill limit is determined by monitoring the time stamp on the data that is ready to be consumed and the time stamp of data that has just been accepted. The difference between these time stamps provides an interval that represents the amount of time related to the data associated with the time-stamped information. Once the interval exceeds a pre-fill limit, the invention allows the buffered time-stamped information to be consumed. As the time-stamped information is consumed, the invention monitors the interval (other embodiments use the time stamp of data that is in the process of being consumed, or data that has just been consumed).

Abstract: A processor architecture including a processor and local memory arrangement where the local memory may be accessed by the processor and other resources at substantially the same time. As a result, the processor may initiate a new or current process following a previous process without waiting for data or instructions from external resources. In addition, the loading of data for the next or subsequent process, the execution of a current process, and the extraction of results of a previous process can occur in parallel. Further, the processor may avoid memory load stall conditions because the processor does not have to access an external memory to execute the current process. In another embodiment, the local memory may be dynamically reallocated so that results from a previous process stored in the local memory may be accessed by the processor for a current process without accessing an external memory.

Abstract: A timing enhancement for a USB controller determines if a short data packet is present. If so, data is placed in a buffer. If the buffer is full, data is sent. If the buffer is not full, the system looks to see if more data is available, if so takes it, if not it sends whatever is available.

Abstract: A virtual channel buffer bypass in a computer system input/output node. A control unit of an input/output node for a computer system includes a buffer circuit configured to receive control commands. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. The buffer circuit may also be configured to determine whether each of the plurality of buffers is empty prior to storing a particular control command corresponding to a given one of the plurality of buffers. In addition, the buffer circuit may be configured to cause the particular control command to bypass the given one of the plurality of buffers in response to determining that each of the plurality of buffers is empty.

Abstract: A method for controlling a FIFO array. The method uses a write pointer to indicate a write address, a read pointer to indicate a read address, a flag to indicate the status of the write pointer and the read pointer, and a number of status parameters to indicate the status of the FIFO array. The FIFO array has M addresses, and a first address is one of the M addresses. When both the write pointer and the read pointer point to the first address of the FIFO array and a write data operation is performed, the flag is a first value and the write pointer points to the next address following the first address of the FIFO array. When both the read pointer and the write pointer point to the first address of the FIFO array and a read data operation is performed, the flag is a second value and the read pointer points to the next address following the first address of the FIFO array. Finally, status parameters are set. By these, the FIFO array is easily and effective controlled in various situations.

Abstract: A print data management system includes a memory to store print data; a controller to transfer the stored print data to a printer; and a user interface to indicate to a user a degree of occupation of the memory by the print data, the user interface including first and second distinct forms of indication respectively corresponding to a range of low occupation and a range of high occupation of the memory, the user interface further including a setting unit to variably set boundaries of at least one of the ranges of high and low occupations by the user.

Abstract: A recording/reproducing apparatus using an IC memory, comprising: an IC memory to/from which writing/reading of an audio signal is performed; and a control circuit for controlling writing/reading of the audio signal to/from this IC memory, and its address, and controlling, on writing and reading the audio signal to and from the IC memory, so that its address becomes ring-shaped, writing, when a recording key is pressed, the audio signal from an address contiguous to an area, within the IC memory, where the writing, which has never been read after the writing, is performed, and reading, when a reproduction key is pressed, the audio signal from the head of an area, within the IC memory, where the writing, which has never been read after the writing, is performed.

Abstract: The present invention provides for a virtual serial port (VSP) situated between a serial port in a mobile electronic device, applications that require a serial port connection handle, and other applications that require command-mode access to the serial port. Data-communication applications (e.g. web browsing, e-mail, etc.) connect to the serial port through the VSP. The VSP creates a virtual connection handle that is returned to the application. Command-mode requests (e.g., short messaging requests) are received by the hardware abstraction layer, translated into command-mode messages (e.g., AT commands) and placed in a queue. The VSP multiplexes the serial port between the currently-open data communication session (data-mode) and command-mode messages by periodically suspending the currently-open connection and processing one or more command-mode messages that are in the queue. A buffer continually stores incoming data while the data communication session is suspended.

Abstract: An output interface allows a user circuit to access data for multiple objects in an interleaved fashion. Status information is provided to guarantee data availability before each transfer sequence is started. An identifier is provided for each object. Each identifier, after data transfer has ended, may be subsequently reused to identify a different object. The interface provides the ability to retrieve all data in an object or to cancel the object before reaching the end and discarding the unretrieved data. The objects are provided to the appropriate processing mechanisms within the printer to implement a printing task. These objects correspond to images and text to be printed on a page. Object data is temporarily stored in limited data memory of the memory system and object headers are stored in header memory before transfer via the output interface. Each object to be printed has an object header and may, or may not, have associated object data.

Abstract: Incoming serial data which is received M bits at a time where M=N, N+1 or N−1 and N is greater than 1 is synchronized to a local clock by receiving a first M bits of data, storing the first M bits, receiving M additional bits, storing the M additional bits, repetitively receiving and storing until at least a predetermined number R of bits have been stored, where R=(M*X)+1 where X is an integer greater than one. When this occurs, the first R bits are output and any remaining S bits in excess of R are stored and additional groups of M bits added, with the process continuing until all of a packet has been received. With this arrangement, the R bits may be output at a rate which is a fraction of the serial bit rate.

Abstract: Disclosed are a system and method of transmitting and receiving data through a peripheral device coupled to a transmission medium. The peripheral device is coupled to a host processing system through a data bus. The peripheral device includes logic to discriminate among data cells based upon virtual channels and maintains a receive buffer for storing data cells for each virtual channel. When a buffer fills, the peripheral device transmits the data cells to a receive buffer queue associated with a virtual channel and maintained in the host processing system. The host processing system may also maintain a plurality of transmit buffer queues for storing data cells for transmission in virtual channels. The peripheral device may also comprise logic for scheduling data cells in the transmit buffer queues for transmission according a quality of service (QoS) associated with one or more virtual channels.

Abstract: To avoid a reduction in the efficiency of data transmission of a data processing device that conducts data communications using a serial bus that conforms to the IEEE 1394 Standards. The data processing device 1 has a calculator 9 and a comparator 8. The calculator 9 calculates the data volume of a response packet intended for reception that corresponds to a request packet intended for transmission when an attempt is made to transmit these packets, the comparator 8 compares the data volume of the response packet intended for reception and the empty volume of the receiving buffer 7, and when the empty volume of the receiving buffer 7 is smaller than the data volume of the response packet intended for reception, the packet transmitting device 3 does not transmits the request packet intended for transmission to the IEEE 1394 bus 6, and if the empty volume of the receiving buffer is too small and the response packet cannot be received, the request packet is not transmitted.

Abstract: A method and apparatus assists communication between a writer of a shared file and the reader of the shared file without requiring the use of a shared file. When the writer fills a buffer with information and provides a write commend to write the buffer to a shared file, the buffer is not written to a file. Instead, the pointer to the buffer is passed to the reader, and the writer may be suspended until the reader indicates it has read the file. Alternately, two buffers may be used, with the contents of the buffer used by the writer copied to a second buffer, allowing the writer to reuse the first buffer before the reader has completed reading the contents of the second buffer.