Abstract: A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as to the skew is distributed over multiple clock periods.

Abstract: Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional interference between the split units is prevented and stable remote copying is realized. SLPRs which are dedicated regions for the respective users are set inside the disk array device 10. Each SLPR is constituted by dividing various types of resources of ports, cache memories, logical units and the like, and cannot be accessed by an unauthorized host computer 1. Furthermore, a manager of one of the SLPRs likewise cannot refer to or alter the constructions of the other SLPRs. During remote copying, the amount of transfer within the unit time is detected for each of the SLPRs. If the amount of transfer within the unit time exceeds the maximum amount of transfer, a response to the host computer 1 from this SLPR is deliberately delayed, so that the inflow of data from the host computer 1 is restricted.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: Various embodiments of systems and methods for implementing a streaming I/O protocol are disclosed. In some embodiments, a method may involve: receiving a packet initiating a streaming write operation, where the packet indicates that the size of the streaming write is larger than the size of the packet; initiating a write access having a size larger than the size of the packet to a storage device; receiving subsequent packets included in the streaming write operation; and writing data received in the subsequent packets to the storage device as part of the write access initiated in response to the earlier packet. In some embodiments, streaming read operations may also be supported.

Abstract: A method and apparatus optimizes the speed and efficiency of data transfer between two devices having different data input/output rates. In one embodiment, the present invention is directed to a computer software driver or hardware apparatus that may work with any port and/or network. The driver has a calibrator portion for optimizing data transfer between a CPU and a peripheral. The calibrator portion includes a data input/output rate profiler. The profiler preferably sends run-time data samples to the peripheral, builds a table that relates each data sample to an aggregate data transfer rate, and selects the optimum result as a model for further data transfer. A preferred method for performing the present invention is also included.

Abstract: System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Abstract: A method of scheduling the handling of data from a plurality of channels. The method includes accumulating data from a plurality of channels by a remote access server, scheduling a processor of the server to handle the accumulated data from at least one first one of the channels, once during a first cycle time, and scheduling the processor to handle the accumulated data from at least one second one of the channels, once during a second cycle time different from the first cycle time.

Abstract: Disclosed is a system, method, and program for transferring data. Whether data is being transferred to physical volumes in peak mode is identified. If the data is being transferred in peak mode, whether a large chain of data is available for transfer to physical volumes is determined. If the large chain of data is not available, whether a small chain of data is available for transfer to physical volumes is determined. If the small chain of data is available, the small chain of data is transferred to physical volumes. Additionally, if one or more files that have ages greater than a steady state age threshold are available, the one or more files are transferred to the one or more physical volumes. If one or more files that have ages greater than a peak age threshold are available, the one or more files are transferred to the one or more physical volumes.

Abstract: Cancellation of transmission of print data from a host computer to a printer is implemented under a USB Printer Class protocol without increasing the burden upon a printer on the receiving side. Specifically, when the host computer issues a transmit-abort request to the printer during the transmission of print data, the host computer notifies the printer of cancellation of data transmission via a channel different from that used for the data transmission. Upon being so notified, the printer suspends processing and discards the data that has been received. After suspending the processing, discarding the received data completing the preparation of receiving next data stream the printer notifies the host computer of the completion of abort procedure. Host computer will not send next data stream until receiving the completion of abort procedure from printer.

Abstract: A method and an apparatus to track transition of a flag signal for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes one or more memory devices, coupled to a data bus, to receive a command signal, wherein the command signal initiates a set of data transfer operations to transfer data between the data bus and one of the one or more memory devices; and a timing unit, coupled to the one or more memory devices, to receive the command signal, a flag signal, and a memory select signal, the timing unit to generate a trigger signal, in response to a transition of the flag signal, to complete the data transfer operations if the memory select signal corresponds to the one of the one or more memory devices. Other embodiments have been claimed and described.

Abstract: An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.

Abstract: A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input.

Abstract: A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.

Abstract: A method and device for parameter independent buffer underrun prevention in a data communication system includes a buffer for compensating for a difference in the rate of flow of data having a write port and a read port. After a commencement of writing data into the buffer, a predetermined delay time occurs. When the delay time has passed, reading data out from the buffer starts. Then the length of a time gap between the completion of writing data into the buffer and completion of reading data out from the buffer is determined. Finally, the length of the predetermined delay time is decreased by a first value if the length of the time gap is larger than a specified tolerance value and the length of the predetermined delay time is increased by a second value if the length of the time gap is smaller than the specified tolerance value. The provided method and device advantageously adjusts to systems having dynamically varying parameters, e.g.

Abstract: A determination is made as to whether input/output constraints exist for controllers (e.g., control units) of a computing environment. To facilitate this determination, an I/O velocity is calculated. The I/O velocity represents a relationship between an amount of time waiting to use one or more resources of the controller and an amount of time using the one or more resources.

Abstract: An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.

Abstract: A dedicated bandwidth switch backplane has efficient receive processing capable of handling highly parallel traffic. Packets must pass a filtering check and a watermark check before the receive port is allowed to release them to a queue. Highly efficient algorithms are applied to conduct the checks on the packets in a way which expedites receive processing and avoids contention. A hybrid priority/port-based arbitration algorithm is used to sequence filtering checks on pending packets. A watermark comparison algorithm performs preliminary calculations on the current packet using “projected” output queue write addresses for each possible outcome of the queueing decision on the preceding packet and using the actual outcome to select from among preliminary calculations to efficiently address the outcome-dependence of the current packet's watermark check on the queueing decision made on the preceding packet.

Abstract: A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain.

Abstract: A computer system has a node and a service processor (SVP) connected together via a diagnosis section. An input/output (I/O) unit is connected to the SVP. The diagnosis section has a serial controller. The SVP writes data to be transmitted to the node from the I/O unit into the serial controller. The node reads data stored in the serial controller. The node also writes data to be transmitted to the I/O unit into the serial controller. The serial controller instructs the SVP to read the data written by the node. The SVP reads this data and sends it to the I/O unit.

Abstract: A method for altering timing between transmissions of an input device comprising the steps of (A) receiving a plurality of inputs from the input device, (B) altering the timing between the inputs and (C) presenting the altered inputs in a potentially insecure environment.

Abstract: A receiving apparatus constructed to store data received from a network in a buffer and read the data in the buffer based on a reference clock, has a detecting means for detecting change of a sampling frequency of the data, a first controlling means for controlling to stop writing of the data into the buffer and reading of the data from the buffer in response to an output of the detecting means, a clearing means for clearing the data in the buffer in response to the output of the detecting means, a clock changing means for changing a frequency of the reference clock in response to the output of the detecting means, and a second controlling means for controlling to restart the writing of the data into the buffer and the reading of the data from the buffer in response to the output of the detecting means.

Abstract: A method and apparatus for processing bytes received from a data stream includes multiple parallel byte processing engines that simultaneously process a first set of bytes received from a data channel during a first cycle and simultaneously process a second set of bytes received from the data channel during a second cycle. The method and apparatus further includes a state memory for storing byte information pertaining to the first set of bytes. When processing HDLC protocol bytes, the multiple parallel byte processing engines process the first and second set of bytes to identify at least one delineating byte contained within the data channel in accordance with a HDLC protocol.

Abstract: A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.

Abstract: A device driver apparatus, which can be configured at low cost, implements various types of tests while making a process perform the same operations as those of an actual I/O device in use. The device driver apparatus is configured by comprising an adapter which transmits or receives signal or data between an initiator and a pseudo process simulating an I/O device connected via a bus using a predetermined protocol, and a driver which is arranged between the adapter and the pseudo process simulating the I/O device, notifies the pseudo process of one or more of command and data from the adapter, and also notifies the adapter of one or more of status and data from the pseudo process. With this low-cost configuration, various types of tests can be conducted while making a process perform the same operations as those of an actual I/O device in use.

Abstract: An apparatus and method for making changes to an active schedule being processed by a host controller is disclosed. The apparatus and method includes examining a transaction descriptor, determining a current state for a transaction based on the transaction descriptor, and preventing the transaction from starting if the current state indicates the transaction has not already started.

Abstract: A host channel adapter configured for outputting packets according to InfiniBand™ protocol includes a queue pair attributes table having queue pair entries configured for specifying attributes of the respective queue pairs. Each queue pair entry includes a timestamp field for storing a time value. Upon teardown of a queue pair, a management agent stores a timestamp value, according to a prescribed time resolution interval, within the timestamp field and sets a corresponding wait state bit. The queue pair attributes table is accessed each prescribed time resolution interval for identification of idle queue pairs having passed a minimum idle interval at least equal to the prescribed time resolution interval. If an identified idle queue pair has a corresponding timestamp value indicating passing of the minimum time idle interval, the corresponding wait state bit is reset enabling the queue pair to be reused.

Abstract: A packet device is disclosed for recovering timing information from packets that were transmitted over a packet network. The packet device is comprised of a buffer and a synchronization system that includes a clock. The buffer receives packets that were transmitted based on a transmitter timing signal, and fills to a target number of packets. The buffer receives a receiver timing signal from the clock, and transfers the packets based on the receiver timing signal. The synchronization system determines a measured number of the packets in the buffer at any given time. The synchronization system compares the measured number to the target number to recover timing information. The synchronization system then adjusts the second timing signal based on the timing information.

Abstract: One or more queues store data information such as packets or data flows for later transmission to downstream communication devices. A real-time clock tracks current time and an advancement of a moving time reference, which is displaced with respect to the current time of the clock by an offset value. Thus, as current time advances, the moving time reference also advances in time. Upon servicing a queue, a time stamp associated with the serviced queue is also advanced in time. To monitor a rate of outputting data from the one or more queues, a processor device at least occasionally adjusts the offset value so that the moving time reference and values of the time stamps advance in relation to each other. Consequently, by tracking a relative time difference between current time of the real-time clock and a relative advancement of time stamps, a rate of outputting data information from the queue is monitored over time.

Abstract: A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.

Abstract: A latency-independent interface between hardware components, such as a hard disk controller (HDC) and a read/write (R/W) channel or a read channel (RDC) supports high read and write latencies of greater than one sector. Such an interface also supports a split sector format and multiple mark format. In addition to read and write clock signals, the interface comprises a data gate signal that controls the transfer of data between the the HDC and R/W channel, and a media gate signal that controls transfer of mode selection information from the HDC to the R/W channel and also controls the transfer of data between the R/W channel and a disk. The media. gate signal replaces the conventional read and write gate control signals. A buffer attention signal is also provided.

Abstract: A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART.

Abstract: Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

Abstract: A bus system and a command delivering method includes (a) delivering a first command to a first slave device, and (b) delivering a second command to a second slave device at a point in time which is less than or equal to a latency time of the second slave device in advance of the completion of data transfer according to the first command. Accordingly, preparation necessary for data transfer can begin sooner, thereby reducing idle clock cycles of a data bus.

Abstract: A method and apparatus for a burst mode write in a shared bus architecture comprising detecting a write data burst, determining if at least one memory unit is available to receive the write data burst, writing the write data burst to the at least one memory unit if the at least one memory unit is available to receive data. Storing a first portion of the write data burst in a buffer, concurrently with activating the at least one memory unit to receive data, if the at least one memory unit is not available to receive data; writing a second portion of the write data burst to the at least one memory unit when the at least one memory unit is available to receive data, and writing the first portion of the write data burst from the buffer to the at least one memory unit after writing the second portion of the write data burst.

Abstract: An apparatus for limiting a data transfer bandwidth through handshake suppression is configured to generate a first reset signal, generate a second reset signal a predetermined number of clock cycles after generating the first reset signal, generate a handshake count representing a number of receptions, between the first reset signal and the second reset signal, of a first Ready to Send (“RTS”) handshake signal and a first Ready to Receive (“RTR”) handshake signal, and disable a second RTR handshake signal and the first RTS handshake signal based on a comparison of the handshake count and a maximum value.

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract: A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued transaction of the at least one processor-issued transaction if the address conflict exists and rejects the first coherent I/O transaction. The forwarding device holds remaining processor transactions of the at least one processor-issued transaction that have an address conflict with the first address of the first coherent I/O transaction. The forwarding device transmits the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forwarding device releases the remaining processor transactions once the first coherent I/O transaction has been completed.

Abstract: A unique system and method for ordering commands to reduce disc access latency while giving preference to pending commands. The method and system involves giving preference to pending commands in a set of priority queues. The method and system involve identifying a pending command and processing other non-pending commands in route to the pending command if performance will not be penalized in doing so. The method and system include a list of command node references referring to a list of sorted command nodes that are to be scheduled for processing.

Abstract: A method and apparatus for reducing link latency caused by logic in a network interface. A media access controller having a converter, modification logic, a FIFO and a controller reduces the link latency caused when the logic modifies a data packet. The converter receives frame data from a transmit buffer and converts the frame data into a data packet having a prescribed format for transmission onto a network. The logic modifies the data packet. The FIFO buffers the data packet using a plurality of flip-flops. The controller controls the flow of the data packet and determines when to transmit the data packet onto a network via a media access controller.

Abstract: A user terminal (1) having a communications processor (10) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP application may not access the memory (14, 15). In the communications processor (10), the memory (14, 15) stores a process image. The communications processor (10), for the purpose of synchronization, transmits at the beginning of a cycle a cycle start interrupt (ZSI,x) and at the end of the cyclic part (ZYK,x) a cycle end interrupt (ZEI,x). Once the arithmetic unit (5, 7, 8) has accessed the memory it releases the interrupts. The duration (&Dgr;T′s2,1; &Dgr;T′e2,1) between two successive interrupts serves to detect access violations and to initiate appropriate fault treatment measures.

Abstract: A system for aggregating data includes aggregation mechanisms. Each aggregation mechanism is configured to receive data from incoming ports and aggregate timing information for the incoming ports before determining where to route the data from outgoing ports. The system may include line cards. Each line card may be configured to transmit data to the aggregate mechanisms.

Abstract: A timing information generating apparatus includes an input/output information identifying unit, a delay time calculating unit and a timing information output unit. The input/output information identifying unit compares logical connection information with a library to identify intra-block input stage sequential circuits contributing to information exchange with extra-block input stage sequential circuits, and intra-block output stage sequential circuits contributing to information exchange with extra-block output stage sequential circuits. According to timing constraint information, the delay time calculating unit sets first delay times from input pins to the intra-block input stage sequential circuits, and second delay times from the intra-block output stage sequential circuits to output pins. The timing information output unit outputs timing information including the first delay times and the second delay times.

Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.

Abstract: A signal output section of a port sampling circuit 6 periodically changes the output level of an output port 11 based on a sampling period stored in a register which is set by CPU 2. A data latch section of the port sampling circuit 6 latches the data given to an input port 10 based on a timing signal, with a starting point being set on a change point of the output level. A data register stores the latched data.

Abstract: An I/O control device that transfers data according to transfer control information, comprising a transfer control information memory means that stores transfer control information, a state detecting means that detects the processed state of the transfer control information stored in the transfer control information memory means, and a transfer control information memory control means by which new transfer control information is stored in the transfer control information memory means in place of the transfer control information upon completion of transfer control information-dependent transfer processing as a result of the detection by the state detecting means.

Abstract: A robust state machine is provided for controlling a slave interface to an I2C-bus. The state machine is configured to enforce the slave-device-protocol of the I2C specification, and to provide recovery from anomalous master-device behavior. In accordance with this invention, the state transitions of the state machine at the slave-device are controlled by the master-device's control of the SCL line of the I2C-bus, except if a START condition is detected. The state machine is configured to asynchronously respond to a START condition on the I2C-bus, regardless of its current state, to force the state machine to a known state. In the known state following the START condition, the slave-device terminates any transmissions to the I2C-bus, thereby minimizing subsequent interference on the bus.

Abstract: A system and method uses grouped calendars, flow queues, pointers and stored rules to process information packets so that different flow control characteristics associated with the information units are maintained.

Abstract: The present invention provides a method and apparatus for a scheduling driver to implement a protocol using time estimates for use with a device that does not generate interrupts. An application calls the scheduling driver to start an Input/Output (I/O) request to a device. The scheduling driver determines if the device is busy. If the device is not busy, the scheduling driver provides an estimated processing time (EPT) for the I/O request to be completed to the application. In one embodiment, if the device is busy, the scheduling driver calculates an estimated amount of time left (EATL) until the device will be available to the application and provides this EATL to the application. When the device is not busy, the application sleeps for the estimated processing time (EPT) and calls the scheduling driver to obtain the I/O operation results. If the I/O request has been completed, the scheduling driver provides the I/O operation results to the application.