Abstract: A wireless bridge includes a first universal asynchronous receiver/transmitter (UART) for coupling to a serial bus that receives data packets. A protocol independent module has a timer set to a desired time to detect a start and/or an end of a data packet received from the serial bus. A wireless transceiver is coupled to the universal asynchronous receiver/transmitter for sending and receiving data packets.

Abstract: In one embodiment of the present invention, while composing a textual message, a portion of the textual message is dynamically indicated as having heightened emotional value. In one embodiment, this is indicated by depressing a key on a keyboard for a period longer than a typical debounce interval. While the key remains depressed, a plurality of text parameters for the character associated with the depressed key are accessed and one of the text parameters is chosen. Animation processing is then performed upon the textual message and the indicated portion of the textual message is visually emphasized in the animated text message.

Abstract: Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward and reverse processing paths and forward and reverse processing time intervals along the respective paths. The forward and reverse processing time intervals begin when a block of data, such as encryption data, is gated into an individual processing element for processing and terminate when the processed block of data is gated into a subsequent adjacent processing element along the respective forward or reverse processing path. A clock signal distribution circuit provides a clock signal to the plurality of processing elements such that the clock signal arrives at successive processing elements along the clock signal distribution circuit with an increasing amount of delay so that one of the forward or reverse processing time intervals is greater than the other.

Abstract: Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller.

Abstract: A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction.

Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract: Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

Abstract: A communication apparatus includes a plurality of isochronous transfer processing units, each of which is configured to perform isochronous transfer using an isochronous channel set thereto; a security ensuring processing unit coupled to each of the plurality of isochronous transfer processing units, and configured to perform security ensuring processing to ensure the security of isochronous transfer performed by the corresponding isochronous transfer processing unit; and a security ensuring control unit configured to, in response to a request from a second communication apparatus for ensuring security of isochronous transfer, cause the security ensuring processing unit corresponding to the isochronous transfer processing unit which performs the isochronous transfer using an isochronous channel having been notified from the second communication apparatus along with or in advance of the request for ensuring security of isochronous transfer to perform the security ensuring processing.

Abstract: An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency FP and a secondary clock having a frequency FS?. The primary data is received over a fixed periodic interval TI and at a rate substantially equal to FP. The amount of primary data received over TI is known to be N. The data relay stage is further configurable to provide secondary data via a secondary data interface based on the primary data and the secondary clock. The circuit also includes a phase-locked loop (PLL) circuit configurable to receive an interval reference signal having a frequency FI substantially equal to 1/TI. The PLL circuit is also configurable to provide the secondary clock based on the interval reference signal.

Abstract: A system, method, and computer program product are provided for inserting a gap in information sent from a drive to a host device. In operation, one or more commands are received at a drive from a host device. Additionally, information is queued to send to the host device. Furthermore, a gap is inserted in the information to send to the host device such that the host device is capable of sending additional commands to the drive.

Abstract: Provided is an information processing system that communicates with a storage apparatus through a plurality of paths Pi (i=1 to n, where n is a total number of the paths), and that issues an I/O to the storage apparatus through one of the paths Pi. The information processing system sets weights Wi for the respective paths Pi; obtains an I/O issue interval di of each of the paths Pi by dividing a sum total ?Wi of the weights Wi by the weight Wi set for the path Pi; obtains I/O issue timings ti(m)of each of the paths Pi by using the following equation: ti(m)=di/C+m·di (m=0, 1, 2, . . . ) (where C is a constant); and issues the I/Os to the paths Pi in an order corresponding to the an order of the I/O issue timings ti(m) chronologically arranged.

Abstract: A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.

Abstract: An apparatus such as a Device Wire Adapter (DWA) with improved buffer management and packaging of Wireless Universal Serial Bus (WUSB) isochronous packets for transmission to a host. The apparatus includes an isochronous IN endpoint that receives data segments from a device function. Memory is associated with the endpoint and includes an endpoint buffer configured in a loop and a plurality of registers. The apparatus includes an endpoint controller that stores the received data segments sequentially in the loop buffer, assigns a set of the registers to each of the stored data segments, and stores additional packet information in the registers for each of the data segments rather than in the endpoint buffer. The additional packet information includes presentation time for the stored data segment derived from a sample time of a last segment in the buffer and a time interval between two consecutive data segments in the buffer.

Abstract: Proposed is a highly reliable information detecting apparatus and method. In an information detecting apparatus and method for detecting transmission information a transmission signal in which a burst period of transmitting a burst signal and a space period as a no-signal period are repeated in a pattern according to the subject matter of the transmission information, whether the absolute value of a signal amplitude level of the transmission signal is not less than a first threshold is detected, whether the absolute value of a signal amplitude level of the transmission signal is not less than a second threshold is detected, and whether the amplitude level displacement of the transmission signal is based on noise or the reception of the transmission information is determined based on the detection results.

Abstract: Methods, systems, apparatuses and program products are disclosed for communications such as may be used for debugging computers and similar electronic products at a level suitable for low level firmware. This may find application, for example, in environments after cache initialization around the time of memory bring up or motherboard device enumeration but including durability into and beyond software loading. GPIO (General Purpose input/output) connections may be used for communication that may, for some purposes, be regarded as half-duplex but without necessarily being anisochronous.

Abstract: A data storage device includes a plurality of memory devices and a memory controller. The memory controller exchanges data with the plurality of memory devices via a plurality of channels and adjusts drive strength of the plurality of channels by referring to at least one of the number of the plurality of memory devices and current temperature.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: Provided are a method and a system for controlling a disk input/output (I/O). The method includes detecting the number of consumed tokens that are the processing units of the disk I/O. Also, the method includes assigning a time slice that is a duration for processing the disk I/O according to the number of the consumed tokens using a preset minimum disk I/O bandwidth and a preset maximum disk I/O bandwidth.

Abstract: In a multimedia system, a method and system for deglitching in a mobile multimedia processor are provided. A deglitching operation may be provided to reduce noise and compensate for strobe signal delays that may result in false bus cycles and other operating errors. A circuit comprising a plurality of delay cells, a multiplexer, and a latch may be utilized to perform the deglitching operation. The delay cells may be selected from several delay options having different time delays based on operating temperature and applied supply voltage. The time delay may be programmable and may be dynamically varied in accordance with the operation of the mobile multimedia processor.

Abstract: A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/output operation. The hurry up command can be employed in the Direct Access File System.

Abstract: A method for handling input/output (I/O) commands in a storage system includes establishing first and second counters for counting unfinished I/O commands, and establishing a reference which is initially set to the first counter. The reference is periodically switched between the first counter and the second counter, and the switching interval is less than the I/O timeout value. Upon placing an I/O command into an I/O command queue, a copy of the current reference is made into an I/O specific control block and the current referenced counter is incremented. Upon finishing of an I/O command, the counter referenced by the I/O specific control block is decremented and the I/O command is removed from the I/O command queue. When switching the reference, a problem is detected in the event that the counter being switched to is above a predetermined threshold. Upon detection of a problem, a more explicit I/O check is conducted.

Abstract: An apparatus, system, and method are disclosed for acceleration initiated association. A peripheral knock module receives a first knock command from a first accelerometer of a peripheral device. The first knock command comprises a plurality of peripheral time stamps for a plurality of peripheral device accelerations. A peripheral identifier module creates a peripheral identifier comprising time interval values of time intervals between the peripheral time stamps. A broadcast module broadcasts a discovery signal with a signal identifier that comprises the peripheral identifier.

Abstract: A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system includes: a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; and a FIFO. The FIFO is connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the received data can be supplied from the FIFO to the stream register unit. The Processing system also includes a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.

Abstract: A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: A display controller including: a host I/F which performs interface processing between the display controller and a host CPU; a memory into which a multimedia processing program is loaded, when the host CPU has read the multimedia processing program from a multimedia processing program group stored in a host memory and transmitted the multimedia processing program to the display controller; a built-in CPU which executes a software processing portion of the multimedia processing assigned to software processing based on the multimedia processing program; and an H/W accelerator which executes a hardware processing portion of the multimedia processing assigned to hardware processing.

Abstract: Methods and systems are provided for helping maintain isochronous communications with peripheral devices (308), such as USB devices, over a network (302). Some methods for facilitating isochronous IN communication include noting (1906) passage of a predetermined interval without communication (310) from the peripheral device driver (402), and then creating (1908) a dummy communication (312) and sending (1910) it over the network toward the peripheral device to maintain isochronous communication toward the peripheral device. Some methods for facilitating isochronous OUT communication include noting (2006) passage of a predetermined interval without receipt, over the network, of a responsive communication (310) from the peripheral device in response to a first communication, and then creating (2008) a dummy communication (312) and sending (2010) it toward the peripheral device driver to maintain isochronous communication transmissions toward the peripheral device driver.

Abstract: Methods and systems for communicating information through a USB device using suspend/resume states are presented. A USB host stops transmitting Start-of-Frame (SOF) packets to a USB device, causing the USB device to enter a sleep/suspend state. The USB host then restarts the transmission of SOF packets to trigger the USB device back into a normal/resume state. The USB host repeats this process in a temporal pattern corresponding to a message, such that a circuit monitoring the USB device can determine the message.

Abstract: A storage system including: a controller connectable to a plurality of computers; and a plurality of storage devices connected to the controller, wherein the plurality of storage devices store a plurality of contents, wherein the controller receives a first request from a one of the plurality of computers which requests access to a first content of the plurality of contents, wherein the controller calculates a first data transfer rate of the first request, and wherein, based on the first data transfer rate, the controller dynamically controls settings of a first storage system resource during performing a first data transfer operation to satisfy the first request, to substantially maintain the access to the first content at substantially the first data transfer rate.

Abstract: The invention provides a method of controlling a jitter buffer, which sets a packet delete area, a packet add area, and a clock control area inside a FIFO forming the jitter buffer. The method controls to delete packets when the stored packet quantity is within the packet delete area, controls to add packets when the stored packet quantity is within the packet add area, and controls to raise or lower the clock frequency for reading the packets when the stored packet quantity is within the clock control area, in which the clock control area is set between the packet add area and the packet delete area.

Abstract: A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.

Abstract: A media access controller to adapt a rate of an output signal to a rate of an output medium is provided. The media access controller includes a register configured to output data to an external device, said register comprising a first input configured to control an output of the register and a second input configured to control an input to said register. The media access controller also includes a receiver configured to accept a signal from an external clock over the output medium and to provide said external clock signal to said first input of said register. An internal clock in the media access controller is configured to provide an internal clock signal from said internal clock to said second input of said register.

Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge.

Abstract: A processing engine includes descriptor transfer logic that receives descriptors generated by a software controlled general purpose processing element. The descriptor transfer logic manages transactions that send the descriptors to resources for execution and receive responses back from the resources in response to the sent descriptors. The descriptor transfer logic can manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources all on behalf of the general purpose processing element.

Abstract: Described is a system and method for frequency offset testing. The system comprises an electronic device, a first testing device providing a reference clock signal at a first frequency to the electronic device, and a second testing device receiving data from the electronic device at the first frequency and transmitting data to the electronic device at a second frequency. The second frequency is equal to a product of the first frequency and a frequency offset value.

Abstract: An electronic device is adapted to be connected to a plurality of peripheral devices, and includes a storage unit and a control circuit. The storage unit records a preset time and a control list. The control list lists at least a selected one of the electronic device and the peripheral devices, and an operation mode therefor. The control circuit detects whether the preset time matches a reference time, and if so, controls operation of the selected one of the electronic device and the peripheral devices according to settings in the control list.

Abstract: A data processing system refreshes a display at a first frequency when operating in a first power mode. The data processing system refreshes the display at a second frequency when operating in a second mode. The first frequency is higher than the second frequency, and the second power mode is configured to consume less power than the first power mode.

Abstract: Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

Abstract: Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

Abstract: Embodiments of the present invention are directed to providing continuously updated completion time and an average completion time information for I/O commands on a per-LU, per-target, per-port basis. This measurement is performed by a kernel device driver that handles the I/O for the system at lower layers, so the measurements are more accurate because the delays due to higher level processing are not included. This approach allows the driver to track movements in the average I/O command completion time per LU and limit outstanding I/O counts early enough to potentially prevent overload conditions. By catching the overload early, the invention also has the ability to restore the original outstanding I/O count as the overload condition subsides.

Abstract: Techniques for managing feedback control systems are provided. By way of example, a method of controlling performance of a managed system by a controller includes the following steps/operations. The controller issues a control value to the managed system to affect a performance of the managed system. The controller maintains a measurement time period having a variable start time within which the performance of the managed system is measured, such that the control value is given time to take effect on the managed system and a performance metric fed back to the controller from the managed system reflects the effect of the control value on the managed system.

Abstract: An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling timeout requests to determine whether the expiration time has been reached for execution of an input/output (I/O) request, thereby requiring action to cancel the I/O operation if it has not yet been completed.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: An apparatus, system, and method are disclosed for copying data. The present invention includes a data storage subsystem that supports fast replication and a host system that communicates a fast replication request to the data storage subsystem, estimates an expected wait time for a pending fast replication operation if the fast replication request is not granted, awaits the expiration of the wait time, communicates an additional fast replication request to the data storage subsystem, and records the data as moved if the additional fast replication is granted. In certain embodiments, the host system moves the data via conventional I/O operations if the expected wait time exceeds an expected duration for the conventional I/O operations.

Abstract: The present invention relates to a storage unit comprising: a channel control portion for receiving a data input/output request; a cache memory for storing data; a disk control portion for performing input/output processing on data in accordance with the data input/output request; and a plurality of disk drives for storing data, wherein at least two of the disk drives input data to and output it from the disk control portion at different communication speeds. Further, the storage unit has a plurality of communication paths provided to connect at least one of the disk drives in such a manner as to constitute a loop defined by the FC-AL fiber channel standards, so that the communication speeds can be set differently for these different communication paths.

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.