Addressing Combined With Specific Memory Configuration Or System Patents (Class 711/1)
  • Patent number: 9652306
    Abstract: A service manages a plurality of virtual machine instances for low latency execution of user codes. The service can provide the capability to execute user code in response to events triggered on various event sources and initiate execution of other control functions to improve the code execution environment in response to detecting errors or unexpected execution results. The service may maintain or communicate with a separate storage area for storing code execution requests that were not successfully processed by the service. Requests stored in such a storage area may subsequently be re-processed by the service.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: May 16, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Allen Wagner, Ajay Nair, Marc John Brooker, Scott Daniel Wisniewski
  • Patent number: 9654447
    Abstract: Making a determination of originality of content is disclosed. At least one originality factor related to the content is analyzed, wherein the originality factor is independent of a time when the content is detected. Based on the analysis of the at least one originality factor, automatically the determination is automatically made. The determination is outputted.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: May 16, 2017
    Assignee: Digimarc Corporation
    Inventors: James L. Brock, James E. Pitkow
  • Patent number: 9640232
    Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs data, a data strobe signal, an external command, and a clock signal. The second semiconductor device aligns the data in synchronization with the data strobe signal to generate first and second alignment data and latches the first and second alignment data to generate first and second latch data in response to a latch signal which is generated by dividing the data strobe signal.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 2, 2017
    Assignee: SK HYNIX INC.
    Inventors: Min Chang Kim, Chang Hyun Kim, Do Yun Lee, Jae Jin Lee, Hun Sam Jung
  • Patent number: 9628351
    Abstract: A scalable variant configuration platform separates, behind a defined interface, mechanisms for determining configurations based upon provided variants. Information regarding specific factors, or “variants” is provided and a configuration request object is generated through which services can be configured. A schema is utilized to generate an object model that can assign object-oriented properties, such as type information, to the various factors that can influence configuration. The schema is also utilized to generate a sample configuration file, which can aid in the generation of the configuration file that can specify how one or more factors can affect the configuration of the services. The generation of the configuration request object is based upon self-tuning algorithms that can adapt based upon the types of factors that will be utilized for the configuration of the services being provided.
    Type: Grant
    Filed: June 9, 2013
    Date of Patent: April 18, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Simon Gansky, Justin Melvin, Ivan Laktyunkin, Prasad Tammana, Isidro Hegouaburu
  • Patent number: 9626108
    Abstract: Dynamically provisionable and allocatable memory external to a requesting apparatus may be provided. A request for primary memory may be made by an application executing on a client. An allocation logic unit may determine an allocation strategy in response to the request. As part of the allocation strategy, the allocation logic unit may identify memory appliances on which memory regions are to be allocated. The allocated memory regions may form the primary memory that is allocated to the requesting application. The allocation logic unit may send region allocation requests to region access unit of the respective memory appliances. The memory appliances on which the memory regions are allocated may be external to the client. The application may access the allocated memory regions via client-side access in which one or more processors in the client and/or the memory appliances are bypassed.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 18, 2017
    Assignee: Kove IP, LLC
    Inventors: Timothy A. Stabrawa, Zachary A. Cornelius, John Overton, Andrew S. Poling, Jesse I. Taylor
  • Patent number: 9590839
    Abstract: Provided are a system, method, and computer program product for controlling access to a shared storage system in communication with at least one cluster of host nodes. Cluster membership metadata is stored in a storage independent from the shared storage for at least one cluster. The cluster membership metadata is updated in response to an inclusion or exclusion request from a requesting host node comprising one of the host nodes identifying at least one other host node to include or exclude from a cluster. Access to at least one storage volume in the shared storage system is managed in response to the updating of the cluster membership metadata for the inclusion or exclusion request.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Curran, Carlos F. Fuente, Kalyan C. Gunda, Wolfgang Mueller-Friedt
  • Patent number: 9582415
    Abstract: Technologies for an operating system identifying SSD and CSSD devices based on a corresponding descriptor, and for optimizing operating system functionalities with respect to the SSD/CSSD device. Optimizations include disabling non-SSD/CSSD functionalities, such as HDD defragmentation, and by enabling SSD/CSSD specific functionalities, such as write optimization storage functionalities.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: February 28, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Frank J Shu, Nathan S Obr
  • Patent number: 9569115
    Abstract: An application located in one or more first memory regions is executed. The application has a separate modified portion, which is located in one or more second memory regions. A request is obtained to access one of a first memory region or a second memory region, the request including an address of a first type. Based on obtaining the request, the address is translated to another address. The other address is of a second type and indicates the first memory region or the second memory region. The translating is based on an attribute associated with the address, in which the attribute is used to select information from a plurality of information concurrently available for selection. The plurality of information provide multiple addresses of the second type, one of which is the other address. The other address is used to access the first memory region or the second memory region.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9552355
    Abstract: A system and a method for phrase-based translation are disclosed. The method includes receiving source language text to be translated into target language text. One or more dynamic bi-phrases are generated, based on the source text and the application of one or more rules, which may be based on user descriptions. A dynamic feature value is associated with each of the dynamic bi-phrases. For a sentence of the source text, static bi-phrases are retrieved from a bi-phrase table, each of the static bi-phrases being associated with one or more values of static features. Any of the dynamic bi-phrases which each cover at least one word of the source text are also retrieved, which together form a set of active bi-phrases. Translation hypotheses are generated using active bi-phrases from the set and scored with a translation scoring model which takes into account the static and dynamic feature values of the bi-phrases used in the respective hypothesis. A translation, based on the hypothesis scores, is then output.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: January 24, 2017
    Assignee: XEROX CORPORATION
    Inventors: Marc Dymetman, Wilker Ferreira Aziz, Nicola Cancedda, Jean-Marc Coursimault, Vassilina Nikoulina, Lucia Specia
  • Patent number: 9519542
    Abstract: A storage control apparatus includes a controller to, when more storage devices, among a plurality of storage devices across which a plurality of information areas storing information representing redundant data and one or more spare areas are distributed, than the number of the spare areas fail, perform a rebuild process of information stored in a plurality of information areas of a failed first storage device included in the plurality of combinations of the plurality of information areas and the one or more spare areas, the rebuild process including restoring information corresponding to one information area of the failed first storage device included in one combination among the plurality of combinations, and determining a write destination storage device to which the restored information is to be written in accordance with the number of times information is read from a non-failed second storage device.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: December 13, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Guangyu Zhou, Takeshi Watanabe, Kazuhiko Ikeuchi, Chikashi Maeda, Yukari Tsuchiyama, Kazuhiro Urata
  • Patent number: 9521089
    Abstract: A system for multi-layer quality of service (QoS) management in a distributed computing environment includes: a management node hosting a workload scheduler operable to receive a workload and identify a workload QoS class for the workload; and a plurality of distributed compute nodes, the workload scheduler operable to schedule running of the workload on the compute nodes. The workload scheduler is operable to: translate the workload QoS class to a storage level QoS class; communicate the storage level QoS class to a workload execution manager of the compute nodes; and communicate the storage level QoS class to one or more storage managers, the storage managers managing storage resources. The storage managers are operable to extend the storage level QoS class to the storage resources to support the workload QoS class.
    Type: Grant
    Filed: August 30, 2014
    Date of Patent: December 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yonggang Hu, Zhenhua Hu, Reshu Jain, Prasenjit Sarkar, Rui Zhang
  • Patent number: 9513836
    Abstract: A method for migrating data in a storage system by a computer. Data is selected to migrate from a first storage to the second storage, wherein selected files are in a resident state. Metadata is obtaining and subsets of data are ordered based on the obtained metadata, the order of the subsets of data following an expectation of update value. The subsets of data are transferring to the second storage based on the order of the subsets of data based on a predetermined schedule. Data determined as inactive is overwritten on the sequential access medium by transferred data. End data to the sequential access medium is set after a last active data is written before the one or more sets of data are determined to be inactive. The one or more sets of data determined to be inactive are deleted from the second storage and a transfer is initiated.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Masayuki Iwanaga, Yutaka Oishi
  • Patent number: 9515956
    Abstract: A technique for multi-layer quality of service (QoS) management in a distributed computing environment includes: receiving a workload to run in a distributed computing environment; identifying a workload quality of service (QoS) class for the workload; translating the workload QoS class to a storage level QoS class; scheduling the workload to run on a compute node of the environment; communicating the storage level QoS class to a workload execution manager of the compute node; communicating the storage level QoS class to one or more storage managers of the environment, the storage managers managing storage resources in the environment; and extending, by the storage managers, the storage level QoS class to the storage resources to support the workload QoS class.
    Type: Grant
    Filed: October 19, 2014
    Date of Patent: December 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yonggang Hu, Zhenhua Hu, Reshu Jain, Prasenjit Sarkar, Rui Zhang
  • Patent number: 9514150
    Abstract: Example embodiments relate to automatic WORM-retention state transitions. In example embodiments, a storage computing device may detect a request to access, via a file system, a file that is associated with a first retention state. The first retention state may indicate either a first type of WORM-retention protection for the file or no WORM-retention protection for the file. The storage computing device may determine, in response to the request, that the file should be designated with a second retention state. The second retention state may indicate a second type of WORM-retention protection for the file. The determination may be based on a retention policy file that is tightly integrated with the file system and metadata of the file. The storage computing device may transition the file (e.g., by communicating with the file system) to be associated with the second retention state instead of the first retention state.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 6, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Andrew M Sparkes, Rajkumar Kannan, Michael J Spitzer, Joseph E Fernandes
  • Patent number: 9507593
    Abstract: An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension. The functional unit has a second register to store a second input vector operand specifying coordinates of a particular segment of the multi-dimensional structure. The functional unit also has logic circuitry to calculate an address offset for the particular segment relative to an address of an origin segment of the multi-dimensional structure.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Mikhail Plotnikov, Andrey Naraikin, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 9495291
    Abstract: A method of interleaving a memory by mapping address bits of the memory to a number N of memory channels iteratively in successive rounds, wherein in each round except the last round: selecting a unique subset of address bits, determining a maximum number (L) of unique combinations possible based on the selected subset of address bits, mapping combinations to the N memory channels a maximum number of times (F) possible where each of the N memory channels gets mapped to an equal number of combinations, and if and when a number of combinations remain (K, which is less than N) that cannot be mapped, one to each of the N memory channels, entering a next round. In the last round, mapping remaining most significant address bits, not used in the subsets in prior rounds, to each of the N memory channels.
    Type: Grant
    Filed: April 13, 2014
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Feng Wang, Bohuslav Rychlik, Anwar Q. Rohillah
  • Patent number: 9459928
    Abstract: A data processing system supports remote graphics console and virtual media access to virtual machines. The data processing system is configured for usage with a virtualization platform that runs multiple operating systems simultaneously on at least one physical server. The data processing system comprises a virtual keyboard/video/mouse (KVM) element integrated into the virtualization platform and is configured to generate a remote management graphics console and map virtual media into the operating system plurality.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: October 4, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Thomas J. Bonola, John M. Hemphill, Mike Dickson
  • Patent number: 9443618
    Abstract: Provided is a semiconductor memory device that may efficiently map an internal address used inside the semiconductor memory device in response to an external address that is applied from the outside of the semiconductor memory device. The semiconductor memory device may include a memory cell array configured to include a first main cell array, a first spare cell array, a second main cell array, and a second spare cell array each of which has internal cells that are selected in response to an internal address, and an address mapping unit configured to map external address as the internal address when the external address designates the first main and spare cell arrays, and to operate calculation with a given value and the external address and to map the calculation result value as the internal address when the external address designates the second main and spare cell arrays.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 13, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sang-Oh Lim
  • Patent number: 9424257
    Abstract: A method for operating a data processing system to extract information from a record is disclosed. The method includes defining a plurality of ALTERNATIVE statements. Each ALTERNATIVE statement includes a label that identifies that ALTERNATIVE statement, a Signature that defines a test that is to be performed on a field in the data record defined by a first window, and a NEXT statement that defines a different ALTERNATIVE statement and a second window for testing by that different ALTERNATIVE statement. In one aspect of the invention, the test includes a regular expression that is to match the field. The method defines a SCHEMA statement that defines a plurality of fields within the record. One of the defined fields includes an offset defining a location in the record, a field name, and a field length. The offset and/or the field length are computed by the data processing system.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 23, 2016
    Assignee: Keysight Technologies, Inc.
    Inventors: Andrew Robert Lehane, Antony Kirkham
  • Patent number: 9400697
    Abstract: A recursive solution to a bin-packing algorithm provides efficient allocation of computing or communications resources to resource consumers in a computer or network system. The algorithm determines resource requirement vectors for the consumers that specify amounts of multiple resource types required for each consumer, thereby forming a multi-dimensional bin-packing problem. The algorithm assigns the resource consumers to corresponding groups of computing or communication resources by recursively exploring partial solutions that assign the consumers to the groups by extending the partial solutions via recursion until the requirements in the resource requirement vectors are met.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: July 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael David Moffitt
  • Patent number: 9396035
    Abstract: A recursive solution to a bin-packing algorithm provides efficient allocation of computing or communications resources to resource consumers in a computer or network system. The algorithm determines resource requirement vectors for the consumers that specify amounts of multiple resource types required for each consumer, thereby forming a multi-dimensional bin-packing problem. The algorithm assigns the resource consumers to corresponding groups of computing or communication resources by recursively exploring partial solutions that assign the consumers to the groups by extending the partial solutions via recursion until the requirements in the resource requirement vectors are met.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: July 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael David Moffitt
  • Patent number: 9368147
    Abstract: Systems and methods are described for validating storage media and/or media drives in a storage library using a hidden drive pool and a non-hidden media pool. For example, a storage library can be instructed to perform media/drive validation (MDV) on a selected pool of physical storage media using a selected pool of drive resources. Embodiments handle the pools so that, at least during performance of MDV, the drive resources in the drive pool are not visible to the host applications, but the storage media is still visible and can still be accessed by the host application. For example, the MDV can be performed in such a way that the host application cannot task a drive being used for validation, but the host application can perform operations on storage media in the media validation pool. Further, some embodiments operate in the context of storage library complex-wide validation pools.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 14, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Hyoungjin Kim, Alex Amador, Stephanie Lynn Russell
  • Patent number: 9361987
    Abstract: Systems and processes may use a first memory, a second memory, and a memory controller. The second memory is at least as large as a block of the first memory. Data is received and stored in the second memory for further writing to the second memory.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: June 7, 2016
    Assignee: Apple Inc.
    Inventors: Michael J. Cornwell, Christopher P. Dudte
  • Patent number: 9329834
    Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Radomir Jakovljevic, Aleksandar Beric, Edwin Van Dalen, Dragan Milicev
  • Patent number: 9323564
    Abstract: Systems, methods, and computer program products that provide for the use of a type 2 VMM to de-link or isolate underlying processor hardware from an operating system. This may allow the launching of a task that requires direct access to processor hardware, where such access requires the absence of an operating system. Such a task may take the form of a type 1 VMM, such as an information security or integrity VMM, e.g., an anti-malware VMM.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Manohar R. Castelino, Vedvyas Shanbhogue, Sergio Rodriguez
  • Patent number: 9274819
    Abstract: Techniques are provided to allow concurrent operation of threads in an operating system that does not support kernel threads. A first process may create a first thread. The first thread may create a second process. The second process is granted access to a portion of the address space of the first thread. Synchronization information is passed between the first thread and the second process over a communications channel.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: March 1, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Thirusenthilanda Arasu Velayutham
  • Patent number: 9268680
    Abstract: An electronic apparatus includes a read-only memory (ROM), a random access memory (RAM), a processing module, a demand paging module and a decompression module. The ROM stores multiple sets of compressed data corresponding to a plurality of sets of uncompressed data. The plurality of sets of uncompressed data are divided from one same set of original data. According to a request associated with the set of original data and from the processing module, the demand paging module selects one or more sets from the multiple sets of compressed data. The decompression module decompresses and stores the selected one or more sets of compressed data to the RAM for use of the processing module.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 23, 2016
    Assignee: MStar Semiconductor, Inc.
    Inventors: Shu-Cheng Chou, Yu-Kuey Wu
  • Patent number: 9270619
    Abstract: Configuring third party solutions to operate with virtual machines and virtual switches in a distributed network environment. The method includes receiving information at a logical switch about third party solutions in a distributed network. The method further includes receiving information at the logical switch about requirements for virtual components of the distributed network. The method further includes the logical switch automatically configuring third party solutions in the distributed network to meet the requirements for the virtual components of the distributed network.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 23, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pradeep Senniappan, Karthikeyan Nenmeli Ravichandran, Natalia Valeryevna Varava, Gregory M. Cusanza
  • Patent number: 9264449
    Abstract: An access control determination service automatically determines and/or revises an access control policy using actions attempted by a client system. A client is observed during operation. A policy system analyzes the actions performed and/or results of the actions performed by a client system. Using the results of the analysis, the access control determination service determines the permissions needed in an access control policy that will be applied to the client.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: February 16, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Gregory B. Roth, Eric Jason Brandwine, Reto Kramer
  • Patent number: 9241087
    Abstract: A method for controlling a mobile terminal, and which includes entering, via a camera of the mobile terminal, a capture mode; receiving, via a controller of the mobile terminal, a start input for starting a grouping image process; capturing, via the camera, at least one image; receiving, via the controller, an end input for ending the grouping image process; and storing, in a memory associated with the mobile terminal, the at least one image captured between the start input and the end input in a group.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: January 19, 2016
    Assignee: LG Electronics Inc.
    Inventor: Yongkyoung Shin
  • Patent number: 9141490
    Abstract: When information about a failed physical server is inputted, the number of processing programs which are insufficient to meet an availability requirement specified in advance is calculated for each subsystem executing on a computer system, and a graceful degradation which meets the availability requirement is determined by changing the quantity of computer resources allocated to processing programs.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: September 22, 2015
    Assignee: NEC CORPORATION
    Inventor: Fumio Machida
  • Patent number: 9134917
    Abstract: A hybrid media storage architecture has a log-structured file system configured to control a plurality of different storage media organized as hybrid storage media that cooperate to provide a total storage space of a storage system. The log-structured file system is configured to perform initial placement and migration of data, as well as fine-grain write allocation of the data, among storage space locations of the hybrid storage media to thereby improve the performance characteristics of the media. By defining and implementing heuristics and policies directed to, e.g., types of data, the file system may initially place data on any of the different media and thereafter migrate data between the media at fine granularity and without the need for manual enforcement.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: September 15, 2015
    Assignee: NetApp, Inc.
    Inventors: Jeffrey S. Kimmel, Steven R. Kleiman, Steven C. Miller
  • Patent number: 9128939
    Abstract: A system and method of automatically naming files on a mobile device can include determining at least one of a current geographical location data of a mobile device, a current time data, and a current date data. The current geographical location data, the current time data, and the current date data can be made can be compared to at least one of a personal information manager database and a geographical location database. A filename can be automatically-generated based on the comparison, and the filename can be applied to camera data received on the mobile device. The automatically-generated filename can include information relevant to the content of the camera data, thereby enhancing the efficiency and ease of identifying and organizing camera data stored on a memory of the mobile device.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 8, 2015
    Assignee: BlackBerry Limited
    Inventor: Alexander Scott Kinsella
  • Patent number: 9122698
    Abstract: Peer-to-peer redundant file server system and methods include clients that determine a target storage provider to contact for a particular storage transaction based on a pathname provided by the filesystem and a predetermined scheme such as a hash function applied to a portion of the pathname. Servers use the same scheme to determine where to store relevant file information so that the clients can locate the file information. The target storage provider may store the file itself and/or may store metadata that identifies one or more other storage providers where the file is stored. A file may be replicated in multiple storage providers, and the metadata may include a list of storage providers from which the clients can select (e.g., randomly) in order to access the file.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 1, 2015
    Assignee: Overland Storage, Inc.
    Inventors: Francesco Lacapra, Peter Wallace Steele, Bruno Sartirana, Ernest Ying Sue Hua, I Chung Joseph Lin, Samuel Sui-Lun Li, Nathanael John Diller, Thomas Reynold Ramsdell, Don Nguyen, Kyle Dinh Tran
  • Patent number: 9122688
    Abstract: Storing a data storage object in a first data storage system that uses object IDs with a first object ID format includes determining if the data storage object was created on a second, different, data storage system having a second object ID format different from the first object ID format or created using an emulator of the different data storage system, using a lookup table to translate between the first object ID format and the second object ID format in response to the data storage object having been created on the different data storage system, and directly converting the object ID to a new object ID having the second object ID format without using external data. Directly converting may include converting at least a portion of the content of the data storage object into at least a portion of the object ID.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: September 1, 2015
    Assignee: EMC Corporation
    Inventor: Raj Palanki
  • Patent number: 9117035
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 25, 2015
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 9111302
    Abstract: A data communication method and apparatus for a retail organization is disclosed. In the method an intermediate data processing entity generates a set of data for sending to at least one mobile terminal based on data from at least one data processing device associated with the retail organization and send the generated set of data to the at least one mobile terminal. At least one mobile terminal may send user data to the intermediate data processing entity. Upon receipt of user data from at least one mobile terminal the received user data is processed in the intermediate data processing entity to determine if data is to be communicated from the intermediate data processing entity. If it is determined that communication of data is needed, data can be communicated to at least one of a data processing device associated with the retail organization and at least one mobile terminal.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: August 18, 2015
    Assignee: PHM ASSOCIATES LIMITED
    Inventor: Peter Hookham-Miller
  • Patent number: 9104330
    Abstract: A method, computer program product, and computing system for identifying a target storage device upon which a plurality of logical storage devices are to be defined. The target storage device includes a plurality of physical storage blocks. At least a first logical storage device and a second logical storage device are defined for mapping within the target storage device. Each of the first and second logical storage devices includes a plurality of logical storage slices. At least a portion of the logical storage slices for each of the first and second logical storage devices are non-sequentially mapped to at least a portion of the plurality of physical storage blocks included within the target storage device to generate an interlaced target storage device.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: August 11, 2015
    Assignee: EMC Corporation
    Inventors: David Haase, Michael D. Haynes, Miles A. de Forest, Paul T. McGrath, Dayanand Suldhal, Nagapraveen Veeravenkata Seela, Alan L. Taylor
  • Patent number: 9098488
    Abstract: A communication object including a plurality of object words may be received. The communication object may be parsed to identify each of the object words as tokens. A first natural language and at least one natural language different from the first natural language that are associated with the plurality of object words may be determined, based on a language analysis of the tokens. Tokens associated with the first natural language and tokens included in embedded word phrases associated with the embedded natural language may be translated, via a translating device processor, to a target natural language, based on at least one context associated with the communication object.
    Type: Grant
    Filed: April 3, 2011
    Date of Patent: August 4, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ahmed Abdul Hamid, Kareem Darwish
  • Patent number: 9098211
    Abstract: Non-disruptive data migration from a source array to a destination array entails generating a virtual array spanning at least one destination array for receiving a copy of all data at the source array. The virtual array has at least as many virtual ports as physical source ports of the source array and at least as many logical units (LUNs) as the source array. Each source array LUN corresponds to a virtual array LUN and equals the storage capacity of that corresponding LUN. Each virtual port has a virtual port address. All data resident in the LUNs of the source array are copied to corresponding LUNs in the virtual array. A name server database is reconfigured to associate port names of the physical source ports with the virtual port addresses of the virtual ports such that the virtual array appears to a host as the source array.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 4, 2015
    Assignee: EMC Corporation
    Inventors: Kiran Madnani, Adi Ofer, Jeffrey A. Brown
  • Patent number: 9087066
    Abstract: A system manages a file directory containing data that is exposed by a file-server. The system provides a block-device layered on top of a network share that treats the underlying network share as read-only but allows local file-system semantics to operate on top of the network share. The end-result is a virtual disk containing a locally recognizable file-system that can read and write from the perspective of the operating system but where the data is store in the cloud as network shares. The virtual disk appears to be a fully functional local disk with all the expected local disk semantics.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: July 21, 2015
    Assignee: SWISH DATA CORPORATION
    Inventor: Soubir Acharya
  • Patent number: 9076507
    Abstract: A nonvolatile memory includes multiple banks, control logic and multiple read and write (RW) circuits. Each bank includes multiple memory cells. The control logic includes multiple storage units corresponding to the banks, respectively, and configured to output write enable signals and read enable signals to respective banks based on mode information stored in respective storage units. The RW circuits are connected to the banks, respectively, and are configured to independently enable or disable write and read operations of the respective banks in response to the write enable signals and the read enable signals of the respective banks. In an initial state after the mode information is stored in the respective storage units, the control logic activates the write enable signals and the read enable signals of the respective banks regardless of the mode information stored in the respective storage units.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: July 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chankyung Kim, Sangbo Lee, Seonghyun Jeon
  • Patent number: 9069467
    Abstract: Embodiments of the present invention relate to systems, methods, and computer storage media for concurrently maintaining a spanned virtual hard drive across two or more computer-storage media and a non-spanned virtual hard drive on one of computer-storage media. The method includes storing data of the spanned virtual hard drive across the computer-storage media utilizing volume spanning. While the spanned virtual hard drive is maintained on the computer storage media, the method includes storing data of the non-spanned virtual hard drive on one of the computer-storage media.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: June 30, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Naga Govindaraju, Mark Russinovich
  • Patent number: 9043773
    Abstract: Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed runtime environment (MRE) executed by a processing device, a notice of misprediction of optimized code, the misprediction occurring during a runtime of the optimized code, determining, by the MRE, whether a local misprediction counter (LMC) associated with a code region of the optimized code causing the misprediction exceeds a local misprediction threshold (LMT) value, and when the LMC exceeds the LMT value, compiling, by the MRE, native code of the optimized code to generate a new version of the optimized code, wherein the code region in the new version of the optimized code is not optimized.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Alejandro M. Vicente, Joseph M. Codina, Christos E. Kotselidis, Carlos Madriles, Raul Martinez
  • Patent number: 9026808
    Abstract: In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: May 5, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Mark W. Jetton, Thomas W. Liston
  • Patent number: 9003165
    Abstract: A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: April 7, 2015
    Inventors: Shlomo Selim Rakib, Marc Schaub
  • Patent number: 8972648
    Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to hypervisor, allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keerthi Kumar, Shailaja Mallya
  • Patent number: 8972647
    Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to a hypervisor; allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 8966152
    Abstract: According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 24, 2015
    Assignee: Cavium, Inc.
    Inventors: Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn, Najeeb I. Ansari
  • Patent number: 8937940
    Abstract: An approach is provided in which a virtual function, which executes on a network adapter, receives a data packet from a first virtual machine. A translation entry is identified that corresponds to sending the data packet from the first virtual machine to a second virtual machine, and a determination is made as to whether an onboard memory partition assigned to the virtual function includes the identified translation. If the onboard memory location includes the translation entry, the data packet is sent to the destination virtual machine using the translation entry retrieved from the onboard memory partition. Otherwise, if the translation entry is not located in the onboard memory partition, the data packet is sent to the destination virtual machine using a translation entry retrieved from an off board memory location.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Omar Cardona, Vinit Jain, Jayakrishna Kidambi, Renato J. Recio