Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Abstract: This disclosure describes systems, methods, and devices related to analyzing data stored in a relational database. A method may include installing a structured query language (SQL) server on a host server; installing statistical analysis modules on the host server; executing the statistical analysis modules within a relational database of the SQL server to analyze data stored in the relational database; and generating outputs based on the execution of the statistical analysis modules within the relational database.

Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.

Abstract: A control circuit includes a latching relay, a power loss activation circuit, and a watchdog circuit. A microcontrol unit (MCU) communicates with the watchdog circuit in a normal operation of the control circuit. As an action of a failsafe precaution in the event of a main power loss or a component failure, the MCU stops communicating with the watchdog circuit, at which point the watchdog circuit instructs the power loss activation circuit to continue operation of the control circuit. The control circuit further operates to implement mitigation operations in the event of a main power loss or component failure.

Abstract: A storage controller implemented on a System On Chip (SOC) includes an upstream functional module, a host interface, a logical to physical (L2P) interface, and a message inspection engine. The configured message inspection engine is obtained using one or more configuration settings and receives an input message from the upstream functional module. The input message is analyzed to determine a retention plan, a content modification plan, and a destination control plan. An output message is generated based at least in part on the input message, the content modification plan, and the destination control plan. If there is an affirmative content modification decision, the output message is populated with content absent from the input message. If there is an affirmative destination modification decision, the output message is populated with a destination absent from the input message. The output message is output unless there is an affirmative retention decision.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

Abstract: The present application discloses a method for processing a deallocation command and a storage device thereof. The disclosed method includes the following steps: in response to receiving the deallocation command, obtaining an address range indicated by the deallocation command; and updating the table items of the deallocation table according to the address range indicated by the deallocation command. Embodiments of the present application can reduce the delay in processing the deallocation command and reduce the impact of processing the deallocation command on the processing bandwidth of the IO command.

Abstract: A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.

Abstract: A computer-implemented method comprises a topological communications configurator (TCC) of a computing system determining a connections-optimized configuration of processors among compute nodes of the system. Processors included in the compute nodes can execute compute workers of an application of the system and can form intranodal segments of an internodal interconnection topology communicatively coupling the intranodal segments. The intranodal segments can be interconnected via an internodal interconnections fabric. The TCC can determine the connections-optimized configuration based on internodal communications costs corresponding to communications routes among the internodal segments via the internodal interconnection fabric. The computing system can comprise the TCC and can comprise a data-parallel computing system.

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

Abstract: Over the past several decades, rapid advances in semiconductors, automation, and control systems have resulted in the adoption of programmable logic controllers (PLCs) in an immense variety of environments. A synchronization system coordinates storage, retrieval, and activation of engineering object models among local and remote nodes. The synchronization system facilitates local and remote design and development access to the PLCs, as well as continued correct operation of the PLCs.

Abstract: With regard to a function group including all or some functions included in one of multiple binary codes stored in the memory device, a binary code including a first function that is executed at a first timepoint is loaded into a first memory area at a second timepoint that precedes the first time point, thereby minimizing the operation delay time of the memory system, and minimizing the overhead occurring in the processing of calling a specific function.

Abstract: Various implementations of the invention develop executable code for an embedded system, including a microcontroller and a device. Some implementations of the invention comprise a microcontroller development tool configured to operate on a general purpose computer.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing a read ID command to a flash module; and parsing an opcode of a reliable command from reserved bytes in reply data for the read ID command, where the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode.

Abstract: A method of managing a stack includes detecting, by a stack manager of a processor, that a size of a frame to be allocated exceeds available space of a first stack. The first stack is used by a particular task executing at the processor. The method also includes designating a second stack for use by the particular task. The method further includes copying metadata associated with the first stack to the second stack. The metadata enables the stack manager to transition from the second stack to the first stack upon detection that the second stack is no longer in use by the particular task. The method also includes allocating the frame in the second stack.

Abstract: Systems, methods, computer readable media and articles of manufacture consistent with innovations herein are directed to computer virtualization, computer security and/or memory access. According to some illustrative implementations, innovations herein may utilize and/or involve a separation kernel hypervisor which may include the use of a guest operating system virtual machine protection domain, a virtualization assistance layer, and/or a detection mechanism (which may be proximate in temporal and/or spatial locality to malicious code, but isolated from it), inter alia, for detection and/or notification of, and action by a monitoring guest upon access by a monitored guest to predetermined physical memory locations.

Abstract: A serial peripheral interface circuit includes a serial peripheral interface device with a master-in-slave-out (MISO) line, a master-out-slave-in (MOSI) line, a serial clock (SCLK) line and a slave select (SS) line, a first conducting line, a second conducting line, a first resistor connecting the MISO line and the first conducting line, and a second resistor connecting the MOSI line and the second conducting line.

Abstract: The invention relates to an electronic system, comprising components and/or units of various kinds, hence the electronic system can be called a heterogeneous system. The invented electronic system can be applied in the electric system digital control domain and in particular it is targeting (but not limited to) control of power train of pure electric or hybrid vehicle electric motors that require hard real time and safe control.

Abstract: An obfuscation circuit relies on a tamper-resistant nonvolatile memory which encodes a trusted Boolean function. The Boolean function is used to enable several operations relating to circuit obfuscation, including obfuscation of logic circuitry, obfuscation of operand data, and release of IP blocks. The tamper-resistant nonvolatile memory is part of a trusted integrated circuit structure, i.e., one fabricated by a trusted foundry, separate from another integrated circuit structure which contains the various operational logic circuits of the design and is fabricated by an untrusted foundry. The Boolean function is encoded based on a look-up table implemented as a cascaded multiplexer circuit. Multiple obfuscation functions can be so encoded. The obfuscation functions may be reprogrammed using a protocol that relies on symmetric keys, one of which is stored in the tamper-resistant nonvolatile memory.

Abstract: A method of testing a memory device includes steps as follows. Commands that meet a specification of the memory device are used. A random decision is performed on the plurality of commands to generate varied patterns, so that a testing device can test the memory device according to the varied patterns, where each of the varied patterns includes a sequence of one or more commands randomly selected from the plurality of commands.

Abstract: A method for managing Internet Protocol Version 6 (IPv6) addresses in a wireless sensor network is provided that includes storing, on a wireless sensor device in the wireless sensor network, a prefix of an IPv6 address in association with a key, forming an address indicator for the IPv6 address, the address indicator consisting of the key and a node address of the IPv6 address, and storing the address indicator in at least one memory location on the wireless sensor device in lieu of the IPv6 address.

Abstract: In one embodiment, a method includes starting a network-coordination service, a network-interface component, and an application as separate processes within a user space of an operating system of a device; receiving, by the network-coordination service, a request from the application to connect with a host; selecting, by the network-coordination service and in response to the request, the network-interface component to service the requested connection with the host, the network-interface component is associated with a network interface; allocating, by the network-coordination service, a shared memory region for the application and the network-interface component, the shared memory region is associated with a reference; and sending, by the network-coordination service, the reference to the application, the reference is configured to be used by the application to access the shared memory region, and the shared memory region is configured to be used by the application and the network-interface component to commu

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

Abstract: Various implementations of the invention develop executable code for an embedded system, including a microcontroller and a device. Some implementations of the invention comprise a microcontroller development tool configured to operate on a general purpose computer.

Abstract: A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.

Abstract: Utilizing a storage replica data structure includes receiving, at a hyper-kernel running on a computing node in a plurality of interconnected computing nodes, an indication of an operation pertaining to at least one of a guest physical memory address or a stable storage address. A guest operating system is run on a virtual environment that is defined by a set of hyper-kernels running on the plurality of interconnected computing nodes. It further includes updating a storage replica data structure. The storage replica data structure comprises a set of entries. The set of entries in the storage replica data structure comprises associations among guest physical memory addresses, physical memory addresses, and stable storage addresses.

Abstract: A method and system for detection, classification and prediction of user behavior trends using correspondence analysis is disclosed. The methods and systems reduce the n-dimensional feature space to a lower dimensional space for easy processing, improved quality of emerging clusters and superior prediction accuracies. Further, the method applies the correspondence analysis so that each user is assigned with a new coordinate in the lower dimension, which maintains a similarity, difference and the relationship between the variables. Once the correspondence analysis is completed, clustering or grouping of the coordinates based on the similar trends of the users is performed. Further, unlabeled cluster members are assigned class membership proportional to the labeled samples in the cluster. Finally, the method predicts the future actions of the users based on the past trends that are observed from the labeled clusters.

Abstract: A blockchain integrated station receives a configuration instruction after accessing a blockchain network. The blockchain integrated station configures, based on the configuration instruction, a first network address corresponding to a certificate authority center and a second network address corresponding to a first blockchain node in the blockchain network. The blockchain integrated station initiates an authentication request to the certificate authority center based on the first network address. The blockchain integrated station receives, from the certificate authority center, a digital certificate after the certificate authority center determines that the authentication request passes verification. The blockchain integrated station sends, based on the second network address, the digital certificate to the first blockchain node, where the digital certificate is used by the first blockchain node to add the blockchain integrated station as a new blockchain node in the blockchain network.

Abstract: The present application discloses a method for processing a deallocation command and a storage device thereof. The disclosed method includes the following steps: in response to receiving the deallocation command, obtaining an address range indicated by the deallocation command; and updating the table items of the deallocation table according to the address range indicated by the deallocation command. Embodiments of the present application can reduce the delay in processing the deallocation command and reduce the impact of processing the deallocation command on the processing bandwidth of the IO command.

Abstract: Methods and apparatuses for memory device mode selection in a serial memory device are presented. Memory device configuration information may be retrieved in response to a memory device initialization condition, and a configuration register bit mask that is included in the memory device configuration information may then be written to a configuration register of the memory device. A write command that may also be included in the memory device configuration information may be used to write the configuration bit mask to the configuration register. The serial memory device may be a serial flash memory. The configuration register bit mask may include an I/O mode bit setting that indicates enabling the memory to operate in a quad-bit I/O mode or other multi-bit serial I/O mode instead of a single-bit serial I/O mode.

Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration da

Abstract: A firmware updating method applicable to an electronic device is provided. The electronic device comprises a non-volatile memory comprising a firmware partition and a spare partition. The firmware updating method comprises: executing an auxiliary firmware, wherein the firmware partition comprises a first block and a second block, and the auxiliary firmware is in the first block and comprises a disk partition table of the non-volatile memory; receiving a system update file corresponding to a system firmware of the electronic device; and when a storage space required by the system firmware is larger than an available storage space, writing the system firmware into the second block of the firmware partition and a spare block of the spare partition according to the disk partition table and the system update file.

Abstract: A memory system includes a memory device including plural memory blocks divided into a system region, a user data region and a reserved region. The system region includes a first block storing original firmware and a second block storing copied firmware, and the reserved region includes a dedicated test block having an operational characteristic that substantially the same as that of the second block. The memory system includes a controller configured to access the dedicated test block for determining a status of the second block based on an operation state of the dedicated test block, and to update both the dedicated test block and the second block based on the status of the second block.

Abstract: A method is provided for validating a compiler-generated program portion that forms an optimized runnable code relative to an input runnable code. The method computes respective data sets used by the compiler-generated program portion. The respective data sets include (i) memory inputs UM, (ii) constant data memory areas UM_CONST, (iii) output memory areas DM, and (iv) output registers DR. The method copies the compiler-generated program portion to another memory area from a current memory area and appends a return instruction back to the current memory area at each exit point of the compiler-generated program portion. The method computes minimum and maximum base register offsets for base registers, from a union formed from a subset of the respective data sets. The method computes an allocation size for each of the base registers and an address assigned to each of the base registers.

Abstract: A virtualized storage for use in performing dynamic analysis of a sample is configured, at least in part by copying the sample to the virtualized storage. A virtual machine emulator is launched using a snapshot of a virtualized platform. A location of the copied sample in an image corresponding to the virtualized storage is determined, at least in part by identifying an offset. The copied sample is installed and dynamic analysis is performed on the sample.

Abstract: A virtualized storage for use in performing dynamic analysis of a sample is configured, at least in part by copying the sample to the virtualized storage. A virtual machine emulator is launched using a snapshot of a virtualized platform. A location of the copied sample in an image corresponding to the virtualized storage is determined, at least in part by identifying an offset. The copied sample is installed and dynamic analysis is performed on the sample.

Abstract: Provided are a method for multiple accesses in a memory, an apparatus supporting multiple accesses in the memory and a storage system. The method comprises: receiving a number N of addresses in the memory, wherein N is an integer larger than 1 and the number N of addresses are discontinuous; performing a preset operation according to the number N of addresses; and outputting the result of the operation. As a consequence, the performances of a computer system can be improved, and a user can input and use the desired addresses just as required by the user.

Abstract: A hypervisor associates a combined register space with a virtual device to be presented to a guest operating system of a virtual machine, the combined register space comprising a default register space and an additional register space. Responsive to detecting an access of the additional register space by the guest operating system of the virtual machine, the hypervisor performs an operation on behalf of the virtual machine, the operation pertaining to the access of the additional register space.

Abstract: Systems and devices for coordinating heterogeneous processes of a software application to comply with multiple address spaces or other computing system constraints are disclosed. In an example, operations for coordinating data processing among multiple processes of a software application include: executing a first process of the software application, as the first process operates with a first capability that is limited to an operational constraint of the computing system; initiating a second process of the software application, as the second process is initiated as a child of the first process, and as the second process operates with a second capability that exceeds the operational constraint of the computing system; communicating data from the first process of the software application to the second process; and receiving data from the second process of the software application, in response to the data being processed by the data analysis operations of the second process.

Abstract: Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.

Abstract: An operating system (OS) receives a request to allocate a physical memory page to an address space of an application. The OS maintains a data structure that stores references to a plurality of physical memory pages that are available to be allocated, and generates a random index into the data structure, wherein the random index comprises a random number, and wherein the random index corresponds to a first reference for a first physical memory page of the plurality of physical memory pages. The OS selects the first physical memory page of the plurality of memory pages from the data structure using the random index, and maps the first physical memory page to the address space of the application.

Abstract: One or more configuration state registers are provided in-memory rather than in-processor. A request to access a configuration state register is obtained. A determination is made that the configuration state register is in-memory rather than in-processor. Based on determining that the configuration state register is in-memory, the access is converted from an in-processor access operation to an in-memory access operation.

Abstract: A system comprising a computer processor comprising a plurality of registers, a load-store unit configured to load data in at least one of the plurality of registers, and a memory. The memory includes a memory location mapped to a first virtual memory address and a second virtual memory address. Issuance of a load from the memory location via the first virtual memory address causes execution of a side effect. The memory also includes a computer program containing programming instructions that, when executed by the computer processor, performs an operation that includes storing a predetermined data value at the memory location, and testing the memory for errors during load operations.

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

Abstract: The present invention is related to a method for high volume logging for large scale network address translation. A first device intermediary to a plurality of clients and a plurality of database servers allocates a portion of memory to each packet engine in a plurality of packet engines executing on a respective core of a plurality of cores of the first device. The first device establishes large scale network address translation (LSN) for the plurality of clients, the first device logging LSN information of sessions to a corresponding logging buffer established in a respective packet engine's portion of memory. The first device identifies, for a LSN session, a packet engine from the plurality of packet engines to log the information for the LSN session and stores information of the LSN session to the logging buffer in the packet engine's portion of memory.

Abstract: A solid state drive (or other non-volatile storage device) includes a plurality of non-volatile storage elements arranged in blocks (or other units). Blocks (or other units) can be individually switched between analytics mode and I/O mode. The SSD (or other non-volatile storage device) performs in-drive data analytics for blocks in analytics mode while blocks in I/O mode are available for concurrent I/O operations.

Abstract: Systems and procedures are provided to enable large size fixed block architecture (FBA) device support over FICON. The FBA devices may have a size greater than 2 terabytes. For example, in known storage systems, an FBA device size may be 64 terabytes and an architecture provided for 512-terabyte devices, and the described system supports such large, or even larger, FBA devices. The system may be used with existing fixed block command sets.

Abstract: A computer system has: a virtual machine operating on a physical machine; and a management block operating on the physical machine and managing the virtual machine. The virtual machine has a specific function processing module that performs specific function processing with respect to a packet for transmission and a received packet. The management block has a virtual switch that relays a packet transmitted and received by the virtual machine. The virtual switch has an offload processing block that performs the specific function processing if the specific function processing is offloaded to the management block. If the specific function processing is offloaded from the virtual machine to the management block, the specific function processing module notifies the management block of processing information required for the specific function processing, and the offload processing block executes the specific function processing based on the processing information received from the virtual machine.

Abstract: Various aspects provide for optimizing memory mappings associated with network nodes. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The second network node receives the memory page request in response to a determination that the second network node comprises a memory space associated with the memory page request. The first network node also maps a memory page associated with the memory page request based on a set of memory page mappings stored by the first network node.