Abstract: A new approach contemplates systems and methods to support control of power consumption of a memory on a chip by throttling port access requests to the memory via a memory arbiter based on a one or more programmable parameters. The memory arbiter is configured to restrict the number of ports being used to access the memory at the same time to be less than the available ports of the memory, thereby enabling adaptive power control of the chip. Two port throttling schemes are enabled—strict port throttling, which throttles the number of ports granted for memory access to be no more than a user-configured maximum throttle port number, and leaky bucket port throttling, which throttles the number of ports granted for the memory access down to be within a range based on a number of credit tokens maintained in a credit register.

Abstract: Techniques manage a storage system. In accordance with such techniques, an access request for target data is received; a storage position of the target data is determined, the storage position indicating one of a storage device and a cache; a target element corresponding to the target data is determined from a first replacement list and a second replacement list associated with the first replacement list based on the storage position, the first replacement list including at least a counting element, the counting element indicating an access count of data in the storage device, the second replacement list including a low-frequency access element, the low-frequency access element indicating a cache page with a low access frequency in the cache; and a position of the target element in a replacement list where the target element exist is updated. Therefore, the overall performance of the storage system can be improved.

Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.

Abstract: Synchronization events associated with cache coherence are monitored without using invalidations. A callback-read is issued to a memory address associated with the synchronization event, which callback-read either reads the last value written in the memory address or blocks until a next write takes place in the memory address and reads a newly written value.

Abstract: A self-correcting secure computer system is provided. The computer system includes a read-only memory (ROM) device, a random access memory (RAM) device, and at least one processor in communication with the ROM device and the RAM device. The at least one processor is programmed to receive an activation signal; retrieve, from the ROM device, data to execute an operating system; execute, on the RAM device, the operating system based on the data from the ROM device; receive a clear RAM signal; end execution of the operating system on the RAM device; and depower the RAM device such that all data on the RAM device is deleted.

Abstract: An input/output delay optimization method, used in an electronic system comprising a host controller and a memory device. The method comprising: switching the memory device from a first mode to a second mode a high power consumption mode of the memory device; transmitting one or more first read commands to the memory device, wherein the one or more first read commands are transmitted according to different output delay values; determining an optimized output delay value according to the response status of memory device for the one or more first read commands; transmitting one or more second read commands to the memory device, wherein the one or more second read commands are transmitted according to the optimized output delay value; receiving a known data from the memory device according to different input delay values; and determining an optimized input delay value according to the correctness of the received known data.

Abstract: A semiconductor storage apparatus capable of realizing continuous read with high speed is provided. A continuous read method of a NAND flash memory includes: a step for holding setting information related to a read time of a memory cell array in continuous read in a register; a step for reading data from the memory cell array in the read time based on the setting information; a step for holding the read data in a latch (L1) and a latch (L2); and a step for outputting the data held synchronously with an external clock signal corresponding to the setting information.

Abstract: A computing system includes a host and a storage device. The host includes a central processing unit (CPU) and a first volatile memory device. The storage device includes a second volatile memory device and a nonvolatile memory device. The CPU uses the first volatile memory device and the second volatile memory device as a main memory to store temporary data used for operation of the CPU. The CPU determines a swap-out page to be swapped-out of first pages stored in the first volatile memory device, determines a swap-in page to be swapped-in of second pages stored in the second volatile memory device, and exchanges the swapped-out page and the swapped-in page.

Abstract: A system receives vehicle metric data from a gateway device connected to a vehicle. The vehicle gateway device gathers data related to operation of the vehicle and/or location data. The system receives data from multiple vehicles in a fleet. The vehicle gateway device gathers vehicle metric data at a high frequency. Instead of transmitting a large amount of vehicle metric data at a fine level of granularity, the vehicle gateway device aggregates and buckets the vehicle metric data over a period of time (such as, every five minutes). The system uses the bucketed data for fleet management analysis.

Abstract: Systems, apparatuses, and methods for performing coherence processing and memory cache processing in parallel are disclosed. A system includes a communication fabric and a plurality of dual-processing pipelines. Each dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. The communication fabric forwards a transaction to a given dual-processing pipeline, with the communication fabric selecting the given dual-processing pipeline, from the plurality of dual-processing pipelines, based on a hash of the address of the transaction. The given dual-processing pipeline performs a duplicate tag lookup in parallel with a memory cache tag lookup for the transaction. By performing the duplicate tag lookup and the memory cache tag lookup in a parallel fashion rather than in a serial fashion, latency and power consumption are reduced while performance is enhanced.

Abstract: A method for operating a memory system includes determining whether a recovery operation is performed, when power is supplied after being interrupted, generating an internal command for checking an operation status of a memory device when a recovery operation starts, accessing at least one open memory block in the memory device in response to the internal command, checking an operation status of the at least one open memory block, programming a preset amount of dummy data on a preset number of blank pages from a boundary programmed page in the at least one open memory block, and restoring data associated with the recovery operation in the at least one open block.

Abstract: An example apparatus comprises a drive carrier assembly which may include a memory device, and an energy storage device having at least a portion thereof encased in a housing. In some examples, the apparatus may include a printed circuit assembly to detect a power failure of a host computing device. The printed circuit assembly, may have a first portion coupled to the energy storage device and a second portion coupled to a backplane of the host computing device.

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

Abstract: A system for parallel computing leveraging the use of a key value solid state drive. The system including a modified set of compiler directives that enable the use of parallel compute and data threads. The system may further include a concurrency manager to ensure that the parallel data threads are operated in a thread-safe manner.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory package and the controller may be a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus.

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

Abstract: Implementations described and claimed herein provide methods and systems for routing data, message, and register access transactions through common ports in an on-chip interface interconnect module while supporting Quality of Service (QoS) and maintaining fair data throughput. In one implementation, a System on Chip system includes an AXI interconnect module to route data, message, and register access transactions via common ports in the AXI interconnect module. The system may include at least one master circuit module configured to initiate data transaction, wherein the at least one master circuit module behaves as a slave to receive message transactions and register access transactions. The system may include at least one slave circuit module configured to respond to data transactions, wherein the at least one slave circuit module behaves as a master to initiate message transactions. The system may use QoS signaling as a priority indicator to prioritize the transactions.

Abstract: Techniques are directed to reading data. Such techniques involve in response to receiving a read request for the target data, determining that target data is stored in both a first storage device and a second storage device. Such techniques further involve determining at least one of reliability and access load for each of the first storage device and the second storage device. Such techniques further involve: determining, based on the at least one of the reliability and the access load, one of the first storage device and the second storage device as a target storage device so as to respond to the read request. By means of certain techniques, at least one of the access load and service lives is balanced between storage devices so as to improve the efficiency of data read and the overall performance of a storage system.

Abstract: In response to receiving a request to perform a transaction with two or more memory operations on one or more tiered data structures, the memory controller: writes a start transaction record to the log stream including a transaction identifier corresponding to the transaction; and performs the two or more memory operations. For a first memory operation associated with a key, the memory controller: writes a new data object in a datastore; assigns, in a key-map, a location of the new data object to the key; maintains an old data object in the datastore whose location was previously assigned to the key; and writes an operation commit record to a log stream upon completion of the first memory operation. In accordance with a determination that the two or more memory operations are complete, the memory controller writes a transaction commit record to the log stream including the transaction identifier.

Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.

Abstract: A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.

Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.

Abstract: A magnetic data recording system utilizing different magnetic memory element types to optimize competing performance parameters in a common memory chip. The memory system includes a first memory portion which can be a main memory and which includes magnetic memory elements of a first type, and a second memory region which can be a temporary memory region and which includes magnetic memory elements of a second type. A memory controller can be provided for controlling the input and retrieval of data to and from the first and second memory elements. The second, memory region can be a scratchpad memory or could also be cache type memory. The first type of magnetic memory elements can be designed for high data retention, whereas the second type of magnetic memory elements can be designed for fast write speed (low latency) and low write power consumption.

Abstract: Hardware for speeding up MCMC is realized. An information processing apparatus includes a plurality of Ising chips and a controller that controls the plurality of Ising chips. Each of the plurality of Ising chips includes a plurality of units, and each of the plurality of units retains a spin state. The controller instructs one set of Ising chips among the plurality of Ising chips to compare values of spin states of corresponding units and instructs the one set of Ising chip to invert values of a portion of spins among spins having different values of spin states of the corresponding units.

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. The I/O request may be processed as a write miss I/O. One or more dirty pages associated with the write miss I/O may be placed into a tree according to a key. It may be determined whether one of a first event and a second event occurs. A data flush may be triggered for the tree when the first event occurs, and the data flush may be triggered for the data flush for the tree when the second event occurs.

Abstract: An information handling system may include a resistive memory buffer to supplement a system main memory unit of the information handling system. A processor of the information handling system may map the resistive memory buffer as system memory, along with the system main memory unit. The processor may use the system memory, including the resistive memory buffer and the system main memory unit in executing one or more applications. The resistive memory buffer may improve performance of the information handling system, such as during hibernation and wake-up processes and memory flush processes.

Abstract: A controller may include: a ROM code register configured to generate and store a ROM code including a plurality of firmware images; and a ROM controller configured to change an operation setting of a ROM based on an operation firmware image of the plurality of firmware images, wherein each of the plurality of firmware images includes an image header including attribute information on a corresponding firmware image and image data, and wherein the operation firmware image includes, as its image header, an operation image header, which includes an operation mode field indicating whether the operation setting of the ROM is changed, and, as its image data, operation image data including information on the operation setting of the ROM.

Abstract: A memory system may include a volatile memory, a nonvolatile memory, and a controller. The controller may copy data from a memory to the other memory. The controller may include a page hit detection circuit and a page requester. The page hit detection circuit may generate information regarding page hit and page miss according to whether page information requested from a host and page information of the nonvolatile memory loaded in the volatile memory correspond to each other. The page requester may perform page swapping and transmit a ready response signal to the host.

Abstract: The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the array includes a counter corresponding to one of the plurality of designated subsets of memory cells. The memory device is configured to receive input corresponding to a data batch, where the input includes a designation that corresponds to the one of the plurality of designated subsets of memory cells to be conditionally updated, and to change a numerical value stored by the counter corresponding to the one of the plurality of designated subsets of memory cells.

Abstract: Systems and techniques for collecting and using merge tree garbage metrics are described herein. A kvset is created for a node in a KVS tree. Here, a set of kvset metrics for the kvset are computed as part of the node creation. The kvset is added to the node. The node is selected for a compaction operation based on a metric in the set of kvset metrics. The compaction operation is performed on the node.

Abstract: An example system includes a plurality of execution units, a shared resource, and an allocation control circuit. Each execution unit may generate a resource allocation request that includes a resource allocation size. The allocation control circuit may select a particular resource allocation request from the plurality of resource allocation requests, and determine an availability, based on an allocation register, of contiguous resource blocks within the shared resource. In response to determining that a number of the contiguous resource blocks satisfies a requested allocation size, the allocation control circuit may select an address corresponding to a particular resource block of the one or more contiguous resource blocks, and allocate the resource blocks to a corresponding execution unit. In response to a beginning of a second system clock cycle, the allocation control circuit may also update the allocation register based on the selected address and the requested allocation size.

Abstract: A method, non-transitory computer readable medium and storage controller computing device that receives a read request from a client device. Data corresponding to the read request is retrieved from a flash cache comprising local flash memory. The data is returned to the client device in response to the read request. A determination is made when the data is stored in a flash pool. The flash pool comprises a plurality of solid state drives (SSDs). The data is inserted into the flash pool, when the determining indicates that the data is not stored in the flash pool. With this technology, a flash pool is populated based on hits in a flash cache. Accordingly, flash cache is utilized to provide low latency reads while the most important data is preserved in the flash pool to be used by another storage controller computing device in the event of a failover.

Abstract: A first receiver device receives, from a sender device in a unicast communication, a data flow including a multicast identifier, the multicast identifier indicating that the data flow is to reach multiple receiver devices. The first receiver device determines that the data flow is to reach multiple receiver devices in response to detecting the multicast identifier. The first receiver device sends, to a second receiver device in a unicast communication, the data flow including the multicast identifier.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.

Abstract: The present disclosure directs to solutions for performing deduplication by a storage device. In the solutions, according to a duplicate data locality principle, non-duplicate data blocks whose logical addresses are contiguous are stored in contiguous physical addresses in a sequence of the logical addresses, and fingerprints of the non-duplicate data blocks whose logical addresses are contiguous are also stored in contiguous physical addresses in the sequence of the logical addresses, and in addition, a mapping from a logical address, which is of one data block in the non-duplicate data blocks whose logical addresses are contiguous, to an aggregation address is established.

Abstract: A Memory Device (MD) includes a configurable Non-Volatile Memory (NVM) including a first memory array and a second memory array. The configurable NVM stores temporary data designated for volatile storage by a Central Processing Unit (CPU) and persistent data designated for non-volatile storage by the CPU. An address is associated with a first location in the first memory array and with a second location in the second memory array. In performing a command to write data for the address, it is determined whether to write the data in the second location based on a volatility mode set for the MD. According to another aspect, a CPU designates a memory page in a virtual memory space as volatile or non-volatile based on data allocated to the memory page, and defines the volatility mode for the MD based on whether the memory page is designated as volatile or non-volatile.

Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

Abstract: Cache memory for resistive switching memory modules is provided herein. The cache memory can reside on a separate DIMM from the resistive switching memory, in some embodiments, or can share a common DIMM with the resistive switching memory. Cache management protocols are provided to service read and write policies for managing interaction of data between the cache memory and the resistive switching memory. In various embodiments, memory controllers are optimized for physical characteristics of resistive switching memory, and cache management protocols can be implemented to take advantage of these characteristics.

Abstract: An example of a system includes a host interface, a set of non-volatile memory cells, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to access a host memory through the host interface by sending host memory access requests for two or more blocks of host data according to an interleaving scheme.

Abstract: An apparatus includes a memory card that includes at least one memory module and an expansion connector to connect with at least one expansion memory card. A lane distributor on the memory card interfaces with a set of bidirectional lanes and provides a base lane set and an expanded lane set of bidirectional lanes to support communications with the memory module and the expansion memory card via the expansion connector.

Abstract: A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected memory cell among the resistive memory cells, based on a write command; and a memory controller suitable for providing the write command with the write data to the peripheral circuit and scheduling the write command based on an amount of power consumption calculated depending on the number of either low bits or high bits in the write data.

Abstract: In one implementation, a memory module with on-die error correction code (ECC) with scrub operation capabilities and a programmable patrol scrub period is coupled to a memory controller that causes error correction operations to perform based on a power status of an energy storage device.

Abstract: A memory system has a first memory which comprises a nonvolatile memory data region, and a second memory which stores data before storing in a third memory, the data not being written back on the third memory in a lower-level with access priority lower than access priority of the first memory, among data inside the nonvolatile memory data region, wherein the second memory has a bit error rate lower than a bit error rate of the first memory.

Abstract: A memory module includes memory devices; data buffers suitable for receiving write data transferred from a memory controller and transmitting read data to the memory controller; a buffer control signal generation circuit suitable for generating buffer control signals for controlling the data buffers, by using a command transferred from the memory controller; a command delay circuit suitable for generating an effective command by delaying the command by a delay amount of the buffer control signal generation circuit in a read operation and a write operation; a data processing circuit suitable for processing write data transferred from the data buffers and transferring processed write data to the memory devices, and processing read data transferred from the memory devices and transferring processed read data to the data buffers, in response to the effective command; and a command buffer circuit suitable for transferring the effective command to the memory devices.

Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request for data. A number of storage devices of a plurality of storage devices in a Mapped RAID group that will be used to process the I/O request may be determined. It may be determined that an amount of I/O credits available for the number of storage devices is insufficient. The amount of I/O credits available for the number of storage devices to process the I/O request may be tuned dynamically based upon, at least in part, determining that the amount of I/O credits available for the number of storage devices is insufficient.