Solid-state Random Access Memory (ram) Patents (Class 711/104)
  • Patent number: 9430402
    Abstract: The described implementations relate to computer memory. One implementation provides a technique that can include providing stealth memory to an application. The stealth memory can have an associated physical address on a memory device. The technique can also include identifying a cache line of a cache that is mapped to the physical address associated with the stealth page, and locking one or more other physical addresses on the memory device that also map to the cache line.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: August 30, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Marcus Peinado, Taesoo Kim
  • Patent number: 9405697
    Abstract: A method for managing memory using a virtual memory manager includes receiving a memory allocation request, allocating memory of a physical address space in response to the memory allocation request, mapping an address value of the memory allocated in the physical address space to consecutive primary virtual address space, and mapping the address value of the primary virtual address space to one of a first and second secondary virtual address spaces to process a new memory allocation request in a situation where memory a fragmentation occurs. Other embodiments are also disclosed. The methods and apparatuses of the present disclosure are capable of moving active memory blocks of the fragmented virtual memory space to another virtual memory space to resolve the memory fragmentation even when a memory fragmentation occurs.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: August 2, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Kyu Koo, Sang-Bok Han, Myung Sun Kim, In Choon Yeo
  • Patent number: 9384807
    Abstract: A parameter setting circuit includes a first parameter setting unit configured to set a first parameter using first code signals generated by adjusting a value of parameter information to conform to a gear-down mode; a second parameter setting unit configured to generate pre-code signals by adjusting a value of the first code signals to conform to a specification of a second parameter, and set the second parameter using second code signals generated by adjusting a value of the pre-code signals according to a control signal; and a control section configured to generate the control signal according to whether it is the gear-down mode and whether the value of the first code signals is an odd number.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 5, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jae Il Kim
  • Patent number: 9311252
    Abstract: Logically arranged hierarchy or tiered storage may comprise a layer of storage being a faster access storage (e.g. solid state drive (SSD)) and another (e.g., next) layer being a traditional disk (e.g. HDD). In one embodiment, compaction occurs within the higher layer, e.g., until there is no more room and then during the compaction sequence the data may be moved down to the lower layer. In another embodiment, compaction and migration to a lower layer may occur within the higher layer, e.g., based on one or more policies, even if the higher layer is not full. In one embodiment, the data between layers are maintained as disjoint. In one embodiment, the more recent versions are always in the higher layer and the older versions are always in the lower layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Liana L. Fong, Wei Tan
  • Patent number: 9298602
    Abstract: For nonvolatile random access memory (NVRAM) use, a query module identifies persistent data on a NVRAM in response to waking the NVRAM. A management module makes available the persistent data for use.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 29, 2016
    Assignee: Lenovo (Singapore) PTE. LTD.
    Inventor: Mark Charles Davis
  • Patent number: 9286208
    Abstract: According to one embodiment, a controller includes a first command queuing part corresponding to a first bank, the first command queuing part queuing a first command, a second command queuing part corresponding to a second bank, the second command queuing part queuing a second command, and a command execution control part which is configured to generate a first sub-command sequence based on a group of commands in the first command, generate a second sub-command sequence based on a group of commands in the second command, and determine whether or not to execute the first and second sub-command sequences in parallel as an interleave operation between the first and second banks, by comparing an additional value of a first numeric converted parameter of the first sub-command sequence and a second numeric converted parameter of the second sub-command sequence with a threshold data.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 15, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takashi Ide
  • Patent number: 9244836
    Abstract: A memory system distributes across multiple pages of a flash memory bits of a DRAM data word, the data word having a number of bits equal to a width of a row of a DRAM memory, and the bits of the data word all from a same row of the DRAM memory.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: January 26, 2016
    Assignee: AgigA Tech Inc.
    Inventor: Ronald H. Sartore
  • Patent number: 9225662
    Abstract: Embodiments of the present invention provide an approach for identifying commands for virtual resource instances in a networked computing environment (e.g., a cloud computing environment). Specifically, in a typical embodiment, a set of commands for an instance of a virtual resource may be received in a computer memory medium or the like. The commands may then be analyzed and information pertaining to the commands may be stored in a computer storage device or the like. When a user/requester later wishes to identify a command to be utilized for another instance of the virtual resource, the requester can access the information and make a determination as to what commands are typically utilized for similar and/or previous instances of the virtual resource.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: December 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kelly Abuelsaad, Kulvir S. Bhogal, Lisa Seacat Deluca, Soobaek Jang
  • Patent number: 9208084
    Abstract: A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 8, 2015
    Assignee: Oracle America, Inc.
    Inventors: Sanjiv Kapil, Ricky C. Hetherington
  • Patent number: 9189047
    Abstract: Embodiments of the invention provide techniques for optimizing database queries for energy efficiency. In general, a query optimizer is configured to compare energy requirements of query plans, and to select a query plan requiring minimal energy to execute. In one embodiment, the query optimizer may also compare time performance of the query plans, and may select a query plan by matching to a user preference for a relative priority between energy requirements and time performance.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Bestgen, Wei Hu, Shantan Kethireddy, Andrew P. Passe, Ulrich Thiemann
  • Patent number: 9117493
    Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address-data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical space for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: August 25, 2015
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 9064603
    Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Youn, Su-A Kim, Hyo-Jin Choi, Chul-Woo Park, Hak-Soo Yu
  • Publication number: 20150149713
    Abstract: An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Nvidia Corporation
    Inventors: Michael Asbury Woodmansee, J. Arjun Prabhu
  • Patent number: 9043785
    Abstract: A method and apparatus are disclosed of monitoring a number of virtual machines operating in an enterprise network. One example method of operation may include identifying a number of virtual machines currently operating in an enterprise network and determining performance metrics for each of the virtual machines. The method may also include identifying at least one candidate virtual machine from the virtual machines to optimize its active application load and modifying the candidate virtual machine to change its active application load.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 26, 2015
    Assignee: Open Invention Network, LLC
    Inventor: John Michael Suit
  • Patent number: 9037854
    Abstract: A privileged cryptographic service is described, such as a service running in system management mode (SMM). The privileged service is operable to store and manage cryptographic keys and/or other security resources in a multitenant remote program execution environment. The privileged service can receive requests to use the cryptographic keys and issue responses to these requests. In addition, the privileged service can measure the hypervisor at runtime (e.g., either periodically or in response to the requests) in an attempt to detect evidence of tampering with the hypervisor. Because the privileged service is operating in system management mode that is more privileged than the hypervisor, the privileged service can be robust against virtual machine escape and other hypervisor attacks.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: May 19, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Gregory Branchek Roth, Nachiketh Rao Potlapally
  • Patent number: 9037788
    Abstract: Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: John Rudelic, August Camber
  • Patent number: 9032134
    Abstract: A method of operating a memory system includes receiving a read command from a host, where the read command is associated with a logical sector of a memory, determining whether the logical sector of the memory is indicated as being erased in a sector allocation table, if the logical sector of the memory is indicated as being erased, outputting a data pattern from the sector allocation table to the host, and if the logical sector of the memory is not indicated as being erased, reading a physical sector of the memory and outputting data from the physical sector of the memory to the host.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sergey Anatolievich Gorobets
  • Patent number: 9032185
    Abstract: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Graham Kirsch
  • Publication number: 20150127897
    Abstract: Systems and methods for managing open tabs of an application are provided. In some aspects, a page is presented in a first tab from among multiple tabs open in an application at a computing device. That a content of the page presented in the first tab is different from a default content of the page stored at a web server is determined. Contents of the multiple tabs are retained in a random access memory (RAM). A request is received to reduce an amount of the RAM used by the application. The content of the page presented in the first tab is stored. In response to the request to reduce the amount of the RAM used by the application, a content presented in a second tab from among the plurality of tabs is removed from the RAM.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Google Inc.
    Inventor: Lane LIABRAATEN
  • Publication number: 20150121163
    Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Micron Technology, Inc.
    Inventor: Ramin Ghodsi
  • Publication number: 20150120995
    Abstract: When a read command is received from a host requesting data stored on a disk of a Data Storage Device (DSD), it is determined whether the DSD is in a startup period and whether the requested data is stored in a solid state memory of the DSD. The requested data is designated for storage in the solid state memory if it is determined that the DSD is in the startup period and the requested data is not stored in the solid state memory.
    Type: Application
    Filed: December 13, 2013
    Publication date: April 30, 2015
    Applicant: Western Digital Technologies, Inc.
    Inventors: ZAIHAS AMRI FAHDZAN HASFAR, CHOO-BHIN ONG
  • Patent number: 9021168
    Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: April 28, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert L. Horn, Sebastien A. Jean
  • Patent number: 9021176
    Abstract: A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory controller to which the memory device is connected. Alternatively, the memory controller can control the operation of the cache system.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventor: David Resnick
  • Patent number: 9021192
    Abstract: Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing a central manager responsible for receiving requests from media access requesters. In embodiments, the central manager updates requests with a physical address corresponding to a logical address for a request. In embodiments, the central manager is the only entity updating a mapping table and invalid page table for the system. In embodiments, the central manager may also throttle or prioritize requests originating from two or more requesters to change the ratio of requests executed from each requester.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: April 28, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ho-Fan Kang, Lan D. Phan
  • Patent number: 9015403
    Abstract: A method of controlling a storage device, the method including calculating, in a controller of the storage device, data throughput of the storage device in a current period, comparing, in the controller, the data throughput to a reference value and adjusting, with the controller, an operation performance of the storage device in a next period based on the comparison and a delay factor of a period prior the current period.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation
    Inventors: Jeonghoon Jeong, JiHong Kim, Sungjin Lee, Kyung Ho Kim, Sangmok Kim, Hyunchul Park, Otae Bae, Donggi Lee
  • Publication number: 20150106660
    Abstract: An apparatus can include a circuit board; a processor mounted to the circuit board; a storage subsystem accessible by the processor; random access memory accessible by the processor; a network interface; and a controller mounted to the circuit board and operatively coupled to the network interface where the controller includes circuitry to capture values stored in the random access memory, the values being associated with a state of the apparatus, and circuitry to transmit the values via the network interface. Various other apparatuses, systems, methods, etc., are also disclosed.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: Lenovo (Singapore) Pte. Ltd.
    Inventors: Nagananda Chumbalkar, Rod D. Waltermann
  • Patent number: 9009117
    Abstract: In accordance with embodiments, there are provided mechanisms and methods for creating, exporting, viewing and testing, and importing custom applications in a multitenant database environment. These mechanisms and methods can enable embodiments to provide a vehicle for sharing applications across organizational boundaries. The ability to share applications across organizational boundaries can enable tenants in a multi-tenant database system, for example, to easily and efficiently import and export, and thus share, applications with other tenants in the multi-tenant environment.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 14, 2015
    Assignee: salesforce.com, inc.
    Inventors: David Brooks, Lewis Wiley Tucker, Benji Jasik, Timothy Mason, Eric David Bezar, Simon Wong, Douglas Chasman, Tien Tzuo, Scott Hansma, Adam Gross, Steven Tamm
  • Publication number: 20150100722
    Abstract: A host including a controller configured to be connected to a storage device separate from the host. The controller is configured to maintain random access memory (RAM) code on the host, the RAM code configured to provide a destructive function, temporarily load the RAM code onto a volatile memory in the storage device during a manufacturing process, wherein the loaded RAM code, when executed by a processor in the storage device, is configured to cause the processor in the storage device to perform a destructive function on the storage device, and remove the loaded RAM code from the volatile memory after the manufacturing process, wherein the destructive function is unable to be performed by the processor when the loaded RAM code is removed from the volatile memory.
    Type: Application
    Filed: November 25, 2013
    Publication date: April 9, 2015
    Applicant: Western Digital Technologies, Inc.
    Inventor: MICHAEL W. WEBSTER
  • Patent number: 8996745
    Abstract: An output module for an industrial controller configurable to simplify setup and commissioning is disclosed. The output module includes configurable PWM outputs that may be scheduled to start at different times within the PWM period, that may be configured to generate a fixed number of PWM pulses, and that may have an extendable PWM period. The output terminals are configurable to enter a first state upon generation of a fault and further configurable to enter a second state after a configurable time delay following the fault being generated. The output module may receive inputs signals directly from another module and set output signals at the terminals responsive to these signals.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: March 31, 2015
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Eric D. Decker, Robert J. Kretschmann, Kenwood Hall, Andreas P. Frischknecht, Scott A. Pierce
  • Publication number: 20150089100
    Abstract: A method of operating a data transport system on a computing device is disclosed. The method comprises: writing outgoing data in a first memory space on a memory module of a computing device; detecting the outgoing data on the first memory space by a data channel component coupled to the memory module, wherein the first memory space is designated for external data transmission; and generating a transmission signal encoding the outgoing data, via the data channel component, for transmission from the memory module through an inter-device interconnect to an external memory module.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Inventors: Narsing Vijayrao, Jason Taylor
  • Publication number: 20150089125
    Abstract: Techniques are provided for performing parallel processing on in-memory objects within a database system. In one embodiment, a plurality of in-memory chunks are maintained on a plurality of non-uniform memory access (NUMA) nodes. In response to receiving a query, a set of clusters is determined for the plurality of in-memory chunks. Each respective cluster in the set of clusters corresponds to a particular NUMA node of the plurality of NUMA nodes and includes a set of one or more in-memory chunks from the plurality of in-memory chunks. For each respective cluster in the set of clusters, a query coordinator assigns, to the respective cluster, a set of one or more processes associated with the particular NUMA node that corresponds to the respective cluster.
    Type: Application
    Filed: July 21, 2014
    Publication date: March 26, 2015
    Inventors: NILOY MUKHERJEE, AMIT GANESH, VINEET MARWAH
  • Patent number: 8990493
    Abstract: A disk drive comprising a rotatable disk, a head actuated over the disk, and a controller is disclosed. The controller is configured to write a first force unit access write data to the cache as part of the cache data, write the first force unit access write data and a first metadata corresponding to the first force unit access write data to the first location by using the head, transmit a first write complete status to a host, and maintain the first force unit access write data in the cache as part of the cache data. The controller is also configured to store write data as part of the cache data. Furthermore, the controller is configured to write the cache data to a third location, and a metadata corresponding to the cache data to the disk.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 24, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Raymond Yu, Srinivas Neppalli, Brian E. Jones
  • Patent number: 8990475
    Abstract: A data storage device includes a NAND flash memory, an executable interface and a controller for receiving, from a host, via the executable interface, an instruction to access the NAND flash memory at a virtual address and for translating the virtual address to a physical address of the volatile memory. Preferably, the controller also provides boot functionality to the host.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: March 24, 2015
    Assignee: Sandisk IL Ltd.
    Inventors: Avraham Meir, Amir Mosek, Amir Lehr, Menahem Lasser
  • Patent number: 8990488
    Abstract: The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 24, 2015
    Assignee: Inphi Corporation
    Inventor: Christopher Haywood
  • Publication number: 20150081963
    Abstract: An interface of a receiving module in a FPGA chip receives data. The interface writes the data to a buffer of the receiving module, in which the buffer is implemented by a single piece of RAM of which a bit width is B-bit. A first sub-module of the receiving module reads B-bit data from the buffer each timeslot and writes the B-bit data to a data storage of a scheduling module in the FPGA chip, in which the data storage is formed by M pieces of RAM which are numbered in sequence, each of the M pieces of RAM is divided into address spaces which are numbered in sequence, and the timeslot is allocated by a timing generator of the scheduling module and a timeslot cycle is N. A second sub-module of the scheduling module reads data from the data storage, processes the data read out and sends the processed data.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 19, 2015
    Inventor: Bin Wang
  • Patent number: 8977822
    Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: David Resnick
  • Patent number: 8977806
    Abstract: One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module includes a number of super-stacks and a first interface configured to transmit data between the super-stacks and a memory controller. Each super-stack includes a number of sub-stacks, a super-controller configured to control the sub-stacks, and a second interface configured to transmit data between the sub-stacks and the first interface. Combining memory devices of different types allows utilizing the favorable properties of each type of the memory devices, while hiding their unfavorable properties from the memory controller.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: March 10, 2015
    Assignee: Google Inc.
    Inventors: Daniel L. Rosenband, Frederick Daniel Weber, Michael John Sebastian Smith
  • Publication number: 20150067246
    Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a plurality of state memories, a plurality tag memories, and a control circuit. Each of the state memories may be configured to store coherency state information for a cache memory of a respective plurality of coherent agents. Each of the tag memories may be configured to store duplicate tag information a cache memory of the respective plurality of coherent agents. The control circuit may be configured to receive a tag address, access tag information in each of the tag memories in parallel dependent upon the received tag address, determine, for each cache memory, new coherency state information for a cache entry corresponding to the received tag address, and store the new coherency state information for each of the cache memories into a respective one of the plurality of state memories.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: Apple Inc
    Inventors: Muditha Kanchana, Odutola O. Ewedemi
  • Patent number: 8966158
    Abstract: A data protection program for protecting data to be processed by an application, and a computer including volatile storage means and nonvolatile storage means performs a volatile file unpack function of writing, to the nonvolatile storage means, data corresponding to a data file to be read or written by the application so that the data is associated with the data file; and a volatile file repackage function of outputting the data file corresponding to the data written to the volatile storage means.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sanehiro Furuichi, Masami Tada
  • Patent number: 8966188
    Abstract: Various systems and methods for sharing data in a virtual environment are disclosed. For example, one method involves receiving a request to access data. The request can be received from a first virtual machine of a plurality of virtual machines. The method then involves retrieving a signature for the data where the signature is stored in a deduplicated data store. Next, the method involves detecting whether the signature is included in a map. In order to do so, the method compares the signature with entries in the map. The entries in the map identify data stored in RAM. The data is also stored in the deduplicated data store. If the signature is found in the map, the method involves granting the request to access the data. Otherwise, the method involves creating a new entry in the map and adding the signature to the new entry.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: February 24, 2015
    Assignee: Symantec Corporation
    Inventor: Trimbak Somnathappa Bardale
  • Patent number: 8966179
    Abstract: Computer-implemented methods for temporarily storing history of a web browsing session are provided. In one aspect, the method includes receiving a request to temporarily store session information for a web browsing session comprising at least one request to view a web page. The method also includes compressing data for the session information associated with the web browsing session, and storing the compressed data for the session information associated with the web browsing session only in a volatile memory. The compressed data for the session information stored in the volatile memory is lost when power to the volatile memory is off. A reference to the compressed data for the session information in the volatile memory is removed when the web browsing session is terminated.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 24, 2015
    Assignee: Google Inc.
    Inventors: Meng Wang, Arnaud Claude Weber
  • Patent number: 8954656
    Abstract: A method and system are disclosed for handling logical-to-physical mapping and reducing mapping table size. The method includes the storage device storing in fast access memory, such as DRAM, only the physical location of a primary cluster in each cluster group, and then writing location information for remaining clusters in a cluster group into the header of the data for the primary cluster of the cluster group in non-volatile memory. The system includes a storage device having volatile memory, non-volatile memory and a controller in communication with the volatile and non-volatile memory that is configured to carry out the method noted above.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 10, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Nicholas James Thomas
  • Patent number: 8954694
    Abstract: A data storage device comprises a plurality of non-volatile memory devices configured to store a plurality of physical pages; a controller coupled to the plurality of memory devices that is configured to program data to and read data from the plurality of memory devices. A volatile memory may be coupled to the controller and may be configured to store a firmware table comprising a plurality of firmware table entries. The controller may be configured to maintain a plurality of firmware journals in the non-volatile memory devices. Each of the firmware journals may be associated with a firmware table entry and may comprise firmware table entry information. The controller may be configured to read the plurality of firmware journals upon startup and rebuild the firmware table using the firmware table entry information in each of the read plurality of firmware journals.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignees: Western Digital Technologies, Inc., Skyera, Inc.
    Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
  • Patent number: 8949548
    Abstract: One or more methods and systems of sharing an external memory between functional modules of an integrated circuit chip are presented. The invention provides a system and method of reducing the amount of off-chip memory utilized by one or more integrated circuit chips. In one embodiment, a method for sharing an off-chip memory among one or more on-chip functional modules comprises arbitrating the communication of data between one or more on-chip functional modules and the off-chip memory. In one embodiment, the arbitration is facilitated by using an internal data bus that is controlled by a bus arbiter control unit. In one embodiment, a system for sharing an off-chip memory between functional modules of an integrated circuit comprises a security processing module, a media access controller module, a data interface, and a data bus.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: February 3, 2015
    Assignee: Broadcom Corporation
    Inventor: Mark Buer
  • Patent number: 8943264
    Abstract: A data storing method for a rewritable non-volatile memory module is provided. The method includes receiving page data to be stored in a first logical address. The method also includes determining whether a storage status of the rewritable non-volatile memory module is a predetermined status; if yes, using a first writing mode to write the page data into the rewritable non-volatile memory module; if no, using a second writing mode to write the page data into the rewritable non-volatile memory module. In the first writing mode, lower physical program units of the rewritable non-volatile memory module are applied for writing data, and upper physical program units of the rewritable non-volatile memory module are not applied for writing data; in the second writing mode, the upper physical program units and the lower physical program units are applied for writing data.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: January 27, 2015
    Assignee: Phison Electronics Corp.
    Inventor: Chih-Kang Yeh
  • Patent number: 8943267
    Abstract: Embodiments include a system, an apparatus, a device, and a method. The apparatus includes a processor, a dynamic memory, and a hardware-implemented memory control circuit. The hardware-implemented control circuit includes a control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory. The hardware-implemented control circuit also includes a control circuit for causing a refresh of the dynamic memory during each of at least two extended refresh periods.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 27, 2015
    Assignee: The Invention Science Fund I, LLC
    Inventor: William Henry Mangione-Smith
  • Patent number: 8938577
    Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: January 20, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Sandeep Rohilla
  • Patent number: 8938600
    Abstract: A memory system includes a dual inline memory module (DIMM) connector to which a DIMM is connected, which is selected from a Joint Electron Device Engineering Council (JEDEC) standard DIMM in compliance with JEDEC standards and a customized DIMM not in compliance with JEDEC standard, and a memory controller to determine whether the DIMM being connected is the JEDEC standard DIMM or the customized DIMM to generate a determination result, and to control access to the DIMM based on the determination result and SPD information obtained from a SPD of the DIMM being connected.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: January 20, 2015
    Assignee: Ricoh Company, Ltd.
    Inventor: Daisuke Koya
  • Publication number: 20150019802
    Abstract: A monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning is disclosed. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit and word lines for each memory call are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.
    Type: Application
    Filed: August 28, 2013
    Publication date: January 15, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Pratyush Kamal, Yang Du
  • Publication number: 20150019804
    Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 15, 2015
    Inventors: Siamack Nemazie, Ebrahim Abedifard