Solid-state Random Access Memory (ram) Patents (Class 711/104)
  • Patent number: 8706958
    Abstract: Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: April 22, 2014
    Inventor: Thomas Hein
  • Patent number: 8706955
    Abstract: In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory accessible by a controller of the memory device; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, firmware from a host device, wherein the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the firmware from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained through communication with the memory controller of the memory device.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 22, 2014
    Assignee: Apple Inc.
    Inventors: Anthony Fai, Nir Jacob Wakrat, Nicholas Seroff
  • Patent number: 8706985
    Abstract: The present invention is directed to systems and methods for optimizing garbage collection in data storage. The data storage may be a shingled disk drive or a non-volatile solid-state memory device. Garbage collection is optimized by selectively saving data read from certain locations of the data storage in response to host read commands and using the saved data for subsequent garbage collection operations. The decision of whether to save data may be based on a number of criteria, including whether the data is located in an area of the data storage that is due to be garbage collected in the near future. In this manner, certain garbage collection operations can be performed without having to re-read the saved data.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: April 22, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: William B. Boyle, Robert M. Fallone
  • Patent number: 8706967
    Abstract: A method, computer program product, and cache management system for receiving an indication of a data portion update within an electromechanical storage system. Information concerning the data portion update is provided to at least one proprietary, solid-state, non-volatile, cache memory system. The proprietary, solid-state, non-volatile, cache memory system is associated with at least a first of a plurality of computing devices and is not associated with at least a second of the plurality of computing devices.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: April 22, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Robert C. Solomon, Robert W. Beauchamp, Humberto Rodriguez, John M. Hayden
  • Patent number: 8700834
    Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 15, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert L. Horn, Sebastien A. Jean
  • Patent number: 8700253
    Abstract: A system is provided for collecting defect data of components in a passenger cabin of a vehicle that includes, but is not limited to a component identification device for identifying an affected component, and a malfunction selection device, connected to the component identification device, for selecting a malfunction of the identified component from a predefined quantity of component-specific malfunctions. The system includes, but is not limited to a locating device for acquiring a position of the affected component in the passenger cabin, with the aforesaid being connected to the component identification device. In this manner, by means of devices that are very simple to use, imprecise positioning information, component information and malfunction information can be avoided.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: April 15, 2014
    Assignee: Airbus Operations GmbH
    Inventor: Daniel Fischer
  • Patent number: 8694717
    Abstract: A manufacturing cost of an integrated circuit chip used in a program update system or in an electronic device with program update function is reduced. A first integrated circuit chip has a USB interface circuit, a compression decoder, a CPU and a mask ROM. The first integrated circuit chip is a single chip consolidating a microcomputer with a USB host function and the compression decoder. A second integrated circuit chip has a CPU and an FROM, and serves as a system microcomputer to control the whole system of a car audio. A control program stored in the mask ROM is updated using the FROM incorporated in the second integrated circuit chip.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shizuka Ishimura, Mitsuyoshi Fukuda
  • Publication number: 20140095777
    Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple small sections, and each section is supplied with power from a separately controllable power supply. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. Incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: APPLE INC.
    Inventors: Sukalpa Biswas, Shinye Shiu
  • Publication number: 20140095778
    Abstract: Methods and apparatus are disclosed to cache code in non-volatile memory. A disclosed example method includes identifying an instance of a code request for first code, identifying whether the first code is stored on non-volatile (NV) random access memory (RAM) cache, and when the first code is absent from the NV RAM cache, adding the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Jaewoong Chung, Youfeng Wu, Cheng Wang
  • Patent number: 8689204
    Abstract: There are described tools and methodologies for building Read Only Memory (ROM) mask software images and the corresponding data/code patching software images. One method is for creating ROM mask content having patch references included therein whereby patch reference errors are detected and corrected. A software patch for a ROM mask with existing patch references may then automatically be created.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: April 1, 2014
    Assignee: BlackBerry Limited
    Inventors: Conrad Kreek, Sean Simmons, Jacob Burkholder, Tran Phat, Jonathan Swoboda
  • Patent number: 8683149
    Abstract: Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 25, 2014
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Venu Madhav Kuchibhotla
  • Publication number: 20140081901
    Abstract: Embodiments of the present invention provide various techniques for sharing modeling data between plug-in applications. The plug-in applications may use or generate various modeling data. In an example, the host application that interfaces with the plug-in applications can access and store this modeling data at a location where it is accessible to the other plug-in applications.
    Type: Application
    Filed: April 24, 2009
    Publication date: March 20, 2014
    Applicant: NetApp, Inc.
    Inventor: Martin Szymczak
  • Patent number: 8677060
    Abstract: Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 18, 2014
    Assignee: Netlist, Inc.
    Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
  • Patent number: 8671243
    Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 11, 2014
    Assignee: Netlist, Inc.
    Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
  • Publication number: 20140068166
    Abstract: A disclosed information processing apparatus includes: one or plural memories, each of which includes a self-refresh function; and a memory control unit that stops a patrol that includes reading and error correction with respect to a memory among the one or plural memories, upon starting self-refresh of the one or plural memories, and that restarts the patrol, upon stopping the self-refresh of the one or plural memories. A disclosed memory control unit includes: a patrol unit that performs a patrol including reading and error correction with respect to a memory among one or plural memories that has a self-refresh function; and a controller that stops the patrol, upon starting self-refresh of the one or plural memories, and that restarts the patrol, upon stopping the self-refresh of the one or plural memories.
    Type: Application
    Filed: August 20, 2013
    Publication date: March 6, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Hiromi FUKUMURA, Katsuya SUGA
  • Publication number: 20140068164
    Abstract: A memory content access interface may include, but is not limited to: a read-path memory partition; a write-path memory partition; and a memory access controller configured to regulate access to at least one of the read-path memory partition and the write-path memory partition by an external controller.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: LSI CORPORATION
    Inventors: Herjen Wang, Lei Chen, Ngok Ning Chu, Johnson Yen
  • Publication number: 20140068145
    Abstract: Various exemplary embodiments relate to an integrated circuit including: a RF interface; a wired interface connectable to a host; a volatile memory having a first block and a last block configured to store data transferred between the RF interface and the wired interface; and a memory controller configured to detect when the last block of the volatile memory has been written and to indicate that the volatile memory is ready to read. Various exemplary embodiments relate to a method performed by a tag including: determining that data is to be received on the first interface; blocking the second interface; writing data from the first interface to a volatile memory; detecting that the last block of the volatile memory has been written; unblocking the second interface; indicating that data is available for reading; blocking the first interface; and reading data from the volatile memory to the second interface.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Applicant: NXP B.V.
    Inventors: Francesco Gallo, Paul Bakker, Giancarlo Cutrignelli
  • Publication number: 20140068165
    Abstract: A method is provided for exchanging large amounts of memory within an operating system containing consumer and producer threads located in a user space and a kernel space, by controlling ownership of a plurality of RAM banks shared by multiple processes or threads in a consumer-producer relationship. The method includes sharing at least two RAM banks between a consumer process or thread and a producer process or thread, thereby allowing memory to be exchanged between said consumer process or thread and said producer process or thread, and alternately assigning ownership of a shared RAM bank to either said consumer process or thread or said producer process or thread, thereby allowing said producer process or thread to insert data into said shared RAM bank and said consumer process or thread to access data from said shared RAM bank.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: Accedian Networks Inc.
    Inventors: Thierry DeCorte, Donald Stevenson
  • Publication number: 20140068319
    Abstract: An apparatus including at least one memory controller; and a plurality of random access memories, where the at least one memory controller is configured to allocate the plurality of random access memories among at least a first portion, a second portion and a third portion. The first portion is configured to store protected data. The second portion is configured to store parity information for the stored protected data. The third portion is configured to store unprotected data.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 6, 2014
    Applicant: International Business Machines Corporation
    Inventor: David M. Daly
  • Patent number: 8667230
    Abstract: A digital memory architecture for recognition and recall in support of a host comprises a plurality of pattern processors, each of which has its own random access memory (RAM) and controller, an external data bus and external data bus controller, a results bus and results bus controller, an internal data bus and internal data bus controller, and an external control bus and external control bus and controller. Each of the pattern processors may be a general purpose set theoretic processor (GPSTP) operating in interrupt and block modes.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: March 4, 2014
    Inventor: Curtis L. Harris
  • Publication number: 20140059283
    Abstract: Methods and systems for controlling a memory array are provided. A method of controlling a memory array includes: providing a next index to be read that indicates a location in the memory array from which to retrieve an output; reading validity information from a validity memory unit; comparing the next index with a last read index stored in an index memory unit; reading the output from an output memory unit when the last read index is the same as the next index and the validity information indicates the output in the output memory unit is valid; and reducing power to the memory array when the output is read from the output memory unit.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: James D. Dundas
  • Publication number: 20140059269
    Abstract: Exemplary embodiments may provide a computing device which includes a first random access memory; a second random access memory; a memory controller which is configured to control the first random access memory and second random access memory; and a processor which is configured to use the first random access memory and second random access memory, as a working memory, through the memory controller, wherein the memory controller is configured to access one memory, selected by a transferred command from the processor, from among the first random access memory and second random access memory.
    Type: Application
    Filed: August 27, 2013
    Publication date: February 27, 2014
    Inventors: Young-jin PARK, Ilguy JUNG
  • Publication number: 20140059282
    Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.
    Type: Application
    Filed: December 7, 2011
    Publication date: February 27, 2014
    Inventors: Wei ZHANG, Niraj K. JHA, Li SHANG
  • Publication number: 20140059284
    Abstract: Embodiments of the present invention provide a system, method and computer program products for memory space management for storage class memory. One embodiment comprises a method for information storage in an information technology environment. The method comprises storing data in a storage class memory (SCM) space, and storing storage management metadata corresponding to said data, in the SCM in a first data structure. The method further includes buffering storage management metadata corresponding to said data, in a main memory in a second data structure.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ru Fang, Bin He, Hui-I Hsiao, Chandrasekaran Mohan
  • Patent number: 8661184
    Abstract: An apparatus, system, and method are disclosed to manage non-volatile media. A media characteristic module is configured to determine media characteristics for non-volatile media. A configuration parameter module is configured to determine different configuration parameters for different storage cell abodes and/or for different groups of pages of the non-volatile media based on the determined media characteristics. A cell configuration module is configured to use the different configuration parameters for the different storage cell abodes and/or the different groups of pages of the non-volatile media.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 25, 2014
    Assignee: Fusion-io, Inc.
    Inventors: Robert Wood, Jea Hyun, Hairong Sun
  • Patent number: 8661180
    Abstract: Disclosed herein is a memory controlling device including: an address converting section configured to convert a logical address included in a request issued from a plurality of clients into a physical address of a memory; a request dividing section configured to divide a converted request converted by the address converting section by a command unit for the memory on a basis of the physical address of the converted request; and an arbitrating section configured to perform arbitration on a basis of the physical address indicated in a divided request output from the request dividing section.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: February 25, 2014
    Assignee: Sony Corporation
    Inventors: Satoshi Takagi, Yasuhiro Matsui, Masao Tanaka, Takahiro Ikarashi, Akihiko Saotome, Hiroshi Sumihiro, Yukinao Kenjo
  • Patent number: 8656130
    Abstract: Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Blake G. Fitch, Michele M. Franceschini, Ashish Jagmohan, Todd E. Takken
  • Publication number: 20140047173
    Abstract: A device stores a plurality of applications and a list of associations for those applications. The applications are preferably stored within a secondary memory of the device, and once launched each application is loaded into RAM. Each application is preferably associated to one or more of the other applications. Preferably, no applications are launched when the device is powered on. A user selects an application, which is then launched by the device, thereby loading the application from the secondary memory to RAM. Whenever an application is determined to be associated with a currently active state application, and that associated application has yet to be loaded from secondary memory to RAM, the associated application is pre-launched such that the associated application is loaded into RAM, but is set to an inactive state.
    Type: Application
    Filed: October 22, 2013
    Publication date: February 13, 2014
    Applicants: Sony Electronics Inc., SONY CORPORATION
    Inventors: Phuong Viet Nguyen, Ashish Garg
  • Patent number: 8650356
    Abstract: A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: February 11, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Tim L. Wilson, Joseph W. Triece, Steven G. Dawson
  • Patent number: 8650355
    Abstract: Various embodiments of the present invention are generally directed to a non-volatile resistive sense memory on-chip cache. In accordance with some embodiments, a processing circuit is formed on a first semiconductor substrate. A second semiconductor substrate is affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: February 11, 2014
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Henry F. Huang
  • Patent number: 8643888
    Abstract: Disclosed is an image forming apparatus including: at least three storing devices; a detecting unit; and a control unit, wherein the striping is carried out by using all of the storing devices, and the mirroring is carried out by using at least two of the storing devices except at least one storing device. When one of the storing device is failed, in case that the mirroring was carried out by using the failed storing device, the mirroring is continued by using the one storing device which is not used for carrying out the mirroring instead of the failed storing device. The striping is carried out by using all of the storing devices except the failed storing device.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 4, 2014
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventor: Katsunori Teshima
  • Patent number: 8645609
    Abstract: A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between simultaneous read and write accesses to the same single-port RAM bank. A read mapping memory stores instance information that maps logical banks and a spare bank to the single-port RAM banks for read accesses. Similarly, a write mapping memory stores write instance information that maps logical banks and a spare bank to the single-port RAM banks for write accesses. If simultaneous read and write accesses are not mapped to the same single-port RAM bank, read and write are performed simultaneously. However, if a collision exists, the write access is re-mapped to a spare bank identified by the write instance information, allowing simultaneous read and write. Both read and write mapping memories are updated to reflect any re-mapping.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Kung-Ling Ko, Tony Sonthe Nguyen, Joseph Juh-En Cheng, Tuan Van Quach
  • Patent number: 8645795
    Abstract: The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: February 4, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuya Ishihara, Yoshiaki Tabuchi
  • Publication number: 20140032828
    Abstract: A system, method, and computer program product are provided for copying data between memory locations. In use, a memory copy instruction is implemented. Additionally, data is copied from a first memory location to a second memory location, utilizing the memory copy instruction.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Brucek Kurdo Khailany, Sean Jeffrey Treichler
  • Publication number: 20140032826
    Abstract: A method of training a memory device included in a memory system is provided. The method includes testing memory core parameters for a memory core of the memory device during a booting-up sequence of the memory system; determining trimmed memory core parameters based on the test results; storing the determined trimmed memory core parameters; and applying the trimmed memory core parameter to the memory device during a normal operation of the memory device.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 30, 2014
    Inventors: Woo-Jin LEE, Dae-Hyun KIM, Seung-Jun BAE, Young-Soo SOHN, Tae-Young OH
  • Publication number: 20140032827
    Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 30, 2014
    Inventors: Ming Zhang, Chris Wilkerson, Greg Taylor, Randy J. Aksamit, James Tschanz
  • Patent number: 8639873
    Abstract: A detachable storage device can comprise a ram cache, a device controller, and a storage system. The ram cache may be configured to receive data from a digital device. The device controller may be configured to transfer the data from the ram cache to the storage system. The storage system may be configured to store the data at a predetermined event.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 28, 2014
    Assignee: Imation Corp.
    Inventors: David Alexander Jevans, Gil Spencer
  • Patent number: 8639902
    Abstract: Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Publication number: 20140025878
    Abstract: Disclosed in the disclosure are a terminal for accessing a wireless network and a method for running the same, wherein the terminal includes an expanded external RAM and is configured to store the terminal firmware program obtained from the host side into the expanded external RAM, run the same and interact with the host side to complete a service. the terminal in the disclosure need not expand the FLASH storage space, and the terminal stores the terminal firmware program obtained from the host side into the expanded external RAM thereof, then runs the same and interacts with the host side to complete the service. The terminal does not use FLASH to store the terminal firmware program, avoiding the failure of not being able to be upgraded or used, wherein the failure is due to the exception of the terminal FLASH and reducing the costs of the wireless network access terminal.
    Type: Application
    Filed: July 5, 2011
    Publication date: January 23, 2014
    Applicant: ZTE CORPORATION
    Inventor: Tao Peng
  • Patent number: 8635417
    Abstract: A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 21, 2014
    Assignee: MoSys, Inc.
    Inventors: Michael J. Morrison, Jay B. Patel
  • Publication number: 20140013045
    Abstract: A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.
    Type: Application
    Filed: December 29, 2011
    Publication date: January 9, 2014
    Inventors: James B. Crossland, Toby Opferman, Blaise Fanning
  • Patent number: 8627003
    Abstract: An apparatus, system, and method are disclosed for memory upgrade optimization. A requirements module 402 receives one or more of a capacity upgrade goal 1306 for an overall capacity of the array 706 and a performance upgrade goal 1308 for an overall performance of the array 706. An analysis module 404 identifies a first potential capacity change 1310 that can be achieved at a lower overall performance and a second potential capacity change 1314 that can be achieved at a higher overall performance. A reconfiguration module 406 generates one or more of a first reconfiguration recommendation 1312 calculated to yield an overall capacity improvement that takes into consideration the capacity upgrade goal 1306 and the first potential capacity change 1310 and a second reconfiguration recommendation 1316 calculated to yield an overall performance improvement that takes into consideration the performance upgrade goal 1308 and the second potential capacity change 1314.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 7, 2014
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Daryl Cromer, Donald R. Frame, Michael Scott Mettler, Kenneth Dean Timmons
  • Publication number: 20140006697
    Abstract: A memory bank for a computer system includes a state indication unit for indicating the working state of the memory bank. A register chip of the memory bank includes a detection module that detects whether the memory bank works normally or not and generates a control signal for controlling the indication unit. The indication unit connects to the detection module to receive the control signal and indicates whether or not the memory bank works normally using a light indicator.
    Type: Application
    Filed: June 20, 2013
    Publication date: January 2, 2014
    Inventors: BO TIAN, KANG WU
  • Publication number: 20130346680
    Abstract: A memory system comprises a memory controller, an address RAM coupled to the memory controller, and a non-volatile memory coupled to the memory controller. The non-volatile memory has an address portion and a data portion. The address portion of the non-volatile memory provides data portion addresses and data portion addresses of valid data to the memory controller. The memory controller loads the data portion addresses and stores them in the address RAM at locations defined by the data portion addresses of valid data into the address RAM. The memory controller uses the data portion addresses, and locations of data blocks within the address RAM, to locate the data blocks within the data portion of non-volatile memory.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Inventors: Ross S. Scouller, Frank K. Baker, JR., Ronald J. Syzdek
  • Publication number: 20130346681
    Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.
    Type: Application
    Filed: August 28, 2013
    Publication date: December 26, 2013
    Inventors: Uwe Hildebrand, Josef Hausner, Matthias Obermeier, Daniel Bergmann
  • Publication number: 20130339591
    Abstract: When a relaying apparatus receives communication unit data transmitted from a processing apparatus that performs data processing, the relaying apparatus extracts preset data from the received communication unit data as trace information and calculates the number of pieces of the received communication unit data. History information of the received communication unit data is selected from the extracted trace information and statistical information obtained from the result of the calculation. The selected information is recorded in a storage apparatus available to the processing apparatus.
    Type: Application
    Filed: August 8, 2013
    Publication date: December 19, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Jin Takahashi, Masanori Higeta, Shintaro Itozawa, Masahiro NISHIO, Hiroshi Nakayama, Junji Ichimiya
  • Patent number: 8612684
    Abstract: Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: December 17, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore Carter Briggs, John Michael Wastlick, Gary Belgrave Gostin
  • Publication number: 20130332664
    Abstract: A file comprising an application and data corresponding to a status of the application at a particular time is maintained in a first memory of a user device, the first memory comprising a persistent storage. The application may be a software application, for example. In response to a request, the file is transferred to a second memory of the device, the second memory comprising a random-access memory. The file is activated, or set up, as a running application. The user device may be a cell phone, a wireless telephone, a personal digital assistant, a personal computer, a laptop computer, a workstation, a mainframe computer, etc. In one embodiment, the file is brought to a foreground of the user device.
    Type: Application
    Filed: June 8, 2012
    Publication date: December 12, 2013
    Applicant: ALCATEL-LUCENT USA INC.
    Inventor: James W. McGowan
  • Publication number: 20130332666
    Abstract: According to one embodiment, an information processor configured to execute codes described in Open Computing Language (OpenCL) includes: a first cache; a second cache; a global memory; and an arithmetic module. The first cache is with local scope and configured to be capable of being referred to by all work items in one workgroup. The second cache is with global scope and configured to be capable of being referred to by all work items in a plurality of workgroups. The global memory is with global scope and configured to be capable of being referred to by all work items in a plurality of workgroups. The arithmetic module is configured to execute a code referring to the second cache as a scratch-pad memory.
    Type: Application
    Filed: August 9, 2013
    Publication date: December 12, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kosuke Haruki
  • Publication number: 20130332665
    Abstract: A memory device includes a block of memory cells and a cache. The block of memory cells is not a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 12, 2013
    Applicant: MOSYS, INC.
    Inventors: Dipak Sikdar, Michael J. Miller, Jay Patel