Abstract: A data storing method for a rewritable non-volatile memory module is provided. The method includes receiving page data to be stored in a first logical address. The method also includes determining whether a storage status of the rewritable non-volatile memory module is a predetermined status; if yes, using a first writing mode to write the page data into the rewritable non-volatile memory module; if no, using a second writing mode to write the page data into the rewritable non-volatile memory module. In the first writing mode, lower physical program units of the rewritable non-volatile memory module are applied for writing data, and upper physical program units of the rewritable non-volatile memory module are not applied for writing data; in the second writing mode, the upper physical program units and the lower physical program units are applied for writing data.

Abstract: A memory system includes a dual inline memory module (DIMM) connector to which a DIMM is connected, which is selected from a Joint Electron Device Engineering Council (JEDEC) standard DIMM in compliance with JEDEC standards and a customized DIMM not in compliance with JEDEC standard, and a memory controller to determine whether the DIMM being connected is the JEDEC standard DIMM or the customized DIMM to generate a determination result, and to control access to the DIMM based on the determination result and SPD information obtained from a SPD of the DIMM being connected.

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.

Abstract: A monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning is disclosed. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit and word lines for each memory call are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.

Abstract: A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.

Abstract: For read based temporal locality compression by a processor device in a computing environment, read operations are monitored, traced, and/or analyzed to identify repetitions of read patterns of compressed data. The compressed data is rearranged based on the repetitions of read order of the compressed data that are in a read order.

Abstract: A memory system including a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing metadata. A compare circuit is configured to receive metadata retrieved from a plurality of pages sequentially and compare the retrieved metadata to a search pattern. The physical location of the page can be determined by finding the search pattern. The memory array and the compare circuit are formed in different layers of the substrate.

Abstract: Proposed are a storage system and its control method capable of dealing with the unique problems that arise when using a nonvolatile memory as the memory device while effectively preventing performance deterioration. This storage system is provided with a plurality of memory modules having one or more nonvolatile memory chips, and a controller for controlling the reading and writing of data from and in each memory module. The memory module decides the nonvolatile memory chip to become a copy destination of data stored in the nonvolatile memory when a failure occurs in the nonvolatile memory chip of a self memory module, and copies the data stored in the failed nonvolatile memory chip to the nonvolatile memory chip decided as the copy destination.

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a single-port memory, a dual-port memory, and a control circuit. The single-port memory may be store tag information associated with a cache memory, and the dual-port memory may be configured to store state information associated with the cache memory. The control circuit may be configured to receive a request which includes a tag address, access the tag and state information stored in the single-port memory and the dual-port memory, respectively, dependent upon the received tag address. A determination of if the data associated with the received tag address is contained in the cache memory may be made the control circuit, and the control circuit may update and store state information in the dual-port memory responsive to the determination.

Abstract: The present invention provides a method for safely recovering, protecting, and reading short term memory devices, such as DRAM modules, following their immediate removal from a system after it powers down. By providing power and appropriate control signals, the present invention stabilizes the memory and allows it to be safely read.

Abstract: According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.

Abstract: A computer has a mother board upon which is mounted, a millimetre wave oscillator and a central processing unit (CPU). The millimetre wave oscillator is operable to generate a clock signal and transmit this to the CPU via a link. The clock signal may be employed as a system clock signal and a processing clock signal for the CPU. The millimetre wave oscillator allows higher frequency clock signals than are currently available whilst generating significantly less heat. Therefore, the CPU may not require any cooling system and if it does then a smaller cooling system than is required by the prior art will suffice. Furthermore, the CPU will be more stable. This arrangement requires less power than prior art arrangements and therefore may increase the battery life of a computer.

Abstract: A virtual EEPROM driver is simulated for a virtual switch. A write function may be written to a shared memory device and designated as a virtual EEPROM driver. The virtual EEPROM driver may be duplicated into a non-volatile memory providing availability during a boot process.

Abstract: An apparatus, system, and method are disclosed for detecting intermittent network link failures. A tracking module tracks link failures of a network link of a network over a specified time interval. A failure module determines the network link is failing in response to a number of link failures exceeding a specified failure threshold. A mitigation module mitigates communications over the network link.

Abstract: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.

Abstract: A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.

Abstract: An application server maintains a first plurality of applications in non-volatile memory. The application server loads into volatile memory a subset of the first plurality of applications. The subset is a second plurality of applications. The application server receives a request to execute an application that is not currently loaded in volatile memory, and in response performs a set of operations: (1) determining that there is inadequate storage space in volatile memory to store the application; (2) identifying at least one application in the second plurality of applications that is designated as exempt from eviction from volatile memory; (3) selecting from among the second plurality of applications an eviction target, where the selection process excludes the designed applications; (4) evicting from volatile memory the eviction target; and (5) loading and executing the application in response to the received request, and returning a result responsive to the received request.

Abstract: A method may be performed in a data storage device that includes a controller, a non-volatile memory, and a volatile memory. The method includes loading a first portion of stored data from the non-volatile memory to the volatile memory according to one or more load priority indicators accessible to the controller. The method further includes, in response to completion of the loading of the first portion of the stored data to the volatile memory and prior to completion of loading a second portion of the stored data to the volatile memory, sending a signal to indicate to a host device operatively coupled to the data storage device that the volatile memory is ready for use by the host device.

Abstract: Resistance memory device and apparatus, a fabrication method thereof, an operation method thereof, and a system including the same are provided. The resistance memory device may include a data storage unit and a first interconnection connected to the data storage unit. A first access device may be connected in series with the data storage unit and a second access device may be connected in series with the first access device. A second interconnection may be connected to the second access device. A third interconnection may be connected to the first access device to drive the first access device and a fourth interconnection connected to the second access device to drive the second access device.

Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.

Abstract: Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device, a controller, an extended function section, and an extension register. The controller controls the nonvolatile semiconductor memory device. The extended function section is controlled by the controller. The extension register which is provided with a certain block length capable of defining an extended function of the extended function section. The controller processes a first command to write header data of a command to operate the extended function section to the extended function section through the extension register, and a second command to read header data of a response from the extended function section through the extension register.

Abstract: A method and system for code storage using volatile memory are disclosed. In a first aspect, the method comprises providing a system on a chip (SOC) that includes at least one volatile memory. The method includes coupling a portable power source to the SOC, wherein the portable power source powers the at least one volatile memory with minimal leakage. The method includes storing updatable code on the at least one volatile memory. In a second aspect, the system comprises a system on a chip (SOC) and at least a Static Random-Access Memory (SRAM) coupled to the SOC with updatable code stored therein. The system includes a portable power source coupled to the SOC, wherein the portable power source powers the SRAM with minimal leakage.

Abstract: Embodiments of the invention are directed to systems and methods for improving wear leveling performance in solid-state memory. The embodiments described herein make more consistent the number of wear leveling operations that needs to be performed, so that sudden spikes in the number wear leveling operations may be reduced in solid-state memory. In one embodiment, a staggered threshold-based wear leveling approach is used to spread out the execution of wear leveling operations that otherwise would have been triggered in clusters. Under the staggered threshold-based approach, wear leveling is periodically triggered by different wear leveling thresholds that are associated with various units of solid-state memory such as a group of blocks, so that only a certain amount of units are wear leveled at any given time.

Abstract: An electronic device comprises a buffer, a processing module, and a storage. When the electronic device generates a writing instruction, the processing module executes a protection and writes data of the buffer into the storage. Based on the protection, the processing module fails to execute interrupt instructions while writing data into the storage.

Abstract: Processing a plurality of data units to generate result information, includes: performing a data operation for each data unit of a first subset of data units from the plurality of data units, and storing information associated with a result of the data operation in a first set of one or more data structures stored in working memory space of a memory device; after an overflow condition on the working memory space is satisfied, storing information in overflow storage space of a storage device; and repeating an overflow processing procedure multiple times during the processing of the plurality of data units, the overflow processing procedure including: updating a new set of one or more data structures stored in the working memory space using at least some information stored in the overflow storage space.

Abstract: Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.

Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.

Abstract: A method, a statistics subsystem, and a system use a combination of commercially available high speed memory and high density low speed memory to mitigate cost, space, control, and power issues associated with storing counters for statistics updates, while meeting the growing width and depth needs of multi-hundred gigabit Carrier Class data network devices. The method, statistics subsystem, and system offer a Counter Management Algorithm (CMA) that relies on rollover bits stored within data of counters. An update to the low speed memory is substantially faster than a rollover time for the counter in the high speed memory thereby allowing statistics to be cached in the high speed memory while updates take place to the low speed memory.

Abstract: Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Abstract: A non-volatile mass storage memory and an input/output processing method using the memory are provided. The memory device includes a storage unit including a non-volatile random access memory and a flash memory and a controller to control the storage to process an input/output request. Accordingly, system memories having different purposes and functionalities, such as a flash memory and a dynamic random access memory (DRAM), may be integrated with each other.

Abstract: Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.

Abstract: A computer-implemented method for transferring data from a computer system programmed to perform the method includes receiving in a memory buffer in a first memory module hosted by the computer system, a request for data stored in RAM of the first memory module from a host controller of the computer system, retrieving with the memory buffer, the data from the RAM, in response to the request, formatting with the memory buffer, the data from the RAM into formatted data in response to a defined software transport protocol, and initiating with the memory buffer, transfer of the formatted data to a storage destination external to the first memory module via an auxiliary interface of the memory buffer, bypassing the host controller of the computer system.

Abstract: Decoding a content of interest with optimal power usage. In an embodiment, a central processing unit (CPU) retrieves the frames of a data stream of interest from a secondary storage and stores them in a random access memory (RAM). The CPU forms an index table indicating the locations at which each of the frames is stored. The index table is provided to a decoder, which processes the frames in sequence to recover the original data from the encoded data. By using the index information, the power usage is reduced at least in an embodiment when the decoding is performed by an auxiliary processor.

Abstract: Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.

Abstract: A power supply control device includes an electrical power generating unit that generates electrical power and supplies the generated electrical power to an electronic device having a nonvolatile memory and a control unit; a switching unit that monitors a voltage of electrical power supplied to the electronic device, and switches such that, when the voltage is less than a predetermined threshold value, the electrical power is supplied to the control unit and is not supplied to the nonvolatile memory; and a capacitor that maintains, when the electrical power is switched to be supplied to the control unit, a voltage applied to the nonvolatile memory for a period of time during which writing of data to the nonvolatile memory can be completed.

Abstract: A fast booting computer apparatus includes one or more processors and a memory comprising a hard disk drive and a solid state drive coupled to the one or more processors. The one or more processors are configured to execute programmed instructions stored in the memory. The solid state drive is configured to store and provide the programmed instructions for an operating system for execution by the one or more processors when requested.

Abstract: An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.

Abstract: A computing system includes computer memory of a number of different memory types. An application program compiled for execution on the computing system controls access to a field of a record in the computer memory of the computing system by defining a record that includes one or more fields, the one or more fields including a restricted field having a specification of restricted accessibility when the restricted field is allocated in a particular memory type; allocating an instance of the record in memory of the particular memory type; and denying each attempted access of the restricted field while the record is allocated in the particular memory type.

Abstract: Methods and structure are provided for maintaining gate training parameters for Random Access Memory. The system comprises a memory controller and a management unit. The management unit is able to initialize the system after the system returns from an unpowered state by accessing a non-volatile memory to retrieve timing intervals for electrical impulses sent between the memory controller and a Random Access Memory. The timing intervals previously enabled communication between the memory controller and the Random Access Memory. The management unit is further able to initialize the system after the system returns from an unpowered state by calibrating the memory controller to enable communication with the Random Access Memory based on the retrieved timing intervals.

Abstract: In a microcomputer provided with a program storing device for storing instruction codes and a micro-processor for reading and executing the instruction codes stored in the program storing device, the program storing device have plural memories for storing instruction codes, an output unit for receiving plural pieces of data output from the plural memories, and selecting and outputs one of the plural pieces of data received from the plural memories, a selecting unit for receiving address data sent from the micro-processor to select one of the plural memories, an activating unit for activating the memory selected by the selecting unit, and a controlling unit for controlling the output unit to output data of the memory activated by the activating unit.

Abstract: According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory technology. The processors are configured to receive messages conforming to a first memory technology, translate the messages from the first memory technology to the second memory technology, and send the translated messages to the memory devices.

Abstract: A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.

Abstract: A FIFO apparatus uses a first clock signal in a first clock domain to receive an input signal and uses a second clock signal in a second clock domain to output an output signal. An example apparatus includes: at least three write registers belonging to the first clock domain for receiving the input signal. Each of the write registers has a first output. A first controller belonging to the first clock domain enables the registers, in accordance with an order, to generate an initial signal. A multiplexer receives the first outputs. A second controller belonging to the second clock domain, receives the initial signal through an asynchronous interface and controls the multiplexer to output the first outputs in accordance with the order to be the output signal, wherein the second clock domain is a clock tree generated based on the first clock domain.

Abstract: A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.

Abstract: The present invention relates to semiconductor storage systems (SSDs). Specifically, the present invention relates to a switch-based hybrid storage system. In a typical embodiment, a first RAID controller is coupled to a system control board, and a double data rate semiconductor storage device (DDR SSD) module is coupled to the first RAID controller. The DDR SSD module typically includes a set of DDR SSD units. Also coupled to the system control board are a first switch and a second switch. A second RAID controller is coupled to the first switch, while a hard disk drive (HDD) module coupled to the second RAID controller. The HDD module typically includes a set of HDD/Flash SDD units. Also coupled to the second switch is a communications module having a set (at least one) of ports.

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract: A memory module includes memory banks, a local memory controller to access data in the memory banks, and an interface to an external memory controller that is configured to access the memory module. Multiplexing circuitry selectively connects the memory banks to the local memory controller and to the interface to the external memory controller.

Abstract: According to one embodiment, a memory system includes a memory and a controller configured to control the memory. The memory includes a semiconductor memory region in which data rewrite is executed by an instruction of the controller, a timing determination module configured to derive a command input timing to the memory, based on the instruction and a clock which are received from the controller, and a status register configured to store the command input timing to the memory, which is derived by the timing determination module.