Abstract: A system and method are disclosed which provide a cache structure that allows early access to the cache structure's data. A cache design is disclosed that, in response to receiving a memory access request, begins an access to a cache level's data before a determination has been made as to whether a true hit has been achieved for such cache level. That is, a cache design is disclosed that enables cache data to be speculatively accessed before a determination is made as to whether a memory address required to satisfy a received memory access request is truly present in the cache. In a preferred embodiment, the cache is implemented to make a determination as to whether a memory address required to satisfy a received memory access request is truly present in the cache structure (i.e., whether a “true” cache hit is achieved). Although, such a determination is not made before the cache data begins to be accessed.

Abstract: An enhanced cache line directory entry includes at least one affinity bit that indicates an affinity for a particular type of cache line ownership. The affinity bit is used to modify a request for a cache line in accordance with the indicated affinity. The affinity bit may represent an affinity for read-only requests, and the affinity bit may represent an affinity for read-write requests. For example, if an I/O affinity bit is in the set state and an I/O device requests a cache line with read-write permission, the request may be converted to a read-only request in accordance with the indicated affinity. As another example, if a processor affinity bit is in the set state and a processor requests a cache line with read-only permission, the request may be converted to a read-write request. Software control of the affinity bits enables system performance to be tuned and cache coherency operations can thereby be reduced.

Abstract: A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors.

Abstract: A Harvard-architecture computer system includes a processor, an instruction cache, a data cache, and a write buffer. The caches are both set-associative in that they each have plural memories; both caches perform parallel reads by default. In a parallel read, all cache-memory locations of the selected cache corresponding to the set ID and word position bits of a requested read address are accessed in parallel while it is determined whether or not one of these locations has a tag matching the tag portion of the requested read address. If there is a “hit” (match), then an output multiplexer selects the appropriate cache memory for providing its data to the processor. The parallel read thus achieves faster reads, but expends extra power in accessing non-matching sets. A cache receiving a read request while the processor is waited performs a serial read instead of a parallel read. In a serial read, the tag match is performed before the data is accessed.

Abstract: A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a completion of a request for write to a processing unit. The secondary controller stores the write data and the write time transmitted from the primary controller in the cache memory. At a time, the secondary controller stores the write data in a disk unit in the earlier sequence of the write time. These operations make it possible to guarantee all the write data on or before the reference time.

Abstract: The present invention is directed toward a system and method for caching data for multiple processes. The system utilizes a data storage device, and has at least one process adapted to utilize data stored in that data storage device. A component is used, which includes a basic set of instructions for creating and utilizing a memory map file in the data storage device. The memory map file stores data used by the process. A caching object is then built with the component. The caching object generates and manages the caching of data for the process in the memory map file. Also included in the present invention is a method for adding data caching ability to a process.

Abstract: The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory again over multiple paths.

Abstract: A method and apparatus for cache coherency in storage system is disclosed. The invention maintains cache coherency in the controller system of the storage system in a manner to minimize the performance degradation to a host system, and to allow the caches to be coherent without requiring data to be written to the backing disks. Each controller manages an area of memory on the partner controller, but the area is managed dynamically and is done with the information about the partner controller. A first controller determines which mirror cache line on a second controller to copy data into, and then mirrors the data from a first controller cache line to a second controller cache line. A message is sent from the first controller to the second controller informing the second controller of cache meta data associated with the mirror cache line so that the cache line may be added to the second controller's hash table.

Abstract: An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.

Abstract: Managing a cache memory includes using a first cache memory, copying data from the first cache memory to a second cache memory, and, following copying, using the second cache memory along with the first cache memory. Prior to using the second cache memory, data may be copied to the second cache memory in response to the data being provided from a disk storage area to the first cache memory. Copying data may include background copying the data during times when the cache memories are not otherwise being used. Using the second cache memory along with the first cache memory may include providing data from a disk storage area to a first cache memory, providing data from the disk storage area to a second cache memory, where the first and second cache memories contain at least some data that is different, and writing a portion of the data to both of the cache memories in response to the portion of data being modified while stored in the cache memories.

Abstract: In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access and snoop operation information for the corresponding cache line. The historical processor access and snoop operation information includes different subentries for each different processor which has accessed the corresponding cache line, with subentries being “pushed” along the stack when a new processor accesses the subject cache line. Each subentries contains the processor identifier for the corresponding-processor which accessed the cache line, a processor access history segment, and a snoop operation history segment. The processor access history segment contains one or more opcodes identifying the operations which were performed by the processor, and timestamps associated with each opcode.

Abstract: A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilities the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.

Abstract: Managing data in cache includes providing data from a disk storage area to a first cache memory, providing data from the disk storage area to a second cache memory, where the first and second cache memories contain at least some data that is not stored in the other one of the cache memories, and writing the same data to both of the cache memories in response to the data being modified while stored in the cache memories. Managing data in a cache may also include subdividing the first cache memory into primary and secondary storage areas, subdividing the second cache memory into primary and secondary storage areas, where primary areas of the first cache correspond to secondary areas of the second cache and where secondary areas of the first cache correspond to primary areas of the second cache, and providing data from the disk storage area to the one of the cache memories having a corresponding primary storage area.

Abstract: Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.

Abstract: A multiprocessor system can reduce a broadcast for cache memory consistency control with memory access from an I/O device. The multiprocessor system is provided with a cache memory identifier or an owner tag, and a block length table for recording a memory write block length of the I/O device. The cache memory identifier records that the cache has an exclusive copy. The owner tag records that there is no cache memory having an exclusive copy. If there is an exclusive copy during read through the I/O device, a read request is issued to both a cache holding the copy and a memory. If it is recorded that the copy is not present, data are directly read from the memory. Moreover, when a write block length is recorded in the block length table during write, whole blocks are collected to issue a request for invalidation from the cache and the request is directly written to the memory after the invalidation is completed.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A method of operating a cache memory includes the step of storing a set of data in a first space in a cache memory, a set of data associated with a set of tags. A subset of the set of data is stored in a second space in the cache memory, the subset of the set of data associated with a tag of a subset of the set of tags. The tag portion of an address is compared with the subset of data in the second space in the cache memory in that said subset of data is read when the tag portion of the address and the tag associated with the subset of data match. The tag portion of the address is compared with the set of tags associated with the set of data in the first space in cache memory and the set of data in the first space is read when the tag portion of the address matches one of the sets of tags associated with the set of data in the first space and the tag portion of the address and the tag associated with the subset of data in the second space do not match.

Abstract: A warmswap operation to replace modules in a mirrored cache system has been accomplished by disabling mirrored write operations in the cache system; testing the replacement memory module in the cache system; and restoring the mirrored data in the cache system. The restoring operation is accomplished by first quiescing write operations to stop writing data in the cache system not backed up in non-volatile data storage. Then data is copied from surviving memory modules to the replacement module, and the cooperative interaction of the surviving memory modules with the replacement memory module is validated. The validating operation verifies the cache modules are ready and the controllers are synchronized. After validation the quiesced write operations are un-quiesced, and mirrored-write operations for the cache system are enabled.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: The present invention relates to a processor including at least one memory access unit for presenting a read or write address over an address bus of a memory in response to the execution of a read or write instruction; and an arithmetic and logic unit operating in parallel with the memory access unit and arranged at least to present data on the data bus of the memory while the memory access unit presents a write address. The processor includes a write address queue in which is stored each write address provided by the memory access unit waiting for the availability of the data to be written.

Abstract: The inventive cache uses a queuing structure which provides out-of-order cache memory access support for multiple accesses, as well as support for managing bank conflicts and address conflicts. The inventive cache can support four data accesses that are hits per clocks, support one access that misses the L1 cache every clock, and support one instruction access every clock. The responses are interspersed in the pipeline, so that conflicts in the queue are minimized. Non-conflicting accesses are not inhibited, however, conflicting accesses are held up until the conflict clears. The inventive cache provides out-of-order support after the retirement stage of a pipeline.

Abstract: A cache memory system reduces the rate of cache misses. The cache memory system includes a first auxiliary storage device which stores first information blocks and a second auxiliary storage device which stores second information blocks fetched from a lower level memory device. Each second block includes a plurality of the first information blocks. A process for fetching information selectively fetches a first or second information block from the lower level memory device and selectively stores the fetched block in the first auxiliary storage device and/or the second auxiliary storage device. Selection of the size of block to fetch and where to store the fetched block is according to whether the data to be referenced by the central controller is in the first auxiliary storage device or the second auxiliary storage device and whether first information blocks that do not include the referenced data are both in the second information block including the referenced data and in the first auxiliary storage device.

Abstract: A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port and a second embedded memory port that is electrically coupled to the read port. A data input register, a retransmit register, a data output register and a multiplexer are provided within the cache memory device. The data input register is responsive to a write address and has a data input electrically coupled to the data input port and a data output electrically coupled to the first embedded memory port. The retransmit register is responsive to a retransmit address and has a data input electrically coupled to the data input port.

Abstract: In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of instruction buffers, flags each specific to each of instruction buffers, and a buffer controller circuit. The buffer controller circuit may allocate one of specific values that plural lower bits of an instruction address may take to each of the instruction buffers, and prefetch instructions to the instruction buffers each corresponding to a respective addresses designated to by the plural lower bits, from the address following a predetermined fetch address. The constitution for instruction prefetch as above may be implemented in a simpler manner than the controlling structure using address tags of a cache memory or the controlling structure using read-write pointer based on the counter in FIFO buffers.

Abstract: An information processing device includes a central processing unit, a cache memory unit and first and second decision circuits. The first decision circuit identifies one of partitioned address areas to be accessed before the central processing unit accesses the cache memory unit. The second decision circuit determines whether the above one of the partitioned address areas is a cachable area or a non-cachable area before address tag data is referred to in the cache memory unit.

Abstract: A computer system is presented implementing a system and method for properly ordering write operations. The system and method for properly ordering write operations aids in maintaining memory coherency within the computer system. The computer system includes multiple interconnected processing nodes. One or more of the processing nodes includes a central processing unit (CPU) and/or a cache memory, and one or more of the processing nodes includes a memory controller coupled to a memory. The CPU or cache generates a write command to store data within the memory. The memory controller receives the write command and responds to the write command by issuing a target done response to the CPU or cache after the memory controller: (i) properly orders the write command within the memory controller with respect to other commands pending within the memory controller, and (ii) determines that a coherency state with respect to the write command has been established within the computer system.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: Cache states for cache coherency protocols for a multiprocessor system are described. Some embodiments described include a multiprocessor computer system comprising a plurality of cache memories to store a plurality of cache lines and state information for each one of the cache lines. The state information comprises data representing a first state selected from the group consisting of a Shared-Update state, a Shared-Respond state and an Exclusive-Respond state. The multiprocessor computer system further comprises a plurality of processors with at least one cache memory associated with each one of the plurality of processors. The multiprocessor computer system further comprises a system memory shared by the plurality of processors, and at least one bus interconnecting the system memory with the plurality of cache memories and the multiple processors.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a primary memory controller to communicate with its primary memory. When there is a cache miss in a CPU, the cache controller routes an address request for primary memory directly to the primary memory via the CPU as a speculative request without access the system bus, and also issues the address request to the system bus to facilitate data coherency. The speculative request is queued in the primary memory controller, which in turn retrieves speculative data from a specified primary memory address. The CPU monitors the system bus for a subsequent transaction that requests the specified data in the primary memory. If the subsequent transaction requesting the specified data is a read transaction that corresponds to the speculative address request, the speculative request is validated and becomes non-speculative.

Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Abstract: A data storage apparatus comprises a plurality of computer processors, each having an internal memory, and a plurality of unshared “clean data present” indicators connected to the plurality of computer processors. Each of the plurality of unshared “clean data present” indicators corresponds to one of the plurality of computer processors. Each of the plurality of computer processors is adapted to assert its corresponding unshared “clean data present” indicator when requested data is contained in its internal memory in an unmodified state.

Abstract: A memory area for storing the data for management of a page and a memory area for storing the data of the page itself are allowed to be distributed and allocated to separate caches. An access request for a storage module is received by a cache module managing the access request, and if a requested page is stored in another cache module, a responding process for the access request is performed jointly with the other cache module.

Abstract: Methods and devices to reduce processor-to-system memory access latency through the use of a memory buffer for the storage of cache lines flushed (cast out) from conventional level-1 (L1) and/or level-2 (L2) processor caches are described. The memory buffer, referred to as a cast-out cache, may be incorporated within a system controller and/or memory controller device.

Abstract: A high-performance cache is disclosed. The cache is designed for time- and space-efficiency for a diverse range of information objects. Information objects are stored in portions of a non-volatile storage device called arenas, which are contiguous regions from which space is allocated in parallel. Objects are substantially contiguously allocated within an arena and are mapped by name keys and content-based object keys to a tag table, an open directory, and a directory table. The tag table is indexed by the name keys, and stores references to sets in the directory table. The tag table is compact and therefore can be stored in fast main memory, facilitating rapid lookups. The directory table is organized so that at least a frequently-accessed portion of it also usually resides in fast main memory, which further speeds lookups. The tag and directory tables are organized to quickly determine non-presence of objects.

Abstract: A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, have diverse cache hardware and each preferably store only data having associated addresses within a respective one of a plurality of subsets of an address space. The diverse cache hardware can include, for example, differing cache sizes, differing associativities, differing sectoring, and differing inclusivities.

Abstract: A memory system comprises a memory, a memory controller and a cache. The memory stores a plurality of data packets, which are associated with a plurality of data types. The memory controller receives requests for data packets from a processing unit and passes requested data packets from the memory to the processing unit. The cache comprises a plurality of independently cached areas. The memory controller passes requested data packets from the memory to the cache. The memory controller passes requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller. The memory controller assigns each independently cached area in the cache to store data packets associated with one item type where an item type may be a texture, thread, task or process. Each independently cached area is associated with a data usage indicator.

Abstract: A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.

Abstract: A memory access architecture and technique employs multiple independent buffers that are configured to store items from memory sequentially. The memory is logically partitioned, and each independent buffer is associated with a corresponding memory partition. The partitioning is cyclically sequential, based on the total number of buffers, K, and the size of the buffers, N. The first N memory locations are allocated to the first partition; the next N memory locations to the second partition; and so on until the Kth partition. The next N memory locations, after the Kth partition, are allocated to the first partition; the next N locations are allocated to the second partition; and so on. When an item is accessed from memory, the buffer corresponding to the item's memory location is loaded from memory, and a prefetch of the next sequential partition commences to load the next buffer.

Abstract: In a system including a collection of cooperating cache servers, such as proxy cache servers, a request can be forwarded to a cooperating cache server if the requested object cannot be found locally. An overload condition is detected if for example, due to reference skew, some objects are in high demand by all the clients and the cache servers that contain those hot objects become overloaded due to forwarded requests. In response, the load is balanced by shifting some or all of the forwarded requests from an overloaded cache server to a less loaded one. Both centralized and distributed load balancing environments are described.

Abstract: A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value for a store instruction is the same as a current value already contained in the memory hierarchy, and discarding the store instruction without issuing any associated cache operation in response to this determination. When a store hit occurs, the current value is retrieved from the local cache. When a store miss occurs, the current value is retrieved from a remote cache by issuing a read request. The comparison may be performed using a portion of the cache line which is less than a granule size of the cache line. A store gathering queue can be use to collect pending store instructions that are directed to different portions of the same cache line.

Abstract: The inventive mechanism uses a cache table to map branch targets. When a fetch instruction is initiated, the inventive mechanism searches the IP-to-TM cache to determine whether the branch target instruction has been optimized and placed into the trace memory. If there is a match with the P-to-TM cache, then the code in the trace is executed. This cache is examined in parallel with Instruction Translation Lookup Buffer (ITLB). If not a match is found in the IP-to-TM cache, the original binary in the physical address provided by the ITLB will be executed.

Abstract: The present invention relates to a method and an arrangement for memory management, where a first memory 3 and a second memory 4 works in parallel, such as two memories belonging to a first 1 and a second 2 parallel working processor. Respective memory 3, 4 can be accessed for read and/or write instructions through a memory-bus 13, 24, in time slots correlated to instruction cycles of the execution work of the processors 3, 4. The second memory is to hold the same information as the first memory. The memory management comprises detecting free time slots on the memory-bus, and the management is only performed in such detected free time slots.

Abstract: A multiprocessor system has a controller for arbitrating a memory access request and a coherency maintenance control process. A coherency maintenance controller for maintaining coherency of data stored in a main memory and data stored in a cache memory has a local access controller which arbitrates between a memory access from a processor in a local buffer and a message for coherency maintenance control in a request buffer according to reply messages accumulated in a reply buffer. A directory memory stores. the state of data stored in the main memory, which includes a state representing that the coherency maintenance control process is being carried out. When the state stored in the directory memory indicates that the coherency maintenance control process is being carried out on data corresponding to an access request, a home access controller saves the access request in the main memory.

Abstract: A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a completion of a request for write to a processing unit. The secondary controller stores the write data and the write time transmitted from the primary controller in the cache memory. At a time, the secondary controller stores the write data in a disk unit in the earlier sequence of the write time. These operations make it possible to guarantee all the write data on or before the reference time.

Abstract: A method for providing a memory scheme in computer architectures in an efficient and cost effective manner. A processor is configured with access to dual-L2 caches, preferably configured to cache program instructions and data in one cache and shared data in another cache. In one embodiment of the present invention, one L2 cache is accessible to networking interface devices. Optionally, the cache accessible by the networking interface devices is configured as networking buffers, providing cache for packet data being sent within a network. By use of this invention, the packet forwarding speeds in a conventional computer architecture may be increased.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: In a computing environment having clients with different semantics or protocols, a capability is provided that enables those clients to share the same data or files. A token management function is provided that allows clients that did not previously support token management to use the token management function to access the shared files. These capabilities are provided without requiring modifications to the client software.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).