Multiple Caches Patents (Class 711/119)
  • Patent number: 11908546
    Abstract: A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Richard C Murphy
  • Patent number: 11907528
    Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: February 20, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Kai Chirca, Daniel Wu, Matthew David Pierson
  • Patent number: 11899937
    Abstract: Systems and methods of a memory allocation buffer to reduce heap fragmentation. In one embodiment, the memory allocation buffer structures a memory arena dedicated to a target region that is one of a plurality of regions in a server in a database cluster such as an HBase cluster. The memory area has a chunk size (e.g., 2 MB) and an offset pointer. Data objects in write requests targeted to the region are received and inserted to the memory arena at a location specified by the offset pointer. When the memory arena is filled, a new one is allocated. When a MemStore of the target region is flushed, the entire memory arenas for the target region are freed up. This reduces heap fragmentation that is responsible for long and/or frequent garbage collection pauses.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 13, 2024
    Assignee: Cloudera, Inc.
    Inventor: Todd Lipcon
  • Patent number: 11892955
    Abstract: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 6, 2024
    Assignee: Microchip Technology Inc.
    Inventors: Sanjay Goyal, Larrie Simon Carr, Patrick Bailey
  • Patent number: 11893062
    Abstract: Technologies described herein can be used for the bulk lazy loading of structured data from a database. A request can be received to initialize an application data structure (such as a structured data object, a hierarchical data structure, an object graph, etc.). The data structure can be analyzed to identify a plurality of child objects of the data structure. Database records associated with the plurality of child objects can then be identified. A loaded child record table can be inspected to determine which of the identified database records are not stored in a cache. A request can be generated, comprising one or more queries to retrieve the uncached subset of database records from the database. Once the uncached subset of records are received from the database, these records can be used, along with the cached subset of the identified database records, to initialize the plurality of child objects of the application data structure.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: February 6, 2024
    Assignee: SAP SE
    Inventors: Frank Emminghaus, Wendeng Li, Zhijie Ai
  • Patent number: 11888938
    Abstract: Systems and methods for optimizing distributed computing systems are disclosed, such as for processing raw data from data sources (e.g., structured, semi-structured, key-value paired, etc.) in applications of big data. A process for utilizing multiple processing cores for data processing can include receiving raw input data and a first portion of digested input data from a data source client through an input/output bus at a first processor core, receiving, from the first processor core, the raw input data and first portion of digested input data by a second processor core, digesting the received raw input data by the second processor core to create a second portion of digested input data, receiving the second portion of digested input data by the first processor core, and writing, by the first processor core, the first portion of digested input data and the second portion of digested input data to a storage medium.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: January 30, 2024
    Assignee: Elasticflash, Inc.
    Inventors: Darshan Bharatkumar Rawal, Pradeep Jnana Madhavarapu, Naoki Iwakami
  • Patent number: 11880350
    Abstract: Resource lock ownership identification is provided across processes and systems of a clustered computing environment by a method which includes saving by a process, based on a user acquiring a resource lock, a lock information record to a shared data structure of the clustered computing environment. The lock information record includes user identification data identifying the user-owner of the resource lock acquired on a system executing the process. The method also includes referencing, by another process, the lock information record of the shared data structure to ascertain the user identification data identifying the user-owner of the resource lock, and thereby facilitate processing within the clustered computing environment.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: January 23, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Kenneth McKnight, Yichong Zhang, Dung Thi Tang, Onno Van den Troost
  • Patent number: 11876677
    Abstract: Some embodiments of the invention provide a method for WAN (wide area network) optimization for a WAN that connects multiple sites, each of which has at least one router. At a gateway router deployed to a public cloud, the method receives from at least two routers at least two sites, multiple data streams destined for a particular centralized datacenter. The method performs a WAN optimization operation to aggregate the multiple streams into one outbound stream that is WAN optimized for forwarding to the particular centralized datacenter. The method then forwards the WAN-optimized data stream to the particular centralized datacenter.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: January 16, 2024
    Assignee: VMware LLC
    Inventors: Igor Golikov, Aran Bergman, Lior Gal, Avishay Yanai, Israel Cidon, Alex Markuze, Eyal Zohar
  • Patent number: 11868254
    Abstract: An electronic device includes a cache, a memory, and a controller. The controller stores an epoch counter value in metadata for a location in the memory when a cache block evicted from the cache is stored in the location. The controller also controls how the cache block is retained in the cache based at least in part on the epoch counter value when the cache block is subsequently retrieved from the location and stored in the cache.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nuwan Jayasena
  • Patent number: 11868613
    Abstract: A method includes defining a plurality of data storage policies, each of the plurality of data storage policies providing rules for storing data among a plurality of data storage locations, each of the plurality of data storage locations having a data storage cost and a data retrieval cost associated therewith; determining a baseline policy distribution among the plurality of data storage policies for an entity; receiving new data items corresponding to the entity; storing the new data items in the plurality of data storage locations using the plurality of data storage policies based on the baseline policy distribution; and determining, using the artificial intelligence engine, a selected one of the plurality of data storage policies to use in storing the new data items corresponding to the entity based on the data storage cost for each of the plurality of data storage locations, and the data retrieval cost for each of the plurality of storage locations.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGE HEALTHCARE HOLDINGS LLC
    Inventors: Philippe Raffy, Jean-Francois Pambrun, David Dubois, Ashish Kumar
  • Patent number: 11863623
    Abstract: Storage devices and systems are capable of dynamically managing QoS requirements associated with host applications via a management interface. The management interface may the enable storage devices to: (i) decide which data needs to be transferred back to the hosts, (ii) choose to skip portions of the data transferred back to the hosts to improve throughput and maintain low cost, and (iii) operate contention resolutions with host applications. Furthermore, storage devices and systems may achieve a virtual throughput that may be greater than its actual physical throughput. The management interface may also be operated at an application level, which advantageously allows the devices and systems the capabilities of managing contention resolutions of host applications, and managing (changing, observing, fetching, etc.) one or more QoS requirements for each host application.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 2, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Patent number: 11855898
    Abstract: Methods, non-transitory computer readable media, network traffic management apparatuses, and network traffic management systems include inspecting a plurality of incoming packets to obtain packet header data for each of the incoming packets. The packet header data is filtered using one or more filtering criteria. At least one of a plurality of optimized DMA behavior mechanisms for each of the incoming packets are selected based on associating the filtered header data for each of the incoming packets with stored profile data. The incoming packets are disaggregated based on the corresponding selected one of the optimized DMA behavior mechanisms.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 26, 2023
    Assignee: F5, Inc.
    Inventor: William Ross Baumann
  • Patent number: 11847057
    Abstract: Disclosed herein are system, method, and computer program product embodiments for utilizing an extended cache to access an object store efficiently. An embodiment operates by executing a database transaction, thereby causing pages to be written from a buffer cache to an extended cache and to an object store. The embodiment determines a transaction type of the database transaction. The transaction type can a read-only transaction or an update transaction. The embodiment determines a phase of the database transaction based on the determined transaction type. The phase can be an execution phase or a commit phase. The embodiment then applies a caching policy to the extended cache for the evicted pages based on the determined transaction type of the database transaction and the determined phase of the database transaction.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: December 19, 2023
    Assignee: SAP SE
    Inventors: Sagar Shedge, Nishant Sharma, Nawab Alam, Mohammed Abouzour, Gunes Aluc, Anant Agarwal
  • Patent number: 11836093
    Abstract: a method and an apparatus for managing a cache for storing content by determining popularity of the content based on content requests received during a current time slot for the content; transmitting information about the popularity of the content to a time-to-live (TTL) controller and receiving, from the TTL controller, TTL values for each popularity level determined by the TTL controller based on the information about the popularity; and managing the content based on the TTL values for each popularity level are provided.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: December 5, 2023
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chunglae Cho, Seungjae Shin, Seung Hyun Yoon, Hong Seok Jeon
  • Patent number: 11829257
    Abstract: Due to the threat of virus attacks and ransom ware, an apparatus and methods for protecting backup storage devices from malicious software virus attacks is explored. An independent backup storage system is connected to a primary storage server over an undiscoverable communications line. The backup storage system is a read-only backup storage system most of the time buffering the backup storage system from a virus or attack on the primary storage server. The backup storage system changes from a read-only backup storage system to a read/write backup storage system only during a backup window of time where data is backed up to the backup storage system. A snapshot of the backup data is maintained in the backup storage system and can be made available at numerous points of time in the past if the data primary storage server becomes corrupted.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: November 28, 2023
    Assignee: Spectra Logic Corporation
    Inventors: David Lee Trachy, Joshua Daniel Carter
  • Patent number: 11822817
    Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a data storage device includes a main non-volatile memory (NVM), a host command queue that lists pending host read and host write commands, and a write cache which temporarily stores write data sets pending transfer to the NVM responsive to execution of the associated host write commands in the host command queue. A collision prediction circuit predicts a rate of future collisions involving the cached write data sets. A storage manager directs storage of the write data sets to a first target location responsive to the rate of future collisions being at a first level, and directs storage of the write data sets to a different, second target location responsive to the rate of future collisions being at a different, second level.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: November 21, 2023
    Assignee: Seagate Technology LLC
    Inventor: Christopher Smith
  • Patent number: 11822479
    Abstract: Techniques for performing cache operations are provided. The techniques include recording an indication that providing exclusive access of a first cache line to a first processor is deemed problematic; detecting speculative execution of a store instruction by the first processor to the first cache line; and in response to the detecting, refusing to provide exclusive access of the first cache line to the first processor, based on the indication.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 21, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul J. Moyer
  • Patent number: 11803593
    Abstract: A system for receiving and propagating efficient search updates includes one or more processors configured to receive, from a first external system via a network, a first entity change request to modify data in an entity associated with the first external system. The first entity change request is saved in an entity store. The received entity change request is pushed from the entity store to an event publisher for forwarding to a streaming service. The first entity change request is classified and forwarded, from the streaming service, to a search index database. The search index is then updated based on the classified entity change request.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: October 31, 2023
    Assignee: COUPANG CORP.
    Inventor: Seung Won Lee
  • Patent number: 11797446
    Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: October 24, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Alper Buyuktosunoglu, Brian Robert Prasky, Jang-Soo Lee, Deanna Postles Dunn Berger
  • Patent number: 11797230
    Abstract: In one example in accordance with the present disclosure, an electronic device is described. The example electronic device includes a NAND flash device to store a static data component of a variable. The example electronic device also includes a NOR flash device to store a dynamic data component of the variable. The electronic device further includes a controller to write the static data component of the variable to the NAND flash device. This controller is also to write the dynamic data component of the variable to the NOR flash device.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: October 24, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Jeffrey Kevin Jeansonne, Khoa Huynh, Mason Andrew Gunyuzlu
  • Patent number: 11789838
    Abstract: Disclosed are methods, systems, and computer-readable medium for preventing system crashes, including loading a resource from a real resource location; receiving a registration request from a resource user; registering the resource user by updating a resource owner registration list to indicate the resource user registration; receiving a first unload request and determining that the resource user is registered by accessing the registration list; upon determining that the resource user is registered, denying the first unload request; generating a stop use request; transmitting the stop use request to the resource user; receiving a deregistration request from the resource user, based on the stop use request; deregistering the resource user by updating the resource owner registration list; receiving a second unload request after deregistering the resource user; and approving the second unload request to unload the resource.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: October 17, 2023
    Assignee: MicroStrategy Incorporated
    Inventors: Yi Luo, Kaijie Yang, Xianting Lu, Sigit Pambudi
  • Patent number: 11789661
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Angelo Della Monica, Eric Kwok Fung Yuen, Pasquale Cimmino, Massimo Iaculo, Francesco Falanga
  • Patent number: 11782716
    Abstract: Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Michael LeMay, Vedvyas Shanbhogue, Deepak Gupta, Ravi Sahita, David M. Durham, Willem Pinckaers, Enrico Perla
  • Patent number: 11778062
    Abstract: A system architecture can be used to facilitate communication among applications that are native and/or non-native to an application environment. The system architecture can include a first application environment executed on a client-side computing device. The first application environment can execute software applications that are native thereto. The first application environment can further execute software applications that are native thereto, but which software applications themselves comprise second application environments of types different from the first application environment, and which software applications can therefore execute additional software applications that are non-native to the first application environment. The first application environment can further execute a computation engine that is configured to store and execute instructions received from the first software application, the second software application, or both.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: October 3, 2023
    Assignee: Palantir Technologies Inc.
    Inventors: Peter Wilczynski, Christopher Hammett, Lloyd Ho, Sharon Hao
  • Patent number: 11749347
    Abstract: In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows, bit lines respectively coupled to the columns, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row based on a current data page. Each memory cell is configured to store a piece of N-bits data at one of 2N levels, where N is an integer greater than 1. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, one multipurpose storage unit, and N?1 data storage units.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: September 5, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Weijun Wan
  • Patent number: 11734177
    Abstract: A memory interface for interfacing between a memory bus and a cache memory, comprising: a plurality of bus interfaces configured to transfer data between the memory bus and the cache memory; and a plurality of snoop processors configured to receive snoop requests from the memory bus; wherein each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: August 22, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Martin John Robinson, Mark Landers
  • Patent number: 11726916
    Abstract: A method, computer program product, and computing system for defining a normal IO write mode for writing data to a storage system including: writing the data to a cache memory system of a first storage node, writing the data to a journal of the first storage node, sending a notification concerning the data to a second storage node, writing one or more metadata entries concerning the data to a journal of the second storage node, sending an acknowledgment signal to the host device, and writing the data to the storage array. A request may be received to enter a testing IO write mode. In response to receiving the request, the data may be written to the cache memory system. The writing of the data to the journal may be bypassed. The acknowledgment signal may be sent to the host device. The data may be written to the storage array.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: August 15, 2023
    Assignee: EMC IP Holding Company, LLC
    Inventors: Geng Han, Vladimir Shveidel, Uri Shabi
  • Patent number: 11726913
    Abstract: Provided are a computer program product, system, and method for using track status information on active or inactive status of track to determine whether to process a host request on a fast access channel. A host request to access a target track is received on a first channel to the host. A determination is made as to whether the target track has active or inactive status. The target track has active status when at least one process currently maintains a lock on the target track that prevents access and the target track has inactive status when no process maintains a lock on the target track that prevents access. Fail is returned to the host to cause the host to resend the host request on a second channel in response to the target track having the active status. The first channel has lower latency than the second channel.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 15, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11720498
    Abstract: An arithmetic processing device including: request issuing units configured to issue an access request to a storage; and banks each of which includes: a first cache area including first entries; a second cache area including second entries; a control unit; and a determination unit that determines a cache hit or a cache miss for each of the banks, wherein the control unit performs: in response that the access requests simultaneously received from the request issuing units make the cache miss, storing the data, which is read from the storage device respectively by the access requests, in one of the first entries and one of the second entries; and in response that the access requests simultaneously received from the request issuing units make the cache hit in the first and second cache areas, outputting the data retained in the first and second entries, to each of issuers of the access requests.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: August 8, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Katsuhiro Yoda
  • Patent number: 11704251
    Abstract: The present disclosure relates to devices and methods for using a banked memory structure with accelerators. The devices and methods may segment and isolate dataflows in datapath and memory of the accelerator. The devices and methods may provide each data channel with its own register memory bank. The devices and methods may use a memory address decoder to place the local variables in the proper memory bank.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: July 18, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Stephen Sangho Youn, Steven Karl Reinhardt, Hui Geng
  • Patent number: 11687459
    Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: June 27, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Michael Malewicki, Thomas McGee, Michael S. Woodacre
  • Patent number: 11687417
    Abstract: Due to the threat of virus attacks and ransom ware, an apparatus and methods for protecting backup storage devices from malicious software virus attacks is explored. An independent backup storage system is connected to a primary storage server over an undiscoverable communications line. The backup storage system is a read-only backup storage system most of the time buffering the backup storage system from a virus or attack on the primary storage server. The backup storage system changes from a read-only backup storage system to a read/write backup storage system only during a backup window of time where data is backed up to the backup storage system. A snapshot of the backup data is maintained in the backup storage system and can be made available at numerous points of time in the past if the data primary storage server becomes corrupted.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: June 27, 2023
    Assignee: Spectra Logic Corporation
    Inventors: David Lee Trachy, Joshua Daniel Carter
  • Patent number: 11683394
    Abstract: Systems and methods for isolating applications associated with multiple tenants within a computing platform receive a request from a client associated with a tenant for running an application on a computing platform. Hosts connected to the platform are associated with a network address and configured to run applications associated with multiple tenants. A host is identified based at least in part on the request. One or more broadcast domain(s) including the identified hosts are generated. The broadcast domains are isolated in the network at a data link layer. A unique tenant identification number corresponding to the tenant is assigned to the broadcast domains. In response to launching the application on the host: the unique tenant identification number is assigned to the launched application and is added to the network address of the host; and the network address of the host is sent to the client associated with the tenant.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: June 20, 2023
    Assignee: Palantir Technologies Inc.
    Inventors: Greg DeArment, Divyanshu Arora, Jason Hoch, Mark Elliot, Matthew Williamson, Robert Kruszewski, Steven Austin
  • Patent number: 11677624
    Abstract: An indication that a client system has connected to a server system that is associated with a network file system may be received. In response to the indication that the client system has connected to the server system, a number of client systems that are connected to the server system may be determined. The network file system may be configured in view of the determined number of client systems that are connected to the server system. Access to the network file system may be provided to the client system in response to configuring the network file system in view of the determined number of client systems that are connected to the server system.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 13, 2023
    Assignee: Red Hat, Inc.
    Inventors: Poornima Gurusiddaiah, Amar Tumballi Suryanarayan
  • Patent number: 11675703
    Abstract: A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: June 13, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William L. Walker, William E. Jones
  • Patent number: 11669471
    Abstract: A method, computer program product, and computing system for receiving an input/output (IO) command for processing data within a storage system. An IO command-specific entry may be generated in a register based upon, at least in part, the IO command. An compare-and-swap operation may be performed on the IO command-specific entry to determine an IO command state associated with the IO command. The IO command may be processed based upon, at least in part, the IO command state associated with the IO command.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: June 6, 2023
    Assignee: EMC IP Holding Company, LLC
    Inventors: Eldad Zinger, Ran Anner, Amit Engel
  • Patent number: 11663207
    Abstract: Systems, devices, and techniques are disclosed for translation of tenant identifiers. A record may be received. A value of a tenant identifier for the record may be determined from a key for the record or a scan descriptor. The value of the tenant identifier in the key for the record may be replaced with a new value for the tenant identifier. A bitmap stored in a record header of the record may be used to identify columns of the record that stored an encoded value of the tenant identifier. An encoded new value of the tenant identifier may be stored in columns identified by the bitmap stored in the record header that include an attribute indicating that tenant identifier translation is enabled.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 30, 2023
    Assignee: Salesforce, Inc.
    Inventor: Thomas Fanghaenel
  • Patent number: 11656995
    Abstract: A method comprising receiving a memory access request comprising an address of data to be accessed and determining an access granularity of the data to be accessed based on the address of the data to be accessed. The method further includes, in response to determining that the data to be accessed has a first access granularity, generating first cache line metadata associated with the first access granularity and in response to determining that the data to be accessed has a second access granularity, generating second cache line metadata associated with the second access granularity. The method further includes storing the first cache line metadata and the second cache line metadata in a single cache memory component.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Robert M. Walker
  • Patent number: 11645390
    Abstract: A next generation antivirus (NGAV) security solution in a virtualized computing environment includes a security sensor at a virtual machine that runs on a host and a security engine remote from the host. The integrity of the NGAV security solution is increased, by providing a verification as to whether a verdict issued by the security engine has been successfully enforced by the security sensor to prevent execution of malicious code at the virtual machine.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: May 9, 2023
    Assignee: VMWARE, INC.
    Inventors: Shirish Vijayvargiya, Vasantha Kumar Dhanasekar, Sachin Shinde, Rayanagouda Bheemanagouda Patil
  • Patent number: 11640357
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 2, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Michael Hippleheuser
  • Patent number: 11625251
    Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 11, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Varun Agrawal, Yasuko Eckert
  • Patent number: 11620225
    Abstract: A circuit and corresponding method map memory addresses onto cache locations within set-associative (SA) caches of various cache sizes. The circuit comprises a modulo-arithmetic circuit that performs a plurality of modulo operations on an input memory address and produces a plurality of modulus results based on the plurality of modulo operations performed. The plurality of modulo operations performed are based on a cache size associated with an SA cache. The circuit further comprises a multiplexer circuit and an output circuit. The multiplexer circuit outputs selected modulus results by selecting modulus results from among the plurality of modulus results produced. The selecting is based on the cache size. The output circuit outputs a cache location within the SA cache based on the selected modulus results and the cache size. Such mapping of the input memory address onto the cache location is performed at a lower cost relative to a general-purpose divider.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: April 4, 2023
    Assignee: Marvell Asia Pte Ltd
    Inventor: Albert Ma
  • Patent number: 11620141
    Abstract: Methods and systems are provided for a browser in a client device that receives a user interface script-code snippet from a web page. A chain logic engine determines whether an in-memory map indicates an output value of prior execution of the UI script-code snippet. If the in-memory map does indicate the output value, it is returned from the in-memory map to generate the user interface. If not, the engine determines whether an in-local storage map indicates the prior executed snippet output. If the in-local storage map indicates the prior executed snippet output, it is returned from the in-local storage map to generate the user interface, and it is stored in the in-memory map. If not, the UI script-code snippet is executed to generate the output value, which is used to generate the user interface, and is stored in the in-memory map and in the in-local storage map.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: April 4, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Itamar Azulay, Amir Geri, Guy Lewin, Yossi Haber, Meir Baruch Blachman
  • Patent number: 11610281
    Abstract: A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: March 21, 2023
    Inventors: Sushant Kondguli, Arun Radhakrishnan, Zachary D. Neyland, David C. Tannenbaum
  • Patent number: 11593265
    Abstract: A graphics processing system is disclosed having a cache system (24) arranged between memory (23) and the graphics processor (20), the cache system comprising a first cache (53) for transferring data to and from the graphics processor (20) and a second cache (54) arranged and configured to transfer data between the first cache (53) and memory (23). When data is to be written from the first cache (53) to memory (23), a cache controller (55) determines a data type of the data and, in dependence on the data type, either causes the data to be written into the second cache (54) without writing the data to memory (23), or causes the data to be written to memory (23) without storing the data in the second cache (54). In embodiments the second cache (54) is write-only allocated.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 28, 2023
    Assignee: Arm Limited
    Inventor: Olof Henrik Uhrenholt
  • Patent number: 11586388
    Abstract: Storage systems are disclosed. For instance, a storage system comprises a first storage device of a first type and a second storage device of a second type, and the first storage device has a higher access velocity than the second storage device. A threshold indicating a volume limit of data stored in the first storage device can be determined. Data, which is specified by a write request for writing data to the storage system, is written to the first storage device in response to determining the data amount in the first storage device is lower than the threshold. A read request from a client device is processed based on data stored in the first storage device. Consequently, the first storage device with a higher access velocity in the storage system may be utilized as much as possible, so that storage device latency in the storage system is managed more effectively.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 21, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Willa Lang Yuan, Chark Wenshuai Yu
  • Patent number: 11556473
    Abstract: Embodiments of the present disclosure relate to cache memory management. One or more global caches are dynamically partitioned and sized into one or more cache partitions based on anticipated input/output (IO) workloads.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: January 17, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Owen Martin, Vladimir Desyatov, Michael Scharland
  • Patent number: 11556344
    Abstract: Embodiments herein describe transferring ownership of data (e.g., cachelines or blocks of data comprising multiple cachelines) from a host to hardware in an I/O device. In one embodiment, the host and I/O device (e.g., an accelerator) are part of a cache-coherent system where ownership of data can be transferred from a home agent (HA) in the host to a local HA in the I/O deviceā€”e.g., a computational slave agent (CSA). That way, a function on the I/O device (e.g., an accelerator function) can request data from the local HA without these requests having to be sent to the host HA. Further, the accelerator function can indicate whether the local HA tracks the data on a cacheline-basis or by a data block (e.g., multiple cachelines). This provides flexibility that can reduce overhead from tracking the data, depending on the function's desired use of the data.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 17, 2023
    Assignee: XILINX, INC.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 11550646
    Abstract: The present disclosure provides a method and a system of verifying access by a multi-core interconnect to an L2 cache in order to solve problems of delays and difficulties in locating errors and generating check expectation results. A consistency transmission monitoring circuitry detects, in real time, interactions among a multi-core interconnects system, all single-core processors, an L2 cache and a primary memory, and sends collected transmission information to an L2 cache expectation generator and a check circuitry. The L2 cache expectation generator obtains information from a global memory precise control circuitry according to a multi-core consistency protocol and generates an expected result. The check circuitry is responsible for comparing the expected result with an actual result, thus implementing determination of multi-core interconnect's access accuracy to the L2 cache without delay.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: January 10, 2023
    Assignee: C-SKY Microsystems Co., Ltd.
    Inventor: Taotao Zhu
  • Patent number: 11543981
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM), and control circuitry configured to receive a plurality of access commands, process the plurality of access commands using a customer prediction model to predict a customer of the data storage device, wherein the customer prediction model is trained off-line based on access patterns of a plurality of different customers. The control circuitry then configures access to the NVSM based on the predicted customer.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chun S. Tsai, Dean V. Dang, Jillian D. Passioukov, Colin W. Morgan