Abstract: A method for allocating memory in a computing device having a non-volatile main memory is described. The method comprises receiving, by a memory allocator, a request for non-volatile memory allocation of an object from a program executing on the computing device, the request comprising a requested memory size and registration data from the program. The method comprises finding an available address of one of a plurality of portions of a page of the non-volatile memory and searching an active page table in the non-volatile main memory to find the page and if the page is not found in the active page table: inserting the page into the active page table; and waiting for a memory write for inserting the page into the active page table to complete.

Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

Abstract: A multi-core architecture including: a plurality of processing devices, each processing device including a single processor or a cluster of processors; and a lock manager associated with each processing device, each lock manager being configured to: store a first data value indicating of whether or not it currently owns a first lock, the first lock authorizing access to a resource; and permit an owner of the first lock to be determined by one or more lock managers by broadcasting, over an interconnection network to each of the other lock managers, at least one message.

Abstract: An application and system fast launch may provide a virtual memory address area (VMA) container to manage the restore of a context of a process, i.e., process context, saved in response to a checkpoint to enhance performance and to provide a resource efficient fast launch. More particularly, the fast launch may provide a way to manage, limit and/or delay the restore of a process context saved in response to a checkpoint, by generating a VMA container comprising VMA container pages, to restore physical memory pages following the checkpoint based on the most frequently used or predicted to be used. The application and system fast launch with the VMA container may avoid unnecessary input/output (I/O) bandwidth consumption, page faults and/or memory copy operations that may otherwise result from restoring the entire context of a VMA container without regard to frequency of use.

Abstract: A system architecture can be used to facilitate communication among applications that are native and/or non-native to an application environment. The system architecture can include a first application environment executed on a client-side computing device. The first application environment can execute software applications that are native thereto. The first application environment can further execute software applications that are native thereto, but which software applications themselves comprise second application environments of types different from the first application environment, and which software applications can therefore execute additional software applications that are non-native to the first application environment. The first application environment can further execute a computation engine that is configured to store and execute instructions received from the first software application, the second software application, or both.

Abstract: A computer system includes a use state analysis program that acquires a use history of data in a first computer system and a program that uses the data; and a data migration program that extracts data that is able to be migrated from the first computer system to a second computer system on the basis of the use history, writes the migratable data to a first storage system and a second storage system, and migrates a program to the second computer system on the basis of a use history of the data used by the program.

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

Abstract: A memory system may include a cache memory, a nonvolatile memory, a write back wait queue, and a controller. To evict an eviction cache entry including a target transaction ID from the memory cache to the nonvolatile memory, the controller performs write back operations on cache entries respectively corresponding to waiting entries at a head of the write back wait queue until a waiting entry including the target transaction ID arrives at the head of the write back wait queue, and then performs a write back operation on the eviction cache entry.

Abstract: Shared memory caching resolves latency issues in computing nodes associated with a cluster in a virtual computing environment. A portion of random access memory in one or more of the computing nodes is allocated for shared use by the cluster. Whenever local cache memory is unable in one of the computing nodes, a cluster neighbor cache allocated in a different computing node may be utilized as remote cache memory. Neighboring computing nodes may thus share their resources for the benefit of the cluster.

Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.

Abstract: Systems and techniques for automatic smart propagation of caching directives are described herein. A request may be received for an object of a webpage. A cache state may be determined for a cache control header retrieved for the object. A time to live value may be calculated for the object based on the cache state and a header time to live value included in the cache control header. A cache directive that includes the time to live value may be stored for the object in a cache. The object may be updated in the cache upon receipt of a subsequent request based on the cache directive.

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

Abstract: A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.

Abstract: Lazy Persistency (LP), a software persistency method that allows caches to slowly send dirty blocks to the non-volatile main memory (NVMM) through natural evictions. With LP, there are no additional writes to NVMM, no decrease in write endurance, and no performance degradation from cache line flushes and barriers. Persistency failures are discovered using software error detection (checksum), and the system recovers from them by recomputing inconsistent results. LP was evaluated and compared to the state-of-the-art Eager Persistency technique from prior work. Compared to Eager Persistency, LP reduces the execution time and write amplification overheads from 9% and 21% to only 1% and 3%, respectively.

Abstract: A method of shuffling turbo-write buffers of a universal flash storage system is described. The method includes periodically determining a performance index of each turbo-write buffer allocated to a unique logical unit number of the universal flash storage system. The method also includes shifting a position of at least two of the turbo-write buffers according to the performance index of each of the turbo-write buffers and a threshold performance level.

Abstract: Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.

Abstract: Non-volatile storage circuitry is provided as primary storage accessible to processing circuitry, e.g. as registers, a cache, scratchpad memory, TLB or on-chip RAM. Power control circuitry powers down a given region of the non-volatile storage circuitry when information stored in said given region is not being used. This provides opportunities for more frequent power savings than would be possible if primary storage was implemented using volatile storage.

Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.

Abstract: The disclosed computer-implemented method for distributing information across failure domains in servers may include (1) dividing, at a computing device, each of a quantity of “K” failure domains (FDs) in a plurality of FDs into a quantity of “P” portions, where the “K” FDs in the plurality of FDs are constituent parts of respective servers in a plurality of servers, “P” is less than “K,” and “P” is a sum of a quantity of “M” data portions and a quantity of “N” parity portions, (2) creating a quantity of “K” erasure-coded volumes in the “K” FDs, where each erasure-coded volume includes “M” data portions and “N” parity portions, and each portion in each erasure-coded volume is stored in a different FD and (3) combining the “K” volumes to create a file system. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The static data masking system may perform one or more operations including unbinding tables in a database, evaluating masking operations on the tables to determine that at least one masking operation on a particular column of a candidate table is a complex masking operation that cannot be completed using a query, adding a temporary key column with unique values to the candidate table, generating a temporary table including the temporary key column and an empty masked column, generating masked values for the particular column at a client, and populating the masked values for the particular column in the empty masked column of the temporary table.

Abstract: Three new software instructions assist a processor in performing indirect prefetching, and managing a next-to-prefetch address list. The software instructions populate hardware register locations according to a hardware register description comprising a data structure of at least seven fields. Multiple instances of the data structure, shared across multiple respectively corresponding threads running concurrently, comprise an indirect-prefetch-tracker table. The indirect-prefetch-tracker table assists the processor to efficiently perform indirect prefetching, from random (not necessarily contiguous) memory locations, and reduces processor core real estate dedicated to control and management of data prefetch and loading operations.

Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.

Abstract: A dedicated input/output (I/O) cache can be used for I/O-to-processor communications. Data received from an I/O device can be written to the I/O cache and also written to a device memory that is accessible to the processor. The processor can then access the data in the fast, dedicated I/O cache if available. Otherwise, the processor can read the data from the memory into a conventional processor cache for processing. Writes to the cache can be full or partial, with partial writes utilizing padding in some embodiments. The data can be written sequentially in a circular manner. Data processed by the processor can be invalidated, and invalidated data can be overwritten on a subsequent write. Phase bits can also be used to indicate the pass during which various writes were performed.

Abstract: A system and method for providing erasure code data protection for an array of solid state drives. The solid state drives are connected to an Ethernet switch which includes a RAID control circuit, or a state machine, to process read or write commands that may be received from a remote host. The RAID control circuit, if present, uses a low-latency cache to execute write commands, and the state machine, if present, uses a local central processing unit, which in turn uses a memory as a low-latency cache, to similar effect.

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.

Abstract: The present disclosure is related to performing speculation in, for example, a memory device or a computing system that includes a memory device. Speculation can be used to identify data that is accessed together or to predict data that will be accessed with greater frequency. The identified data can be organized to improve efficiency in providing access to the data.

Abstract: Distributed computing system functionality is enhanced. Transmission of data changes may be incremental, thus reducing bandwidth usage and latency. Data changes may be propagated over geographic distances in an outward-only manner from a central data store to one or more servers or other remote nodes, using proactive updates as opposed to making cache updates only in reaction to cache misses. Cache expiration and eviction may be reduced or avoided as mechanisms for determining when cached data is modified. A central computing environment may proactively push incremental data entity changes to place them in remote data stores. Remote nodes proactively check their remote data store, find changes, pull respective selected changes into their remote node caches, and provide current data in response to service requests. Data may be owned by particular tenants. Data pulls may be limited to data in selected categories, data of recently active tenants, or both.

Abstract: Embodiments of the present systems and methods may provide techniques to provide simple and accurate estimate of memory requirements for application invocation in a serverless environment. For example, a method may comprise selecting sample invocations of functions as a service from a larger plurality of invocations, submitting for execution the plurality of sample invocations and, for each sample invocation, submitting a specification of a memory size to be used for execution of each sample invocation, determining, whether the specification of the memory size to be used for execution of each sample invocation results in unsuccessful execution of at least some of the sample invocations due to insufficient memory and, if so, adjusting the specification of the memory size for at least some of the sample invocations, and submitting for execution at least those invocations in the larger plurality of invocations that were not included in the plurality of sample invocations.

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

Abstract: Described herein is a method for tracking changes to memory locations made by an application. In one embodiment, the application decides to start tracking and sends a list of virtual memory pages to be tracked to an operating system via an interface. The operating system converts the list of virtual memory pages to a list of physical addresses and sends the list of physical addresses to a hardware unit which performs the tracking by detecting write backs on a coherence interconnect coupled to the hardware unit. After the application ends tracking, the application requests a list of dirty cache lines. In response to the request, the operating system obtains the list of dirty cache lines from the hardware unit and adds the list to a buffer that the application can read. In other embodiments, the operating system can perform the tracking without the application making the request.

Abstract: A cache management method for a computing device, a cache controller, a processor and a processor readable storage medium are disclosed. The cache management method for the computing device includes classifying a workload on a cache based on a cache architecture of the computing device, characteristics of a cache level of the cache and a difference in the workload on the cache, and configuring a priority for the classified workload; and allocating a cache resource and performing cache management according to the configured priority.

Abstract: Embodiments disclosed herein provide systems, methods, and computer-readable media to implement an object store with removable storage media. In a particular embodiment, a method provides identifying first data for storage on a first removable storage medium and designating at least a portion of the first data to a first data object. The method further provides determining a first location where to store the first data object in a first value store partition of the first removable storage medium and writing the first data object to the first location. Also, the method provides writing a first key that identifies the first data object and indicates the first location to a first key store partition of the first removable storage medium.

Abstract: A storage system is coupled to another storage system and a higher-level apparatus via a network, and copies write data received from the higher-level apparatus to the other storage system. This storage system is provided with interface units, each provided with a plurality of ports that can be coupled to the network; and a plurality of controllers coupled to a respective one of the interface units. Each controller has a processor unit. When each processor unit receives write data from the higher-level apparatus via a first port coupled to the interface unit that is coupled to the controller to which the processor unit belongs, the processor unit selects, from among the ports of the interface unit coupled to the controller to which the processor unit belongs, a second port for transmitting the write data to the other storage system, and transmits the write data to the other storage system.

Abstract: Methods and systems for detecting disparate incidents in processed data using a plurality of machine learning models. For example, the system may receive native asset data. The system may extract telemetry data from the native asset data. The system may input the first feature input into a first machine learning model, wherein the first machine learning model is trained to detect known incidents of a first type in a first set of labeled telemetry data. The system may then detect a first incident based on a first output from the first machine learning model, wherein the first incident is a first event in an asset related to the user's behavior.

Abstract: A computer-implemented method, according to one approach, includes: receiving write requests, accumulating the write requests in a destage buffer, and determining a current read heat value of each logical page which corresponds to the write requests. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Furthermore, data in the write requests is destaged from the write queues to their respective page stripes. Other systems, methods, and computer program products are described in additional approaches.

Abstract: Hardware assisted remote transactional memory including receiving, from a first remote processor over a high-speed communications fabric, an indication of a beginning of a first memory transaction; queuing, in a first hardware memory assistant, memory instructions for the first memory transaction; receiving, from a second remote processor over the high-speed communications fabric, an indication of a beginning of a second memory transaction; queuing, in a second hardware memory assistant, memory instructions for the second memory transaction; receiving, from the first remote processor over the high-speed communications fabric, an indication of an ending of the first memory transaction; comparing memory addresses accessed in the first memory transaction to memory addresses accessed in the second memory transaction; and in response to determining that the memory addresses accessed in the first memory transaction overlap with the memory addresses accessed in the second memory transaction, aborting the first memor

Abstract: A multi-controller memory system includes a flexible channel memory controller coupled to at least first and second physical interfaces. The second physical interface is also coupled to an auxiliary memory controller. The physical interfaces may be coupled to separate memory modules. In a single-channel control mode, the memory controllers respectively control the memory modules coupled to the first and second physical interface. In a multi-channel control mode, the flexible channel memory controller controls both memory modules while the auxiliary memory controller is inactive. In a single-channel control mode, the memory controllers coordinate restricted memory control commands which access a resource shared by both modules, by one controller transmitting a request signal for the resource to the other controller, awaiting an acknowledgment signal from the other controller, and maintaining transmission of the request signal until the use of the resource is completed.

Abstract: Determining storage of particular data in cache memory of a storage device includes using a first mechanism to determine when to remove the particular data from the cache memory and using a second mechanism, independent from the first mechanism, to inhibit the particular data from being stored in the cache memory independent of whether the first mechanism otherwise causes the particular data to be stored in the cache memory. The first mechanism may remove data from the cache memory that was least recently accessed. The second mechanism may be based, at least in part, on a prediction value of an expected benefit of storing the particular data in the cache memory. The prediction value may be determined based on input data corresponding to measured cache read hits (RH), cache write hits (WH), cache read misses (RM), cache write destage operations (WD), and prefetch reads (PR) for the particular data.

Abstract: The present teaching relates to a method, system, and programming for determining a source of a data object. A first average latency of a plurality of users in accessing the data object from the first data source is computed, wherein the first data source was previously identified as being the source of the data object. From each of other data sources, a second average latency of the plurality of users in accessing the data object from the other data source is obtained. In response to the first data source satisfying a first criterion associated with the first average latency, the first data source is maintained to be the source of the data object. In response to the first data source violating the first criterion, one of the other data sources that satisfies a second criterion associated with the second average latency is deemed as the source of the data object.

Abstract: Techniques are disclosed for identifying data streams in a processor that are likely to benefit from data prefetching. A prefetcher receives at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams. The prefetcher assigns a confidence level to the the first request based on an amount of confirmations observed in the stream. The request is in a confident state if the confidence level exceeds a specified value. The first request is in a non-confident state if the confidence level does not exceed the specified value. Doing so allows a memory controller to determine whether to drop the at least the first request based on the confidence level and a memory resource utilization threshold.

Abstract: A system and method for efficiently supporting a cache memory hierarchy potentially using a zero size cache in a level of the hierarchy. In various embodiments, logic in a lower-level cache controller or elsewhere receives a miss request from an upper-level cache controller. When the requested data is non-cacheable, the logic sends a snoop request with an address of the memory access operation to the upper-level cache controller to determine whether the requested data is in the upper-level data cache. When the snoop response indicates a miss or the requested data is cacheable, the logic retrieves the requested data from memory. When the snoop response indicates a hit, the logic retrieves the requested data from the upper-level cache. The logic completes servicing the memory access operation while preventing cache storage of the received requested data in a cache at a same level of the cache memory hierarchy as the logic.

Abstract: A multi-level caching method and a multi-level caching system for enhancing a graph processing performance are provided. The multi-level caching method includes searching for graph data associated with a query from a first cache memory in which data output in response to a previous query request is stored, when a query request for the query is received, re-searching for the graph data from a second cache memory in which neighboring data with a history of an access to each of data stored in the first cache memory is stored, when the graph data is not found in the first cache memory, and outputting first neighboring data found by the re-searching as the graph data when a response to the query request is output.

Abstract: Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.

Abstract: An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.

Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.

Abstract: A memory cache controller includes a transaction arbiter circuit and a retry queue circuit. The transaction arbiter circuit may determine whether a received memory transaction can currently be processed by a transaction pipeline. The retry queue circuit may queue memory transactions that the transaction arbiter circuit determines cannot be processed by the transaction pipeline. In response to receiving a memory transaction that is a cache management transaction, the retry queue circuit may establish a dependency from the cache management transaction to a previously stored memory transaction in response to a determination that both the previously stored memory transaction and the cache management transaction target a common address. Based on the dependency, the retry queue circuit may initiate a retry, by the transaction pipeline, of one or more of the queued memory transactions in the retry queue circuit.

Abstract: Allocation of storage array hardware resources between host-visible and host-hidden services is managed to ensure that sufficient hardware resources are allocated to host-visible services. Information obtained from monitoring real-world operation of the storage array is used to generate a model of the storage array. The generated model represents temporal dependencies between storage array hardware, host-visible services, and host-hidden services. Because the model includes information gathered over time and represents temporal dependencies, future occurrence of repeating variations of storage-related service usage and requirements can be predicted. The model may be used to generate hardware recommendations and dynamically re-allocate existing hardware resources to more reliably satisfy a predetermined level of measured performance.

Abstract: A method of managing a direct-mapped cache is provided. The method includes a direct-mapped cache receiving memory references indexed to a particular cache line, using a first cache line replacement algorithm to select a main memory block as a candidate for storage in the cache line in response to each memory reference, and using a second cache line replacement algorithm to select a main memory block as a candidate for storage in the cache line in response to each memory reference. The method further includes identifying, over a plurality of most recently received memory references, which one of the algorithms has selected a main memory block that matches a next memory reference a greater number of times, and storing a block of main memory in the cache line, wherein the block of main memory stored in the cache line is the main memory block selected by the identified algorithm.

Abstract: A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.

Abstract: Loading of a page into memory of an in-memory database system is initiated. Thereafter, a new page size for the page in memory is allocated corresponding to a greater of a current page size and an intended page size. Later, the page is loaded into the allocated memory so that a consistent change can be opened. Content within the page is reorganized according to the new page size followed by the consistent change being closed.