Parallel Caches Patents (Class 711/120)
  • Patent number: 8082465
    Abstract: A system, method and computer program product for detecting a failed storage device within an “n” device array. The “n” device array is configured to store “n” device array formatted data. The “n” device array is reconfigured into an “n?1” device array. The “n” device array formatted data is written to the “n?1” device array in an “n?1” device array format.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: December 20, 2011
    Assignee: EMC Corporation
    Inventors: Kiran Madnani, David W. DesRoches
  • Patent number: 8074026
    Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: December 6, 2011
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Christopher J. Hughes, Yen-Kuang Chen, Partha Kundu
  • Patent number: 8065485
    Abstract: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: November 22, 2011
    Assignee: Oracle America, Inc.
    Inventors: Gideon N. Levinsky, Paul Caprioli, Sherman H. Yip
  • Patent number: 8051248
    Abstract: In one embodiment, a processor comprises an execution core, a level 1 (L1) data cache coupled to the execution core and configured to store data, and a transient/transactional cache (TTC) coupled to the execution core. The execution core is configured to generate memory read and write operations responsive to instruction execution, and to generate transactional read and write operations responsive to executing transactional instructions. The L1 data cache is configured to cache memory data accessed responsive to memory read and write operations to identify potentially transient data and to prevent the identified transient data from being stored in the L1 data cache. The TTC is also configured to cache transaction data accessed responsive to transactional read and write operations to track transactions. Each entry in the TTC is usable for transaction data and for transient data.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Frank, David J. Leibs, Michael J. Haertel
  • Publication number: 20110258393
    Abstract: Methods of protecting cache data are provided. For example, various methods are described that assist in handling dirty write data cached in memory by duplication into other locations to protect against data loss. One method includes caching a data item from a data source in a first cache device. The data item cached in the first cache device is designated with a first designation. In response to the data item being modified by a data consumer, the designation of the data item in the first cache device is re-assigned from the first designation to a second designation, and the data item with the second designation is copied to a second cache device.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 20, 2011
    Inventors: Jonathan Flower, Nadesan Narenthiran
  • Patent number: 8035650
    Abstract: Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the program's cache usage, the available tiles, and/or other factors. A cache controller identifies the tiles assigned to the programs and generates cache addresses for accessing the cache. The cache may be partitioned into physical tiles. The cache controller may assign logical tiles to the programs and may map the logical tiles to the physical tiles within the cache. The use of logical and physical tiles may simplify assignment and management of the tiles.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: October 11, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Guofang Jiao, Chun Yu, De Dzwo Hsu
  • Patent number: 7996548
    Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: August 9, 2011
    Assignee: Intel Corporation
    Inventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
  • Patent number: 7970999
    Abstract: An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data processing node also includes interface logic configured to receive signals from the interconnect and to apply the signals from the interconnect to affect the content of the cache, and to receive signals from the mass storage and to apply the signals from the mass storage to affect the content of the cache. The content of the mass storage and cache of a particular node may also be provided to other nodes of the system, via the interconnect.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: June 28, 2011
    Assignee: ARRIS Group
    Inventor: Robert C Duzett
  • Patent number: 7970998
    Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Takao Yamamoto, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko, Hazuki Okabayashi
  • Publication number: 20110145553
    Abstract: Handling parallelism in transactions. One embodiment includes a method that includes beginning a cache resident transaction. The method further includes encountering a nested structured parallelism construct within the cache resident transaction. A determination is made as to whether the transaction would run faster serially in cache resident mode or faster parallel in software transactional memory mode for the overall transaction. In the software transactional memory mode, cache resident mode is used for one or more hierarchically lower nested transactions. The method further includes continuing the transaction in the mode determined.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Yosseff Levanoni, David L. Detlefs, Jan S. Gray
  • Patent number: 7941604
    Abstract: A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: May 10, 2011
    Assignee: Infineon Technologies AG
    Inventors: Raj Kumar Jain, Xiao Ni Wei, Pin Xing Lin
  • Patent number: 7890795
    Abstract: A system, method and computer program product for detecting a failed storage device within an “n” device array. The “n” device array is configured to store “n” device array formatted data. The “n” device array is reconfigured into an “n?1” device array. The “n” device array formatted data is written to the “n?1” device array in an “n?1” device array format.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: February 15, 2011
    Assignee: EMC Corporation
    Inventors: Kiran Madnani, David W. DesRoches
  • Publication number: 20110022801
    Abstract: An apparatus, system, and method are disclosed for redundant write caching. The apparatus, system, and method are provided with a plurality of modules including a write request module, a first cache write module, a second cache write module, and a trim module. The write request module detects a write request to store data on a storage device. The first cache write module writes data of the write request to a first cache. The second cache write module writes the data to a second cache. The trim module trims the data from one of the first cache and the second cache in response to an indicator that the storage device stores the data. The data remains available in the other of the first cache and the second cache to service read requests.
    Type: Application
    Filed: July 30, 2010
    Publication date: January 27, 2011
    Inventor: David Flynn
  • Patent number: 7873785
    Abstract: A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: January 18, 2011
    Assignee: Oracle America, Inc.
    Inventor: Kunle A. Olukotun
  • Patent number: 7861040
    Abstract: A memory apparatus including: a cache control section to control a cache memory for an auxiliary storage apparatus; a volatile memory; and a nonvolatile memory, wherein the cache memory for the auxiliary storage apparatus is configured to have a volatile cache memory provided in the volatile memory and a nonvolatile cache memory provided in the nonvolatile memory, and wherein the cache control section accesses the nonvolatile cache memory using a write back method.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: December 28, 2010
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Kenji Okuyama, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi
  • Patent number: 7853752
    Abstract: A multicore processor includes a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more input/output modules configured to couple data between an input/output interface and at least one of a memory interface and a cache memory. Each of at least some of the cache memories is assigned as a home location for caching a corresponding portion of the main memory, and is configured to maintain the cache memory based on whether a processor core or an input/output module is requesting access to the cache memory.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: December 14, 2010
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Matthew Mattina
  • Patent number: 7822814
    Abstract: Method, apparatus and article of manufacture for acquiring a buffer after data from a remote sender (e.g., client) has been received by a local machine (e.g., server). Because the client data has already been received when the buffer is acquired, the buffer may be sized exactly to the size of the client data. In general, the buffer may be caller supplied or system supplied.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: October 26, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark Linus Bauman, Bob Richard Cernohous, Kent L. Hofer, John Charles Kasperski, Steven John Simonson, Jay Robert Weeks
  • Publication number: 20100268880
    Abstract: Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATION
    Inventors: Ravi Kumar Arimilli, Donald W. Plass, William John Starke
  • Patent number: 7814270
    Abstract: A storage system is arranged to speed up the operation and easily duplicate data without the capacity of the cache memory being so large even if lots of host computers are connected with the storage system. This storage system includes channel adapters, disk drives, disk adapters, and network switches. Further, the front side cache memories connected with the channel adapters and the back side cache memories connected with the disk adapters are provided as two layered cache system. When a request for writing data is given to the storage system by the host computer, the data is written in both the front side cache memory and the back side cache memory. The write data is duplicated by placing the write data in one of the front side cache memories and one of the back side cache memories or two of the back side cache memories.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: October 12, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Publication number: 20100228919
    Abstract: A storage system is provided that includes storage controller logic that performs rapid data snapshots. The storage controller logic may provide block-level access to a storage volume. The storage controller logic may store all data blocks of the storage volume in a first solid state memory cache. The storage controller logic may form a snapshot of the storage volume in a second solid state memory cache. The first and second solid state memory caches are addressable with a processor. The storage system may complete the snapshot extremely quickly because the processor may copy from one memory location to another between the first and second solid state memory caches.
    Type: Application
    Filed: February 25, 2010
    Publication date: September 9, 2010
    Applicant: ECONNECTIX CORPORATION
    Inventors: Timothy Allen Stabrawa, Andrew S. Poling, John K. Overton
  • Patent number: 7769951
    Abstract: Apparatus and methods for storing user data for use in real-time communications (e.g., IM or VoIP) are provided. The apparatus comprises at least a first cache device (e.g., a cache server) and a second cache device for storing user data, wherein the user data stored with the first cache device is mirrored with the second cache device. The apparatus further comprising a server having logic for causing access to the user data (e.g., to respond to or process messages) from the first cache device, if accessible, and from the second cache device if the user data is not accessible form the first cache device. The apparatus may further include logic for causing user data to be restored to the first cache device from the second cache device if the first cache device loses user data (e.g., if the first cache device goes down).
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: August 3, 2010
    Assignee: Yahoo! Inc.
    Inventors: Ming Judy Lu, Rajanikanth Vemulapalli, Alan S. Li
  • Patent number: 7761680
    Abstract: Provided are a method, system, and article of manufacture for copying data from a first cluster to a second cluster to reassign storage areas from the first cluster to the second cluster. An operation is initiated to reassign storage areas from a first cluster to a second cluster, wherein the first cluster includes a first cache and a first storage unit and the second cluster includes a second cache and a second storage unit. Data in the first cache for the storage areas to reassign to the second cluster is copied to the second cache. Data in the first storage unit for storage areas remaining assigned to the first cluster is copied to the second storage unit.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kevin John Ash, Lokesh Mohan Gupta, Steven Robert Lowe, Alfred Emilio Sanchez, Kenneth Wayne Todd
  • Patent number: 7757051
    Abstract: A system and method for processing data (e.g., encoded audio data in an audio decoder). Various aspects of the present invention may comprise a first memory module comprising a first software module and a second software module. A signal-processing module may comprise a processor and local memory. A first data segment may be received, and the processor may identify the first software module for processing the first data segment. The first software module may be transferred to the local memory and executed by the processor to process the first data segment. A second data segment may be received, and the processor may identify the second software module for processing the second data segment. The second software module may be transferred to the local memory in memory space formerly occupied by the first software module. The processor may then utilize the second software module to process the second data segment.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: July 13, 2010
    Assignee: Broadcom Corporation
    Inventors: Sang Van Tran, Kenneth L. Welch
  • Patent number: 7757047
    Abstract: Maintaining a cache of indications of exclusively-owned coherence state for memory space units (e.g., cache line) allows reduction, if not elimination, of delay from missing store operations. In addition, the indications are maintained without corresponding data of the memory space unit, thus allowing representation of a large memory space with a relatively small missing store operation accelerator. With the missing store operation accelerator, a store operation, which misses in low-latency memory (e.g., L1 or L2 cache), proceeds as if the targeted memory space unit resides in the low-latency memory, if indicated in the missing store operation accelerator. When a store operation misses in low-latency memory and hits in the accelerator, a positive acknowledgement is transmitted to the writing processing unit allowing the store operation to proceed. An entry is allocated for the store operation, the store data is written into the allocated entry, and the target of the store operation is requested from memory.
    Type: Grant
    Filed: November 12, 2005
    Date of Patent: July 13, 2010
    Assignee: Oracle America, Inc.
    Inventors: Santosh G. Abraham, Lawrence A. Spracklen, Yuan C. Chou
  • Patent number: 7752281
    Abstract: A system for managing data in multiple data processing devices using common data paths. Embodiments of the invention comprise a first data processing system comprising a cacheable coherent memory space; and a second data processing system communicatively coupled to the first data processing system with the second data processing system comprising at least one bridge, wherein the bridge is operable to perform an uncacheable remote access to the cacheable coherent memory space of the first data processing system. In some embodiments, the access performed by the bridge comprises a data write to the memory of the first data processing system for incorporation into the cacheable coherent memory space of the first data system. In other embodiments, the access performed by the bridge comprises a data read from the cacheable coherent memory space of the first data system.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: July 6, 2010
    Assignee: Broadcom Corporation
    Inventor: Joseph B. Rowlands
  • Patent number: 7747788
    Abstract: Methods and apparatus for target-side SATA NCQ tag management are disclosed. In one aspect, an apparatus may include a status memory and a status manager circuit in communication with the status memory. The status memory may store status information for each of a plurality of commands that have been queued according to Native Command Queuing (NCQ). The status information may indicate whether or not each of the commands has been completed. The status manager circuit may generate and provide a status signal based on the status information stored in the status memory. Systems including such an apparatus and other components, such as hard disks, are also disclosed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventors: Naichih Chang, Victor Lau, Pak-lung Seto
  • Patent number: 7739485
    Abstract: A rack mounted computer system comprises a plurality of hot replaceable servers and power supplies that are mounted in chassis and assemblies which are coupled together and in which component specific data is stored in cache memory. The cache memory preferably is implemented on a communication module contained in each chassis/assembly. Some, or all, of the rack mounted components include ROM which contains component specific data. Such data includes one or more values specific to that component. The data may include any or all of the following: serial number, part name, manufacturing information, reorder information and physical dimensions of the associated component. By storing the component specific data in cache, less traffic is necessary on the rack's inter-chassis/assembly communication link(s) the chassis/assembly communication module snoops its cache and, if the data present in cache, provides the requested data from cache to the component.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: June 15, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Peter A. Hansen
  • Publication number: 20100146209
    Abstract: Methods, apparatus, computer programs and systems related to combining independent data caches are described. Various implementations can dynamically aggregate multiple level-one (L1) data caches from distinct processors together, change the degree of interleaving (e.g., how much consecutive data is mapped to each participating data cache before addresses go on to the next one) among the cache banks, and retain the ability to subsequently adjust the number of data caches participating as one coherent cache, i.e., the degree of interleaving, such as when the requirements of an application or process change.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 10, 2010
    Applicant: Intellectual Ventures Management, LLC
    Inventors: Doug Burger, Stephen W. Keckler, Changkyu Kim
  • Patent number: 7711721
    Abstract: An apparatus, system, and method are disclosed for suspending a data access request during serialization reinitialization of a file server. The apparatus includes a request recognition module, an availability module, and a suspension module. The request recognition module recognizes a request to be processed by a file server. The availability module determines if the file server is available. The suspension module suspends the data access request if the file server is not available due to serialization reinitialization. In one embodiment, the suspension module implements a hardware interrupt delay loop to suspend an interruptible data access request, such as an application request. In another embodiment, the suspension module queues a non-interruptible data access request and notifies the operating system, for example, that the non-interruptible request has been initiated.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gerard Maclean Dearing, William Stuart Edwards, Elmer Enrique Latorre, Thomas Alexander Mahon, Lyle LeRoy Merithew, Jr.
  • Patent number: 7702972
    Abstract: SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: April 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Timothy Carl Bronson, Garrett Drapala, Hieu Trong Huynh, Patrick James Meaney
  • Patent number: 7698506
    Abstract: A technique for partially offloading, from a main cache in a storage server, the storage of cache tags for data blocks in a victim cache of the storage server, is described. The technique includes storing, in the main cache, a first subset of the cache tag information for each of the data blocks, and storing, in a victim cache of the storage server, a second subset of the cache tag information for each of the data blocks. This technique avoids the need to store the second subset of the cache tag information in the main cache.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: April 13, 2010
    Assignee: Network Appliance, Inc.
    Inventors: Robert L. Fair, William P. McGovern, Thomas C. Holland, Jason Sylvain
  • Patent number: 7694075
    Abstract: A second cache (e.g., L2 cache) is enabled or disabled based at least in part on an utilization of a first cache (e.g., L1 cache). The utilization of the first cache may be interpreted as an estimation of the likely utilization of the second cache. The utilization may be estimated by monitoring, for example, the eviction rates of the first cache or other caches, by monitoring the proportion of ways of the first cache used by an instruction stream, or by monitoring the duration between certain instructions executed by the processor, such as the duration between suspend operations.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: April 6, 2010
    Inventor: Dan Gerrit Feekes, Jr.
  • Patent number: 7689761
    Abstract: A data storage system and a data storing method for the data storage system are provided. The data storage system includes a host unit, a storage unit, and a first input/output bus functioning as an interface between the host unit and the storage unit. The storage unit includes a non-volatile memory buffer unit and a flash memory unit. The non-volatile memory buffer unit includes a plurality of buffers arranged in parallel. The flash memory unit includes a plurality of data storage devices arranged in parallel to input and output data using a parallel method. In the method, a writing request is first classified into one of a plurality of grades according to a writing request frequency when there is a writing request and the writing requested data is stored in one of the non-volatile memory buffer unit and the flash memory unit according to the writing request frequency.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: March 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keunsoo Yim, Jeongjoon Yoo, Jungkeun Park
  • Patent number: 7644233
    Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Patent number: 7640396
    Abstract: A data-processing system and method are disclosed, which include a cached processor for processing data, and a plurality of memory components that communicate with the cached processor. The cached processor is separated from the memory components such that the cached processor provides support for the memory components, thereby providing a diffused memory architecture with diffused memory capabilities. The memory components can constitute, for example, memory devices such as diffused memory, matrix memory, R-Cell memory components, and the like, depending on design considerations.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: December 29, 2009
    Assignee: LSI Corporation
    Inventors: Claus Pribbernow, David Parker
  • Publication number: 20090313435
    Abstract: In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated with cache lines. The directory also includes logic to determine a time delay before the directory can send a concurrent snoop request. Other embodiments are described and claimed.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 17, 2009
    Inventors: Hariharan Thantry, Akhilesh Kumar, Seungjoon Park
  • Patent number: 7613886
    Abstract: Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory; facilitating the data transfer into the local memory; and producing a synchronization signal indicating that the data transfer into the local memory has been completed.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: November 3, 2009
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Takeshi Yamazaki
  • Patent number: 7606971
    Abstract: A storage control apparatus includes a plurality of temporary storage units that are managed in a redundant manner by data mirroring, and temporarily store data input from an outside source; a temporary-storage control unit that controls input and output of the data to the temporary storage units; and a mirroring control unit that controls the data mirroring between the temporary storage units, checks, when performing the data mirroring, validity of the data stored in a temporary storage unit of a mirroring source, and executes, when the validity of the data has been confirmed, the data mirroring.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: October 20, 2009
    Assignee: Fujitsu Limited
    Inventor: Kentarou Yuasa
  • Patent number: 7603488
    Abstract: Systems and methods for providing efficient memory allocation, reduced processor intervention and power consumption, and increased memory access bandwidth. One embodiment comprises a system including a plurality of memory units which are accessible in parallel, a dynamic memory unit configured to dynamically allocate and deallocate storage space in the memory units, and a plurality of direct memory access (DMA) engines configured to access the memory units in parallel through the memory management subsystem. The system may be implemented in the MAC engine of a device that communicates with other devices via a wireless communication link. This embodiment may store packets in FIFOs within the memory units as elements of linked list data structures that can be joined together without having to move the previously stored data. DMA engines access a context table to obtain DMA channel information that enables them to move data through appropriate DMA channels.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: October 13, 2009
    Assignee: Alereon, Inc.
    Inventors: Martin Gravenstein, Nirmalendu B. Patra, Andrew Probst, Dave Ohmann, Clair A. Hardesty
  • Publication number: 20090240888
    Abstract: Increasing security for a hand-held data processing device with communication functionality where such a device includes an access-ordered memory cache relating to communications carried out by the device. The hand-held data processing device has a locked state that is entered by the device receiving or initiating a trigger. On occurrence of the trigger to enter the locked state the memory cache is reordered so as to disrupt the access-ordering of the cache to obscure device traffic information and thus increase the security of the device in the locked state.
    Type: Application
    Filed: June 1, 2009
    Publication date: September 24, 2009
    Applicant: RESEARCH IN MOTION LIMITED
    Inventors: Michael K. Brown, Herbert A. Little, Michael S. Brown
  • Patent number: 7571242
    Abstract: IPv6 has been developed as an evolutionary advance of IPv4. Although IPv6 offers considerable improvement in certain areas such as addressing and routing it has eliminated the Internet header length field. As a result processing of packets to obtain the upper-layer header information in which extension headers have been added can result in slower processing rates. The present invention addresses this issue by caching information relating to the length of header option fields also known as extension headers. When a flow of IPv6 packets is received and if the packet header includes extension headers a review of the cached information can avoid processing steps and hence accelerate packet processing.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: August 4, 2009
    Assignee: Alcatel Lucent
    Inventor: David James Wilson
  • Patent number: 7565678
    Abstract: Methods and devices are disclosed for discouraging unauthorized modifications to set top boxes and gateways. Resource information is received that describing the number of disk drives and/or the capacity of each disk drive. A processor communicates with a database that stores configuration information. The processor compares the resource information to the configuration information. When the resource information differs from the configuration information, then the processor detects unauthorized modifications to the set top box.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: July 21, 2009
    Assignee: AT&T Intellectual Property, I, L.P.
    Inventors: Paul Thomas Watson, Scott R. Swix, James H. Gray
  • Patent number: 7562190
    Abstract: A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability of proximity interconnect, enhancements to the cache protocol to improve latency may be made despite resulting increased bandwidth consumption.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: July 14, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael J. Koster, Brian W. O'Krafka
  • Patent number: 7552282
    Abstract: Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is mapped to a first memory board and a second location is mapped to a second memory board. Data for a read operation is not replicated in cache. Other non-cache data that is critical and thus replicated includes metadata. Cache locations for data of read and write I/O operations are selected dynamically at the time the I/O operation is made from the same pool of cache locations.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: June 23, 2009
    Assignee: EMC Corporation
    Inventors: Michael Bermingham, Kendell A. Chilton, Robert DeCrescenzo, Mark J. Halstead, Haim Kopylovitz, Steven T. McClure, James M. McGillis, Ofer E. Michael, Brett D. Niver, John K. Walton
  • Publication number: 20090132765
    Abstract: A dual controller storage apparatus and a cache memory mirror method thereof are described. The storage apparatus includes a imaging environment module, a storage device, a first controller, and a second controller. The first controller has a virtual disk and a first cache memory. The second controller has a second cache memory. The present invent provides a imaging environment function to select the first or the second controller to serve an extranet according to the request of the extranet. If the imaging environment function selects the second controller, the data received from the extranet is written into the second cache memory. Communication between the second controller and the first controller is established, and the data of the second controller received from the extranet into the first cache memory and the virtual disk.
    Type: Application
    Filed: November 21, 2007
    Publication date: May 21, 2009
    Applicant: Inventec Corporation
    Inventors: Jian-Zhong Wang, Tom Chen, Win-Harn Liu
  • Patent number: 7536510
    Abstract: A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each of the plurality of data arrays is selected in response to the cache read request and selecting a first data of the received cache line data from the most recently used way of the cache. An execution of an instruction is stalled if data identified by the cache read request is not present in the cache line data from the most recently used way of the cache. A second data from a most recently used way of one of the plurality of data arrays other than the most recently used data array is selected as comprising data identified by the cache read request. The second data is provided for use during the execution of the instruction.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: May 19, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Stephen P. Thompson
  • Patent number: 7529889
    Abstract: A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing operations and a cache having a plurality of cache lines for storing data values for access by that at least one processing unit when performing those operations. The at least one processing unit provides a plurality of sources from which access requests are issued to the cache, and each access request, in addition to specifying an address, further includes a source identifier indicating the source of the access request. A storage element is provided for storing for each source an indication as to whether the last access request from that source resulted in a hit in the cache, and cache line identification logic determines, for each access request, whether that access request is seeking to access the same cache line as the last access request issued by that source.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: May 5, 2009
    Assignee: ARM Limited
    Inventors: Vladimir Vasekin, Stuart David Biles
  • Publication number: 20090077318
    Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
    Type: Application
    Filed: March 17, 2006
    Publication date: March 19, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takao Yamamoto, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko, Hazuki Okabayashi
  • Patent number: 7490200
    Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: February 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Leo James Clark, James Stephen Fields, Jr., Guy Lynn Guthrie, William John Starke
  • Publication number: 20080320223
    Abstract: A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in from outside to be written to the cache memory, a second buffer unit that retains a data piece to be currently written to the cache memory, among pieces of the data retained in the first buffer unit, and a write controlling unit that controls writing of the data piece retained in the second buffer unit to the cache memory.
    Type: Application
    Filed: August 26, 2008
    Publication date: December 25, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Masaki Ukai