Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: An operation processing apparatus includes: processor cores configured to perform an operation processing; cache memories each provided for the respective processor cores; and a controller configured to perform a coherency control between the cache memories, wherein, the controller, in the coherency control, in a case where one or more shared cache memories which share a target data block for a store request are present in the cache memories when the store request is received from a request cache memory included in the cache memories: controls one cache memory of the one or more shared cache memories such that the target data block is transferred to the request cache memory; receives an exclusive right acquisition response from another operation processing apparatus which manages a state of the target data block; and transmits the exclusive right acquisition response to the request cache memory.

Abstract: A distributed storage system includes multiple resource nodes each having associated storage media. The resource nodes are configured to operate a first protocol between the resource nodes that exchanges availability and performance information for storage elements in the associated storage media. The resource nodes also operate a second protocol that dynamically distributes and redistributes data between the different resource nodes based on the availability and performance information for the storage elements. Relative distances may be identified between the different resource nodes and the second protocol may weight the availability and performance information based on the relative distances. The second protocol also may identify types of unshared use, shared use, and concurrent use for different portions of the data and distribute the portions of the data to other resource nodes based on the identified types of use.

Abstract: In one embodiment, a computing system includes a cache and a cache manager. The cache manager is able to receive data, write the data to a first portion of the cache, write the data to a second portion of the cache, and delete the data from the second portion of the cache when the data in the first portion of the cache is flushed.

Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.

Abstract: The exemplary embodiments of the invention relates to fault tolerance of a cache memory which recovers an error occurred in the cache memory or reports an error. A cache memory may include a first layer cache configured to store data requested from a processor, together with a tag related to the data and parity check bits for detecting data error and tag error; a second layer cache configured to store data requested from the first layer cache, together with parity check bits and an error correction code(ECC) bit for detecting data error and tag error; and a fault tolerance unit configured to generate an error signal indicating whether the data error or tag error occurred in at least one of the first layer cache and the second layer cache is recoverable.

Abstract: A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory. Synchronization may be used to facilitate memory management operations, such as bulk operations used to change a large section of memory to read-only, operations to manage a free list of memory pages, and/or operations associated with terminating processes.

Abstract: A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory. Synchronization may be used to facilitate memory management operations, such as bulk operations used to change a large section of memory to read-only, operations to manage a free list of memory pages, and/or operations associated with terminating processes.

Abstract: A method for line speed interconnect processing. The method includes receiving initial inputs from an input communications path, performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs, and performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs. The method further includes transmitting the resulting outputs out of the second stage at line speed.

Abstract: A system and method for allocating shared memory of differing properties to shared data objects and a hybrid stack data structure. In one embodiment, the system includes: (1) a hybrid stack creator configured to create, in the shared memory, a hybrid stack data structure having a lower portion having a more favorable property and a higher portion having a less favorable property and (2) a data object allocator associated with the hybrid stack creator and configured to allocate storage for shared data object in the lower portion if the lower portion has a sufficient remaining capacity to contain the shared data object and alternatively allocate storage for the shared data object in the higher portion if the lower portion has an insufficient remaining capacity to contain the shared data object.

Abstract: An apparatus, method, and program product for optimizing a multiprocessor computing system by sampling memory reference latencies and adjusting components of the system in response thereto. During execution of processes the computing system, memory reference sampling of memory locations from shared memory of the computing system referenced in the executing processes is performed. Each sampled memory reference collected from sampling is associated with a latency and a physical memory location in the shared memory.

Abstract: In one embodiment, a computer-implemented method includes detecting a cache miss for a cache line. A resource is reserved on each of one or more remote computing nodes, responsive to the cache miss. A request for a state of the cache line on the one or more remote computing nodes is broadcast to the one or more remote computing nodes, responsive to the cache miss. A resource credit is received from a first remote computing node of the one or more remote computing nodes, responsive to the request. The resource credit indicates that the first remote computing node will not participate in completing the request. The resource on the first remote computing node is released, responsive to receiving the resource credit from the first remote computing node.

Abstract: Embodiments are disclosed for caching multimedia content. An example in-vehicle computing system that adaptively caches multimedia data, the in-vehicle system including a memory, a position sensor, a receiver, and a processor. The position sensor provides a position signal indicative of a present location of the system. The receiver wirelessly receives multimedia data from a remote multimedia data source. The processor stores the received multimedia data in the memory, transfers multimedia data in the memory to a queue for playback when an amount of multimedia data saved in the memory is at least a first threshold value, and adjusts a size of the memory when a wireless communication channel is not available between the system and a remote multimedia data source.

Abstract: According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

Abstract: Apparatuses, systems, and methods are disclosed for managing cache pools. A storage request module monitors storage requests received by a cache. The storage requests include read requests and write requests. A read pool module adjusts a size of a read pool of the cache to increase a read hit rate of the storage requests. A dirty write pool module adjusts a size of a dirty write pool of the cache to increase a dirty write hit rate of the storage requests.

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract: In one embodiment, a computing system includes a cache including one or more memories and a cache manager. The cache manager is able to determine an amount of accessible data for a portion of the cache associated with the cache manager; compare the amount of accessible data to a threshold value; determine, for one or more clients associated with the cache manager, an amount of releasable data if the amount of accessible data exceeds the threshold value; communicate, to one or more clients associated with the cache manager, the amount of releasable data for the client; receive from one or more clients associated with the cache manager information associated with data released by the one or more clients; and determine an amount of data released by the one or more clients associated with the cache manager.

Abstract: In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write data to a first portion of the cache, write the data to the first portion of the cache, update a first map corresponding to the first portion of the cache, receive a request to read data from the first portion of the cache, read from a storage communicatively linked to the computing system data according to the first map, and update a second map corresponding to the first portion of the cache. The cache manager may also be able to write data to the storage according to the first map.

Abstract: In one embodiment, a computing system includes a cache having one or more memories, a cache journal operable to store data associated with one or more portions of the cache, and a configuration manager operable to access the cache and the cache journal. The configuration manager is operable to determine whether the cache journal includes data associated with a first portion of the cache, and to create, in the cache journal, data associated with the first portion of the cache if the cache journal does not yet comprise data associated with the first portion of the cache. The configuration manager is also operable to determine whether the first portion of the cache is valid for use, and to communicate with a memory manager associated with the first portion of the cache regarding whether the first portion of the cache is valid for use.

Abstract: In one embodiment, a computer system includes a cache having one or more memories and a metadata service. The metadata service is able to receive requests for data stored in the cache from a first client and from a second client. The metadata service is further able to determine whether the performance of the cache would be improved by relocating the data stored in the cache. The metadata service is further operable to relocate the data stored in the cache when such relocation would improve the performance of the cache.

Abstract: A method and an apparatus for determining a to-be-migrated task based on cache awareness in a computing system having multiple processor cores is disclosed. In the method, the computing system determines a source processor core and a destination processor core according to a load of each processor core. Through respectively monitoring the number of cache misses of each task and the number of executed instructions of each task in the source processor core and the destination processor core, the computing system obtain an average cache miss per kilo instructions of the source processor core and an average cache miss per kilo instructions of the destination processor core. Then, the computing system determines, according to the obtained average cache miss per kilo instructions of the source processor core and the destination processor core, a task to be migrated from the source processor core to the destination processor core.

Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

Abstract: Methods and systems for updating memory content in a mobile client are disclosed. For example, an exemplary method includes maintaining a list of first attributes relating to a set of first messages on the mobile client, wherein each of the set of first messages resides on the mobile client, maintaining a list of second attributes relating to set of second messages on the mobile client, wherein each of the set of second messages does not reside on the mobile client, identifying target attributes associated with a message request by the mobile client, selecting by the mobile client a selected message from one of the set of first messages and the set of second messages by applying a set of selection rules to the target attributes, and in the situation where a second message is selected, requesting the selected second message from a remote server using a wireless link.

Abstract: In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write data to a first portion of the cache, write the data to the first portion of the cache, update a first map corresponding to the first portion of the cache, receive a request to read data from the first portion of the cache, read from a storage communicatively linked to the computing system data according to the first map, and update a second map corresponding to the first portion of the cache. The cache manager may also be able to write data to the storage according to the first map.

Abstract: In one embodiment, a computer system includes a cache having one or more memories and a metadata service. The metadata service is able to receive requests for data stored in the cache from a first client and from a second client. The metadata service is further able to determine whether the performance of the cache would be improved by relocating the data stored in the cache. The metadata service is further operable to relocate the data stored in the cache when such relocation would improve the performance of the cache.

Abstract: A method for upgrading storage processors in a storage system includes a first storage processor performing IO requests on a first one or more logical units, and a second storage processor performing IO requests on a second one or more logical units of the plurality of logical units. The method includes causing the first storage processor to stop performing the IO requests on the first one or more logical units and the second storage processor to perform the IO requests on the first one or more logical units. The method includes causing the second storage processor to stop performing the IO requests on the first one or more logical units of the plurality of logical units and a third storage processor to perform the IO requests on the first one or more logical units.

Abstract: System and methods for cache coherence in a multi-core processing environment having a local/shared cache hierarchy. The system includes multiple processor cores, a main memory, and a local cache memory associated with each core for storing cache lines accessible only by the associated core. Cache lines are classified as either private or shared. A shared cache memory is coupled to the local cache memories and main memory for storing cache lines. The cores follow a write-back to the local memory for private cache lines, and a write-through to the shared memory for shared cache lines. Shared cache lines in local cache memory enter a transient dirty state when written by the core. Shared cache lines transition from a transient dirty to a valid state with a self-initiated write-through to the shared memory. The write-through to shared memory can include only data that was modified in the transient dirty state.

Abstract: User access for a requested resource is controlled through a computer network within a protected data environment of a computer environment. An exception list comprising an Identifier stored within the protected data environment for granting user access of an unauthorized user is defined. At least one allowed access property relation for user access is defined when accessed by the unauthorized user. An Identifier of a user access request of the unauthorized user is checked in the exception list. A One-Time Identifier is created. The One-Time Identifier is assigned according to the allowed property relation. The requested resource is delivered to the unauthorized user by using the assigned One-Time Identifier.

Abstract: User access is controlled through a computer network within a protected data environment of a computer environment. An exception list comprising an Identifier stored within the protected data environment for granting user access of an unauthorized user is defined. At least one allowed access property relation for user access is defined when accessed by the unauthorized user. An Identifier of a user access request of the unauthorized user is checked in the exception list. A One-Time Identifier is created. The One-Time Identifier is assigned to the electronic data resource according to the allowed property relation. The requested resource is delivered to the unauthorized user by using the assigned One-Time Identifier.

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract: In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.

Abstract: A computer processing system with a hierarchical memory system that associates a number of valid bits for each cache line of the hierarchical memory system. The valid bits are provided for each cache line stored in a respective cache and make explicit which bytes are semantically defined and which are not for the associated given cache line. Memory requests to the cache(s) of the hierarchical memory system can include an address specifying a requested cache line as well as a mask that includes a number of bits each corresponding to a different byte of the requested cache line. The values of the bits of the byte mask indicate which bytes of the requested cache line are to be returned from the hierarchical memory system. The memory request is processed by the top level cache of the hierarchical memory system, looking for one or more valid bytes of the requested cache line corresponding to the target address of the memory request.

Abstract: A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application. The object is stored in a cache region of the memory cache based on an identification that the object has no potential for storage in a shared memory cache and a determination that the cache region is associated with a storage policy that specifies that objects to be stored in the cache region are to be stored in a local memory cache and that a garbage collector is not to remove objects stored in the cache region from the local memory cache.

Abstract: A multiple processor system is disclosed. The processor system includes a first cluster including a first plurality of processors is associated with a first cluster cache, a second cluster including a second plurality of processors associated with a second cluster cache, and a cluster communication network between the first cluster and the second cluster for sharing data between the first cluster and the second cluster. The first cluster includes a first unshared connection to the cluster communication network and the second cluster includes a second unshared connection to the cluster communication network.

Abstract: A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is coupled to the central processing unit. A coherent interconnection may exist between the internal cache and both the memory controller and the closely coupled peripheral, wherein the coherent interconnection is a bus.

Abstract: In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

Abstract: A method of virtualizing an application to execute on a plurality of operating systems without installation. The method includes creating an input configuration file for each operating system. The templates each include a collection of configurations that were made by the application during installation on a computing device executing the operating system. The templates are combined into a single application template having a layer including the collection of configurations for each operating system. The collection of configurations includes files and registry entries. The collections also identifies and configures environmental variables, systems, and the like. Files in the collection of configurations and references to those files may be replaced with references to files stored on installation media. The application template is used to build an executable of the virtualized application.

Abstract: Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.

Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Abstract: The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a private cache to store data, and a spill table to record pointers for data evicted from the private cache to a remote host, wherein the remote host and the respective tile are provided in the same virtual domain. The spill tables may allow for faster retrieval of previously evicted data because the home registry does not need to be referenced if requested data is listed in the spill table. Therefore, embodiments of the present invention may provide a distance-aware cache collaboration architecture without incurring extraneous overhead expenses.

Abstract: A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

Abstract: Embodiments of the invention address deficiencies of the art in respect to cache coherency management and provide a novel and non-obvious method, system and apparatus for silent invalid state transition handling in an SMP environment. In one embodiment of the invention, a cache coherency method can be provided. The cache coherency method can include identifying an invalid state transition for a cache line in a local node, evicting a corresponding cache directory entry for the cache line, forwarding an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line, and relinquishing ownership of the cache line to the home node.

Abstract: A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data.

Abstract: A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.

Abstract: Methods, parallel computers, and computer program products for analyzing update conditions for shared variable directory (SVD) information in a parallel computer are provided. Embodiments include a runtime optimizer receiving a compare-and-swap operation header. The compare-and-swap operation header includes an SVD key, a first SVD address, and an updated first SVD address. The first SVD address is associated with the SVD key in a first SVD associated with a first task. Embodiments also include the runtime optimizer retrieving from a remote address cache associated with the second task, a second SVD address indicating a location within a memory partition associated with the first SVD in response to receiving the compare-and-swap operation header. Embodiments also include the runtime optimizer determining whether the second SVD address matches the first SVD address and transmitting a result indicating whether the second SVD address matches the first SVD address.

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Abstract: Methods, parallel computers, and computer program products for analyzing update conditions for shared variable directory (SVD) information in a parallel computer are provided. Embodiments include a runtime optimizer receiving a compare-and-swap operation header. The compare-and-swap operation header includes an SVD key, a first SVD address, and an updated first SVD address. The first SVD address is associated with the SVD key in a first SVD associated with a first task. Embodiments also include the runtime optimizer retrieving from a remote address cache associated with the second task, a second SVD address indicating a location within a memory partition associated with the first SVD in response to receiving the compare-and-swap operation header. Embodiments also include the runtime optimizer determining whether the second SVD address matches the first SVD address and transmitting a result indicating whether the second SVD address matches the first SVD address.

Abstract: A system, method, and computer program product are provided for conditionally sending a request for data to a home node. In operation, a first request for data is sent to a first cache of a node. Additionally, if the data does not exist in the first cache, a second request for the data is sent to a second cache of the node. Furthermore, a third request for the data is conditionally sent to a home node.