Abstract: A system and method are provided for adaptively configuring L2 cache memory usage in a system of microprocessors. A system-on-chip (SoC) is provided with a plurality of n selectively enabled processor cores and a plurality of n L2 cache memories. The method associates each L2 cache with a corresponding processor core, and shares the n L2 caches between enabled processor cores. More explicitly, associating each L2 cache with the corresponding processor core means connecting each processor core to its L2 cache using an L2 data/address bus. Sharing the n L2 caches with enabled processors means connecting each processor core to each L2 cache via a data/address bus mesh with dedicated point-to-point connections.

Abstract: A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.

Abstract: A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.

Abstract: An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second SMP computer including at least third and fourth processing units and second and third system memory pools. The second system memory pool is a restricted access memory pool inaccessible to the fourth processing unit and accessible to at least the second and third processing units, and the third system memory pool is accessible to both the third and fourth processing units. An interconnect couples the second processing unit in the first SMP computer for load-store coherent, ordered access to the second system memory pool in the second SMP computer, such that the second processing unit in the first SMP computer and the second system memory pool in the second SMP computer form a synthetic third SMP computer.

Abstract: Techniques described herein generally include methods and systems related to cooperatively caching data in a chip multiprocessor. Cooperatively caching of data in the chip multiprocessor is managed based on an eviction rate of data blocks from private caches associated with each individual processor core in the chip multiprocessor. The eviction rate of data blocks from each private cache in the cooperative caching system is monitored and used to determine an aggregate eviction rate for all private caches. When the aggregate eviction rate exceeds a predetermined value, for example the threshold beyond which network flooding can occur, the cooperative caching system for the chip multiprocessor is disabled, thereby avoiding network flooding of the chip multiprocessor.

Abstract: A processor interface (24) receives a flush request from a processor (700) and performs a snoop operation to determine whether the data is maintained in a one of the local processors (700) and whether the data has been modified. If the data is maintained locally and it has been modified, an identified local processor (700) receives the flush request from the processor interface (24) and initiates a writeback to a memory directory interface unit (24). If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22). Memory directory interface unit (22) determines which remote processors within the system (10) have a copy of the data and forwards the flush request only to those identified processors.

Abstract: Techniques for data pattern analysis using deterministic finite automaton are described herein. In one embodiment, a number of transitions from a current node to one or more subsequent nodes representing one or more sequences of data patterns is determined, where each of the current node and subsequent nodes is associated with a deterministic finite automaton (DFA) state. A data structure is dynamically allocated for each of the subsequent nodes for storing information associated with each of the subsequent nodes, where data structures for the subsequent nodes are allocated in an array maintained by a data structure corresponding to the current node if the number of transitions is greater than a predetermined threshold. Other methods and apparatuses are also described.

Abstract: An apparatus for memory access prediction which includes a plurality of processors, a plurality of memory caches associated with the processors, a plurality of saturation counters associated with the processors, each of the saturation counters having an indicator bit, and a physical memory shared with the processors, saturation counters and memory caches. Upon a cache miss for a data item, a cache snoop and access to physical memory are initiated in parallel for the data item if the indicator bit is a first predetermined bit (one (1) or zero (0)) whereas a cache snoop is initiated if the most significant bit is a second predetermined bit (zero (0) or one (1)).

Abstract: The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a private cache to store data, and a spill table to record pointers for data evicted from the private cache to a remote host, wherein the remote host and the respective tile are provided in the same virtual domain. The spill tables may allow for faster retrieval of previously evicted data because the home registry does not need to be referenced if requested data is listed in the spill table. Therefore, embodiments of the present invention may provide a distance-aware cache collaboration architecture without incurring extraneous overhead expenses.

Abstract: A data cache method, device, and system in a multi-node system are provided. The method includes: dividing a cache area of a cache medium into multiple sub-areas, where each sub-area is corresponding to a node in the system; dividing each of the sub-areas into a thread cache area and a global cache area; when a process reads a file, detecting a read frequency of the file; when the read frequency of the file is greater than a first threshold and the size of the file does not exceed a second threshold, caching the file in the thread cache area; or when the read frequency of the file is greater than the first threshold and the size of the file exceeds the second threshold, caching the file in the global cache area. Thus overheads of remote access of a system are reduced, and I/O performance of the system is improved.

Abstract: In operation, a first request for data is sent to a cache of a first node. Additionally, it is determined whether the first request can be satisfied within the first node, where the determining includes at least one of determining a type of the first request and determining a state of the data in the cache. Furthermore, a second request for the data is conditionally sent to a second node, based on the determination.

Abstract: A system, method, and computer program product are provided for conditionally sending a request for data to a home node. In operation, a first request for data is sent to a first cache of a node. Additionally, if the data does not exist in the first cache, a second request for the data is sent to a second cache of the node.

Abstract: A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

Abstract: Managing cache memories in a computing system comprising multiple cores includes: assigning home cache locations for portions of data stored among caches in a group of caches of respective cores; accessing a first one of the portions of the cached data by sending an access request to a first home core of that first one of the portions of cached data; tracking a history of access for the first one of the portions of cached data; determining whether the tracked history of access for the first one of the portions of cached data exceeds or meets a predetermined condition, and re-assigning a home cache location of the first one of the portions of cached data from the first home core to a second, different home core when the predetermined condition is met or exceeded.

Abstract: A method for providing context classification may include causing selection of a single core in a multi-core processor as a context core in a user terminal, configuring cache memory associated with the context core to enable the context core to process context information for the user terminal, and causing execution of prediction and control functions related to user interface interactions based on the context information processed at the context core. Corresponding apparatuses are also provided.

Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Abstract: A system and method are provided for sharing data between a network including one or more network nodes. The network includes a number of individual network nodes and a home network node communicating with one another. The individual network nodes and the home network node include a plurality of processors and memory caches. The memory caches consist of private caches corresponding to individual processors, as well as shared caches which are shared among the plurality of processors of an individual node and accessible by the processors of the other network nodes. Each network node is capable of executing a hierarchy of data requests that originate in the private caches of an individual local network node. If no cache hits occur within the local network node, a conditional request is sent to the home network node to request data through the shared caches of the other network nodes.

Abstract: An approach for automatically sharing a tape drive in a heterogeneous computing environment that includes a first computer and second computer is presented. The first computer receives a message that includes a shared tape drive identifier, a source port identifier of the second computer, and a reservation status change for the tape drive. Based on the tape drive identifier, the first computer determines that the tape drive is connected to the first computer. The source port identifier is determined to not identify any host bus adapter installed in the first computer. In response to the first computer determining that the reservation status change indicates a reservation or a release of the tape drive for the second computer, the first computer sets the tape drive offline or online, respectively, in an application executing in the first computer.

Abstract: According to one embodiment, a data transfer device is provided. The data transfer device is configured to transfer data between a plurality of data transceivers and at least one memory having a first memory area. When one of the data transceivers has acquired an exclusive access right to the first memory area of the memory, the data transfer device stores address information corresponding to the first memory area.

Abstract: A multi-core processor system includes a first processor that among cores of the multi-core processor, identifies other cores having a cache miss-hit rate lower than that of a given core storing a specific program in a cache, based on a task information volume of each core; a control circuit that migrates the specific program from the cache of the given core to a cache of the identified core; and a second processor that, after the specific program is migrated to the cache of the identified core, sets as a write-inhibit area, an area that is of the cache of the identified core and to which the specific program is stored.

Abstract: An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.

Abstract: A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.

Abstract: An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second SMP computer including at least third and fourth processing units and second and third system memory pools. The second system memory pool is a restricted access memory pool inaccessible to the fourth processing unit and accessible to at least the second and third processing units, and the third system memory pool is accessible to both the third and fourth processing units. An interconnect couples the second processing unit in the first SMP computer for load-store coherent, ordered access to the second system memory pool in the second SMP computer, such that the second processing unit in the first SMP computer and the second system memory pool in the second SMP computer form a synthetic third SMP computer.

Abstract: In a multiprocessor system level 2 caches are positioned on the memory side of a routing crossbar rather than on the processor side of the routing crossbar. This configuration permits the processors to store messages directly into each other's caches rather than into system memory or their own coherent caches. Therefore, inter-processor communication latency is reduced.

Abstract: A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit.

Abstract: The present invention provides a secure buffer for use in data storage and encryption processing. Blocks or packets of data are passed to a secure buffer within a processor. The processor may be one of many coprocessors, and the secure buffer may be inaccessible to some or all of the coprocessors. Data may be partially or fully encrypted and stored within the secure buffer. Encryption may occur before or after storage in the buffer, or it may take place within the buffer itself. Optionally, the encrypted data may be sent to and retrieved from a shared memory that is accessible by other coprocessors.

Abstract: Disclosed is a network-on-chip system including an active memory processor for processing increased communication latency by multiple processors and memories. The network-on-chip system includes a plurality of processing elements that request to perform an active memory operation for a predetermined operation from a shared memory to reduce access latency of the shared memory, and an active memory processor connected to the processing elements through a network, storing codes for processing custom transaction in request to the active memory operation, performing an operation addresses or data stored in a shared cache memory or the shared memory based on the codes and transmitting the performed operation result to the processing elements.

Abstract: According to some implementations methods, apparatus and systems are provided involving the use of processors having at least one core with a security component, the security component adapted to read and verify data within data blocks stored in a L1 instruction cache memory and to allow the execution of data block instructions in the core only upon the instructions being verified by the use of a cryptographic algorithm.

Abstract: A method and system for automatically sharing a tape drive in a heterogeneous computing environment that includes a first computer and second computer. The first computer receives a message that includes a shared tape drive identifier, a source port identifier of the second computer, and a reservation status change for the tape drive. Based on the tape drive identifier, the first computer determines that the tape drive is connected to the first computer. The source port identifier is determined to not identify any host bus adapter installed in the first computer. In response to the first computer determining that the reservation status change indicates a reservation or a release of the tape drive for the second computer, the first computer sets the tape drive offline or online, respectively, in an application executing in the first computer.

Abstract: The present application is a protocol for maintaining cache coherency in a CMP. The CMP design contains multiple processor cores with each core having it own private cache. In addition, the CMP has a single on-ship shared cache. The processor cores and the shared cache may be connected together with a synchronous, unbuffered bidirectional ring interconnect. In the present protocol, a single INVALIDATEANDACKNOWLEDGE message is sent on the ring to invalidate a particular core and acknowledge a particular core.

Abstract: A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. A central processing unit is provided with the transactional memory hardware. Code backpatching can be facilitated by providing transactional memory hardware that supports a facility to maintain private memory state and an atomic commit feature. Changes made to certain code are stored in the private state facility. Backpatching changes are enacted by attempting to commit all the changes to memory at once using the atomic commit feature. An efficient call return stack can be provided by using transactional memory hardware. A call return cache stored in the private state facility captures a host address to return to after execution of a guest function completes. A direct-lookup hardware-based hash table is used for the call return cache.

Abstract: A directory of a private cache hierarchy is provided to maintain coherency between data stored in the cache hierarchy, where the directory is to enable concurrent cache-to-cache transfer of data to two private caches from another private cache. This directory can be implemented in a system having a multi-core processor. Other embodiments are described.

Abstract: A system and method determines when the entries of a reply cache, organized into microcaches each of which is allocated to a client connection, may be retired or released, thereby freeing up memory structures. A plurality of connection statistics are defined and tracked for each microcache and for the entries of the microcache. The connection statistics indicate the value of the microcache and its entries to the client. The connection statistics include a measure of the time since the last idempotent or non-idempotent request (TOLR) was received, and a count of the number of idempotent requests that have been received since the last non-idempotent request (RISLR). A microcache with a TOLR time and a RISLR count that exceed respective thresholds may be expired and removed from the reply cache.

Abstract: A first portion of an identifier can be used to assign the identifier to a slot in a first directory. The identifier can identify a cache unit in a cache. It can be determined whether assignment of the identifier to the slot in the first directory will result in the identifier and one or more other identifiers being assigned to the same slot in the first directory. If so, then the technique can include (1) using a second portion of the identifier to assign the identifier to a slot in a second directory; and (2) assigning the one or more other identifiers to one or more slots in the second directory. In addition, it can be determined whether a directory in a cache lookup data structure includes more than one pointer. If not, then a parent pointer that points to the subject directory can be removed.

Abstract: A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.

Abstract: One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed.

Abstract: A method and apparatus for dynamically modifying routing information in an interconnect architecture without quiescence is herein described. Each agent/node holds routing information regarding target agents/nodes in an interconnect architecture, which may include routing preferences. When a node is to be hot removed, it generates port disable messages to neighbors. The neighbors disable a port the disable message is received on and generates a completion message back to the not to be removed. The node to be removed continues to route messages until it receives a completion; at which time it disables a corresponding node. When all nodes are disabled the device may be removed. Other nodes in the interconnect architecture learn of an agent removal through use of return cycles when messages reach dead ends during attempted routing of cycles. Furthermore, hot addition of a node includes broadcasting of an enable message to enable nodes for routing to the added node.

Abstract: A coherency algorithm for a multi processor environment to run on a single processor model is verified by: generating a reference model reflecting a private cache hierarchy of a single processor within the multi processor environment, stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side, and augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, which are set based on interface events. Multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. Further, a single processor model and a computer program product can be employed to execute the method.

Abstract: In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent.

Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units.

Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

Abstract: Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache. Each director may obtain a cache slot from a private stack of nondata cache slots in addition to accessing a shared cache used by all directors.

Abstract: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.

Abstract: Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID allocation logic coupled to and operating in parallel to the decoder to select a transaction ID (TID) for the transaction based on the first node ID, a packet creation unit to create a packet that includes the transaction, the first node ID, the TID and a second node ID corresponding to the requestor.

Abstract: Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.

Abstract: A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other nodes through an expansion port (or scalability port). The method also starts an access of a memory in response to the request for data and snoops a processor cache of each processor in each node. The method accordingly identifies the location of the data in either the processor cache or memory in the node having the processor issuing the request or in a processor cache or memory of another node.

Abstract: A method to associate a storage policy with a cache region is disclosed. In this method, a cache region associated with an application is created. The application runs on virtual machines, and where a first virtual machine has a local memory cache that is private to the first virtual machine. The first virtual machine additionally has a shared memory cache that is shared by the first virtual machine and a second virtual machine. Additionally, the cache region is associated with a storage policy. Here, the storage policy specifies that a first copy of an object to be stored in the cache region is to be stored in the local memory cache and that a second copy of the object to be stored in the cache region is to be stored in the shared memory cache.

Abstract: Techniques are provided for performing transaction-aware caching of metadata in an electronic file system. A mechanism is described for providing transaction-aware caching that uses a cache hierarchy, where the cache hierarchy includes uncommitted caches associated with sessions in an application and a committed cache that is shared among the sessions in that application. Techniques are described for caching document metadata, access control metadata and folder path metadata. Also described is a technique for using negative cache entries to avoid unnecessary communications with a server when applications repeatedly request non-existent data.