Abstract: Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.

Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.

Abstract: A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.

Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

Abstract: An apparatus and method provide persistent data during a user session on a networked computer system. A global data cache is divided into three sections: trusted, protected, and unprotected. An authorization mechanism stores and retrieves authorization data from the trusted section of the global data store. A common session manager stores and retrieves data from the protected and unprotected sections of the global data cache. Using the authorization mechanism, software applications may verify that a user is authorized without prompting the user for authorization information. Using the common session manager, software applications may store and retrieve data to and from the global data store, allowing the sharing of data during a user session. After the user session terminates, the data in the global data cache corresponding to the user session is invalidated.

Abstract: In a method for transmitting data from a first node to a second node through an interlinking network including data transmission equipments: the data is transmitted from the first node to one of the data transmission equipments together with a first request for storage of the data in the one of the data transmission equipments; the data is stored in a storage unit provided in the one of the data transmission equipments in response to the first request; a second request for the data is transmitted from the second node to the one of the data transmission equipments; the data is read out from the storage unit in response to the second request; and the data is transmitted from the one of the data transmission equipments to the second node.

Abstract: A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program instructions read from the cache responsive to the address multiplexer.

Abstract: In one embodiment, the present invention includes a method for performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a data cache, and synchronizing the page in the data cache and an instruction cache if the page implicates instruction information, otherwise not synchronizing the page. In this manner, synchronizations may be performed on demand. Other embodiments are described and claimed.

Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.

Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

Abstract: A method for detecting and repairing cloud splits in a distributed system such as a peer-to-peer (P2P) system is presented. Nodes in a cloud maintain a multilevel cache of entries for a subset of nodes in the cloud. The multilevel cache is built on a circular number space, where each node in the cloud is assigned a unique identifier (ID). Nodes are recorded in levels of the cache according to the distance from the host node. The size of the cloud is estimated using the cache, and cloud-split tests are performed with a frequency inversely proportional to the size of the cloud. Cloud splits are initially detected by polling a seed server in the cloud for a node N having an ID equal to the host ID+1. The request is redirected to another node in the cloud, and a best match for N is resolved. If the best-match is closer to the host than any node in the host's cache, a cloud split is presumed.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: Briefly, in accordance with an embodiment of the invention, a method to store information is provided, wherein the method includes generating a storage parameter to store information, wherein the storage parameter indicates use of the information by a software process and transferring the information to one of at least two memory devices based at least in part on the storage parameter and on a characteristic of the two memory devices.

Abstract: Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.

Abstract: A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache, a tag parity packet and a load instruction are sent from the primary cache to the secondary cache. In response to the tag parity packet, each tag entry in the secondary cache that is associated with the parity error is invalidated. Upon receiving an acknowledgment of receipt of the tag parity packet, the primary cache functions to invalidate each tag entry in the primary cache that is associated with the parity error. Then, the secondary cache communicates data requested in the load instruction to the primary cache.

Abstract: According to one embodiment, the present invention comprises a command cache in which a command which is not compressed or encoded is written from the outside, a data cache in which a compressed or encoded command is written, a processor which executes processing based on a command written in the command cache, and decompresses or decodes a command written in the data cache, and a special cache in which a command decompressed or decoded by the processor is written and which subjects the command to processing by the processor.

Abstract: Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one embodiment, the method, apparatus and computer program product include identifying an add/remove area of a linked list and a static area of the linked list. Elements may only be added or removed from the linked list in the add/remove area or by a garbage collector that performs garbage collection only on elements in the static area of the linked list. The garbage collector identifies an element after the last element in the add/remove area and performs garbage collection beginning with that element and moving through the static area. In an alternative embodiment, a “next element” pointer in a previous list element is set to point to the element being deleted's “next element” pointer. Any global references to the element being deleted must be modified.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: A data memory cache unit is provided which is capable of heightening the speed of memory access. The cache unit 117 executes reading and writing of data in a 16-byte width line unit in a main memory unit 131, executes reading and writing of data in an MPU 113 in the unit of a four-byte width small area included in each line. When the MPU 113 executes a push instruction, if a cache miss takes place on a line which includes a small area that holds data which should be read out to the MPU 113 (NO at S1), then the cache unit 117 opens the line (S301). If a small area into which the data sent from the MPU 113 should be written is adjacent to a line boundary on the side where an address is larger or on the side where write-in is earlier executed (YES at S56), then the cache unit 117 does not execute a refill, and if this small area is not adjacent to the line boundary (NO at S56), then it executes a refill (S21).

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface logic is configured to receive data packets and selectively distribute the data packet to either the user mode or kernel mode logic. The interface logic includes “virtual” bridge logic and “virtual” miniport logic. The bridge logic determines if a received data packet is a user mode or kernel mode data packet. If it is a kernel mode data packet, then the bridge logic provides the data packet to the kernel mode logic. If it is a user mode data packet, then the bridge logic stores the data packet in memory for subsequent use by the user mode logic.

Abstract: According to some embodiments, routing information for an information packet is determined in accordance with a destination address and a device address.

Abstract: An in-order single-issue microprocessor detects data cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss. The data cache has pipeline stages that parallel portions of the main microprocessor pipeline. Replay buffers are employed to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache pipeline stages are restored upon detection that the stall will terminate. The bus requests for the missing data are issued only if the stalled instruction does not access a memory-mapped I/O region of the memory address space.

Abstract: Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.

Abstract: Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing access information to access at least one array stored in the plurality of memory cells. According to another aspect, an electronic system is provided that includes a main memory, a dynamic array cache memory device, a general cache memory device, and a processor. The dynamic array cache memory device is coupled to the main memory and adapted for caching array data. The general cache memory device is coupled to the main memory and is adapted for caching regular data. The processor is coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.

Abstract: A method and apparatus to decrease the amount of time it takes to obtain friendly names of Bluetooth devices is presented. A name server caches friendly names for devices that it has acquired from other devices or from other name servers. The name server is any device that caches friendly names of Bluetooth devices and that makes the friendly names available to other devices. A requesting device determines if a name server has responded to an inquiry command. If a name server has responded, the device gets the friendly names the name server has cached and requests the friendly names of devices that responded that have not been cached by the name server. Identification of a name server is accomplished by embedding a marker in the friendly name field after the null character to indicate that the device is a name server.

Abstract: In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering device and method parse a snoop request issued by one of the plurality of snooping masters and return an Immediate Response if parsing indicates the requested data cannot possibly be contained in a responding snooping master. If parsing indicates otherwise the at least one plurality of snoop masters searches its resources and returns the requested data if marked updated.

Abstract: A processor having a cache memory structure which improves an operation speed of the processor and a method of managing cache memory of the processor are provided. The cache memory is divided into a cache memory for normal programs which stores instructions required for running normal programs and a cache memory for exception programs. An instruction register fetches and stores instructions from one of the cache memories according to the type of program currently running. The method includes dividing the cache memory into a cache memory for normal programs and a cache memory for exception programs, storing instructions and/or data for running the normal and exception programs in their respective cache memories, determining a type of a currently running program, fetching instructions from either cache memory according to the type of program currently running, and inputting the fetched instructions to the instruction register.

Abstract: Power conservation may be achieved in a front end system by disabling a segment builder unless program flow indicates a sufficient likelihood of segment reuse. Power normally spent in collecting decoded instructions, detecting segment beginning and end conditions and storing instruction segments is conserved by disabling those circuits that perform these functions. An access filter may maintain a running count of the number of times instructions are read from an instruction cache and may enable the segment construction and storage circuits if the running count meets or exceeds a predetermined threshold.

Abstract: It is an object to obtain a semiconductor storage having a 1—chip structure which can be simultaneously accessed to memory cells present in different memory cell arrays. A 1-port memory cell array (11) provided with a word line (WL1) for a first port in common and a 2-port memory cell array (12) are provided together over one chip, thereby constituting a semiconductor storage. By selectively bringing any of a plurality of the word lines (WL1) for the first port into an active state by a row decoder (16), it is possible to simultaneously access respective memory cells of the 1-port memory cell array (11) and the 2-port memory cell array (12). By selectively bringing any of a plurality of word lines (WL2) for a second port into an active state by a row decoder (18), it is possible to singly access the 2-port memory cell array (12).

Abstract: Methods and apparatus for controlling hierarchical cache memories permit: controlling a first level cache memory including a plurality of cache lines, each cache line being operable to store an address tag and data; controlling a next lower level cache memory including a plurality of cache lines, each cache line being operable to store an address tag, status flags, and data, the status flags of each cache line including an L-flag; and setting the L-flag of a given cache line of the next lower level cache memory to indicate whether or not a corresponding one the of the cache lines of the first level cache memory has been refilled with a copy of the data stored in the given cache line of the next lower level cache memory.

Abstract: A host adapter, which interfaces two I/O buses, caches data transferred from one I/O bus to another I/O bus in a data first-in-first-out (FIFO)/caching memory. In addition, when a target device on the another I/O bus is ready to receive the data, data is transferred from the data FIFO/caching memory even though not all of the data may be cached in that memory. Hence, data is concurrently transferred to and transferred from the data FIFO/caching memory. The data transfer to the target device is throttled if cached data is unavailable in the data FIFO/caching memory for transfer, e.g., the data cache is empty for the current context.

Abstract: A cache memory control apparatus (20) that may control a cache memory (100) has been disclosed. Cache memory control apparatus (20) may include a control section (21). When a cache miss occurs, a refill request for a line (118) of data may be executed. In response to the refill request, control section (21) may perform control to make a valid bit (103) and a TAG portion (102), corresponding to line (118) of data to be refilled, invalid. This may occur while accessing the address corresponding to the cache miss from an external memory (200). In this way, if a reset occurs during the refill operation, a cache memory control apparatus (20) may recover a cache memory to a state before resetting in a reduced time period. Upon completion of the refill operation, valid bit (103) and TAG portion (102) may be updated.

Abstract: A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the processing system to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing.

Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. The system can support the interaction of multiple independent programs in external memory.

Abstract: A processor integrated circuit capable of executing more than one instruction stream has two or more processors. Each processor accesses instructions and data through a cache controller. There are multiple blocks of cache memory. Some blocks of cache memory may optionally be directly attached to particular cache controllers. The cache controllers access at least some of the multiple blocks of cache memory through high speed interconnect, these blocks being dynamically allocable to more than one cache controller. A resource allocation controller determines which cache memory controller has access to the dynamically allocable cache memory block. In an embodiment the cache controllers and cache memory blocks are associated with second level cache, each processor accesses the second level cache controllers upon missing in a first level cache of fixed size.

Abstract: A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.

Abstract: A main memory and a higher-speed local memory are externally connected to a microprocessor. The entire load module is developed in the main memory. A part or all of the instruction codes in the load module developed in the main memory are stored in the local memory. A memory management unit for data converts a logical address of the entire load module into a physical address of the main memory. A memory management unit for instructions converts a logical address of the instruction code stored in the local memory into a physical address of the local memory. A CPU core gains the instruction code from the local memory at the time of execution of the instruction.

Abstract: A semiconductor device is designed to hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM with a plurality of banks. The semiconductor device includes a plurality of memory banks BANK0 to BANK127, each having a plurality of memory cells, as well as a cache memory CACHEMEM used to retain information read from the plurality of memory banks. The cache memory CACHEMEM includes a plurality of entries, each having a data memory DATAMEM and a tag memory TAGMEM. The data memory DATAMEM has a plurality of sub lines DATA0 to DATA3 and the tag memory TAGMEM has a plurality of valid bits V0 to V3 and a plurality of dirty bits D0 to D3.

Abstract: A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

Abstract: The present invention provides an instruction cache apparatus and method using the instruction read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a first cache instruction word memory, a second cache instruction word memory, a first multiplexer and a second multiplexer. The instruction hit analysis unit receives a programmable counter output signal, compares this with a plurality of tags, and after the analysis, outputs the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. The second multiplexer reads the expected instruction word from one of either the first cache instruction word memory, the second cache instruction word memory or the first multiplexer according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory.

Abstract: A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction prefix. The programmer specifies the count of cache lines to be prefetched in the ECX register, similarly to the repeat count of a REP string instruction. The effective address of the first cache line is specified similar to the conventional PREFETCH instruction. The REP PREFETCH instruction stops if the address of the current prefetch cache line misses in the TLB, or if the current processor level changes. Additionally, a line is prefetched only if the number of free response buffers is above a programmable threshold. The prefetches are performed at a lower priority than other activities needing access to the cache or TLB.

Abstract: A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor among the plurality of processors, the first processor transmits an address-only operation on the interconnect to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor among the plurality of processors. In response to receipt of a combined response for the address-only operation representing a collective response of others of the plurality of processors to the address-only operation, the first processor determines whether or not acquisition of the promotion bit field was successful by reference to the combined response.