Abstract: A system which permits dynamic verification of the availability of a desired time at which to load a data requested by a load instruction. The system comprises (i) means for appending a time dependency value to the load instruction, where the time dependency value corresponds to the desired time, (ii) means for verifying that said desired time is available for loading said data, and (iii) means for sending an acknowledgement (ACK) when the desired time is available, where a processor reserves the system resources for accepting the data at the desired time in response to the ACK.

Abstract: A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction processing pipeline). Addresses corresponding to memory locations being modified are compared to the addresses stored in the core snoop buffer on a page basis. If a match is detected, then instructions are flushed from the instruction processing pipeline and refetched. In this manner, the instructions executed to the point of modifying registers or memory are correct in self-modifying code or multiprocessor environments. Instructions may be speculatively fetched and executed while retaining coherency with respect to changes to memory. The number of pages from which instructions are concurrently outstanding within the microprocessor are typically small compared to the number of cache lines outstanding or the number of instructions outstanding.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each running a distinct copy, or instance, of an operating system. Each of the partitions has access to its own physical resources plus resources designated as shared. The partitioning is performed by assigning all resources with a configuration tree. None, some, or all, resources may be designated as shared among multiple partitions. Each individual operating instance will generally be assigned the resources it needs to execute independently and these resources will be designated as “private.” Other resources, particularly memory, can be assigned to more than one instance and shared.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: A structure and a method provide read and write access to a microprocessor's internal cache. During write access, an external data bus transmits to an internal data bus an address, cache tags and data in accordance with a clock provided externally. During read access, the external data bus transmits an address and receives from the internal data bus data and cache tags. In one embodiment, during write access, the external data bus is time-multiplexed to transmit an address, cache tags and data in two clock periods of an externally provided clock signal. During read access, the external data bus is time-multiplexed to transmit to the internal data bus an address in the first clock period of the external clock signal, and to receive tag and data in the next successive clock periods of the externally provided clock signal. In this embodiment, reserved pins are used to specify a cache access mode.

Abstract: A data processor including a central processing unit and a plurality of direct map cache memories (3, 4) has a plurality of area designating circuits (5, 6) for variably designating location and size of address area in the memory space managed the central processing unit and partially overlaps the address area designated by a plurality of area designating circuits. Thereby, the overlapped area (Eco) has a function as the 2-way set associative cache memory in combination with a plurality of cache memories. For the non-overlapping area, respective cache memory functions as the direct map cache memory. It is previously judged to attain the necessary data processing capability by arranging which processing routine to which address area and then executing such routine with what processing speed.

Abstract: A method, apparatus, and manufacture to facilitate power-efficient register file access for preparing a register file to be accessed. Efficient operation of a processor is facilitated while still conserving power. Register information can be decoded during the first phase of a clock to make a determination as to which register within a register file should be accessed. Furthermore, a determination can be made using logic modules as to whether the register information will actually be required by an execution unit during a second phase of the clock. Upon a determination that the register should be enabled, the register is enabled to allow the contents of the register to be output. In this fashion, power can be conserved when it is determined that the information stored by a register file is not required. Such a determination might be made, for example, when it is learned that the information in the register should be bypassed as invalid or an exception occurs cancelling the instruction.

Abstract: A data processing system 2 is provided with a Harvard-type central processing unit 4 coupled to a first level memory 16. The first level memory 16 may be in the form of a cache memory. The first level memory 16 has a data access port and an instruction access port that support parallel data side and instruction side operations. A cache controller 62 may be provided to arbitrate between situations in which concurrent write operations to the same memory location are requested. A separate line fill port may be provided for cache line fills following a cache miss.

Abstract: A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.

Abstract: A cache memory apparatus is provided with a cache memory for storing thereinto at least one of information about an instruction group related to a system control and information about a data group, an address managment table for managing both an address and a range with respect to the cache memory into which the information is stored, and a selection circuit for selecting the cache memory in response to an access to the address management table. As a result, information related to a system control is stored into the cache memory apparatus.

Abstract: An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics—complexity, power, and timing—that are not significantly impacted by the number of stages in the microprocessor's pipeline. In contrast to conventional result distribution schemes where an intermediate result is distributed to multiple pipeline stages, the present invention provides a cache for storage of multiple intermediate results. The cache is accessed by a dependent micro instruction to retrieve required operands. The apparatus includes a result forwarding cache, result update logic, and operand configuration logic. The result forwarding cache stores the intermediate results. The result update logic receives the intermediate results as they are generated and enters the intermediate results into the result forwarding cache.

Abstract: In order to maintain consistency between an instruction cache and a data cache and between the caches and a main memory, there is provided a cache memory system having a processor, a main memory, and a cache memory disposed between the processor and the main memory, which comprises an instruction cache for holding an instruction and a data cache for holding data, which comprises transferring means for transferring data directly from the data cache to the instruction cache; with which it is possible to exclude a time consuming processing such as access to the main memory, execution of a special instruction or the like.

Abstract: A method and system for branch dispatching of instructions in a data processor. A processor having one or more buffers for storing instructions and one or more execution units for executing instructions is utilized. Each unit has a corresponding queue which holds instructions pending execution. First, a threshold level (selected maximum number of instructions in the instruction queue) is set. The current utilization measure for one or more execution units in the data processing system is determined. The current utilization measure is compared to the predetermined threshold value; and a speculative branch instruction is dispatched to a selected execution unit when the current utilization measure is less than the predetermined threshold value.

Abstract: A system for write-combining uncacheable stores includes a memory order buffer, which receives first and second stores, and a data cache address and control, which receives the first and second stores from the memory order buffer. One of the memory order buffer and the data cache address and control determines whether the first and second stores are uncacheable and whether the first and second stores are contiguous in memory. If those conditions are satisfied, the data cache address and control write-combines the first and second stores before committing them to memory. The system may also apply additional conditions to determine whether the stores should be write-combined, for example requiring a minimum size for each store.

Abstract: An apparatus and method are presented for increasing the throughput within a single-channel of a pipeline microprocessor. Back-to-back pairs of micro instructions are evaluated to determine if they can be combined for execution in parallel. If so, then they are combined and issued for concurrent execution. The apparatus includes a micro instruction queue that buffers and orders micro instructions for sequential execution by the pipeline microprocessor. Within the micro instruction queue, a second micro instruction is ordered to execute immediately following execution of a first micro instruction. Pairing logic is coupled to the micro instruction queue. The pairing logic combines the first and second micro instructions so that the first and second micro instructions are executed in parallel by the pipeline microprocessor.

Abstract: An arrangement and a method provide instruction processing. Instructions are delivered to a multi-stage pipeline arrangement from at least one instruction source. A storing arrangement stores jump address information for jump instructions. The storing arrangement includes at least one FIFO-register. The conditional jump target address information is stored in the FIFO-register while at least the jump instructions are stored in the pipeline arrangement. The jump target address information is delivered from the FIFO-register in such a way that substantially sequential and continuous prefetching of the instructions is enabled irrespective of the number of conditional jumps and irrespective of whether the jumps are taken or not.

Abstract: A computer and its corresponding cache system includes a cache memory, a buffer unit, and a bus transaction queue. The buffer unit includes a plurality of entries suitable for temporarily storing data, address, and attribute information of operations generated by the CPU. A first operation initiated by the load store unit buffers an operation in a first entry of the buffer unit, which initiates a first transaction to be queued in a first entry of the bus transaction queue where the first transaction in the bus transaction queue points to the first entry in the buffer unit. Preferably, the buffer unit is configured to modify the first transaction from a first transaction type to a second transaction type prior to execution in response to an event that alters the data requirements of the queued transaction. Additional utility is achieved by merging multiple store operation that miss to a common cache line into a single entry.

Abstract: A CPU has an execution unit for operating on data under instruction control. A cache and a buffer register are coupled in parallel to an input of the execution unit. The buffer register supplies an information item, such as data or an instruction, to the execution unit upon the cache having completed a refill process.

Abstract: A processing system has an instruction processor (IP), register files for storing data to be processed by the IP, such as a thread context, and a register transfer unit (RTU) connected to the register files and to the IP. Register files may assume different states, readable and settable by both the RTU and the IP. The IP and the RTU assume control of register files and perform their functions partially in response to states for the register files, and in releasing register files after processing, set the states. The invention is particularly applicable to multistreamed processors, wherein more register files than streams may be implemented, allowing for at least one idle register file in which to accomplish background loading and unloading of data. The invention is also particularly applicable to processing systems dealing with real-time phenomena, such as data packet processing in network routers.

Abstract: A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level, receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level.

Abstract: A processor employing a dependency link file. Upon detection of a load which hits a store for which store data is not available, the processor allocates an entry within the dependency link file for the load. The entry stores a load identifier identifying the load and a store data identifier identifying a source of the store data. The dependency link file monitors results generated by execution units within the processor to detect the store data being provided. The dependency link file then causes the store data to be forwarded as the load data in response to detecting that the store data is provided. The latency from store data being provided to the load data being forwarded may thereby be minimized. Particularly, the load data may be forwarded without requiring that the load memory operation be scheduled.

Abstract: A microprocessor capable of predecoding variable-length instructions and storing them in a three-dimensional instruction cache is disclosed. The microprocessor may comprise a predecode unit, an instruction cache, and an address translation table. The predecode unit receives variable-length instructions from a main memory subsystem. These instructions are then predecoded by detecting instruction field boundaries within each variable-length instruction. Instructions fields that are not present in a particular instruction may be added by inserting padding constants so that the instruction matches a predetermined format having all instruction fields. The predecoded instruction is stored in the instruction cache, which may be logically and physically structured as a three-dimensional array. Each instruction is stored in the cache so that it has a fixed length in two dimensions. The address translation table maintains address translations for each instruction stored in the instruction cache.

Abstract: A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.

Abstract: An aligned Instruction cache (AIC) containing multiple instruction cache sectors in which may be recorded out-of-sequence blocks of instructions. Basic blocks of instructions are aligned in AIC sectors at program run time. An AIC directory uses the current instruction address to select an AIC directory entry and an associated row in the AIC containing multiple sectors. The AIC directory entry contains multiple “Sector S first address” fields respectively associated with the multiple AIC sectors, each of these directory fields containing the address of the first instruction in the associated AIC sector S when its contents are valid. A “fetch history table” (FHT) contains four FHT entries for each associated AIC row organized in FHT sets of four entries. Each valid FHT entry records a predicted sequence of instructions based on a prior actual execution of the sequence in the same program, which may repeat over and over again.

Abstract: A processor architecture and method are shown which involve a cache having heterogeneous cache sets. An address value of a data access request from a CPU is compared to all cache sets within the cache regardless of the type of data and the type of data access indicated by the CPU to create a unitary interface to the memory hierarchy of the architecture. Data is returned to the CPU from the cache set having the shortest line length of the cache sets containing the data corresponding to the address value of the data request. Modified data replaced in a cache set having a line length that is shorter than other cache sets is checked for matching data resident in the cache sets having longer lines and the matching data is replaced with the modified data. All the cache sets at the cache level of the memory hierarchy are accessed in parallel resulting in data being retrieved from the fastest memory source available, thereby improving memory performance.

Abstract: The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a microprocessor instruction, such as a CISC instruction, or the like. This increases performance by bypassing the fetch/decode pipeline stages on the front end of the microprocessor by using a parcel cache to store previously decoded instructions. The parcel cache is coupled to the microprocessor fetch/decode unit and can be searched during an instruction fetch cycle. This search of the parcel cache will occur in parallel with the search of the microprocessor instruction cache. When parcel(s) corresponding to the complex instruction being fetched are found in the parcel cache a hit occurs and the corresponding micro-ops are then sent to the execution units, bypassing the previous pipeline stages.

Abstract: A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: An integrated processor/memory device comprising a main memory, a CPU, and a full width cache. The main memory comprises main memory banks. Each of the main memory banks stores rows of words. The rows are a predetermined number of words wide. The cache comprises cache banks. Each of the cache banks stores one or more cache lines of words. Each of the cache lines has a corresponding row in the corresponding main memory bank. The cache lines are the predetermined number of words wide. When the CPU issues an address in the address space of the corresponding main memory bank, the cache bank determines from the address and the tags of the cache lines whether a cache bank hit or a cache miss has occurred in the cache bank. When a cache bank miss occurs, the cache bank replaces a victim cache line of the cache lines with a new cache line that comprises the corresponding row of the corresponding memory bank specified by the issued address.

Abstract: A microprocessor includes a cache memory, a bus interface unit, and an execution engine. The bus interface unit is connected to the cache memory and adapted to receive compressed data from a main memory. The execution engine is connected to the bus interface unit and adapted to receive the compressed data from the bus interface unit. The execution engine decompresses the compressed data into uncompressed data and transmits the uncompressed data to the bus interface unit. The bus interface unit is further adapted to transmit the uncompressed data to the cache memory. The microprocessor may be used in a microprocessor system having a main memory capable of storing compressed data, where the bus interface unit transfers compressed data from the main memory to the cache memory in the microprocessor. A method is also provided for increasing memory bandwidth in a microprocessor system including a microprocessor having a cache memory.

Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Abstract: A memory and memory architecture for use by a processor executing real time code and a system on a chip including the processor and memory containing the code. An effective address is maintained in a cache directory. In the preferred embodiment memory, individual functions are loaded into physical memory at permanently selected locations and selected by the effective address in the cache directory. By preselecting task storage locations, system performance may be tuned or optimized to assure predictable performance or task execution.

Abstract: A method and device for increasing memory utilization using a central processing unit with a Harvard architecture, and by putting speech data into the program memory, that is, putting both the program and the data into the same program memory, memory which is normally wasted by internal instruction is now conserved. Furthermore, no changes are required in the hardware of the central processing unit except for some minor changes to the external circuits, so the original central processing unit can be immediately used for the fabrication of prototypes and programs can be developed faster benefiting market expansion.

Abstract: A branch prediction unit stores a set of branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. Each branch selector identifies the branch prediction to be selected if a fetch address corresponding to that branch selector is presented. In order to minimize the number of branch selectors stored for a group of contiguous instruction bytes, the group is divided into multiple byte ranges. The largest byte range may include a number of bytes comprising the shortest branch instruction in the instruction set (exclusive of the return instruction). For example, the shortest branch instruction may be two bytes in one embodiment. Therefore, the largest byte range is two bytes in the example. Since the branch selectors as a group change value (i.e. indicate a different branch instruction) only at the end byte of a predicted-taken branch instruction, fewer branch selectors may be stored than the number of bytes within the group.

Abstract: A cache memory is updated with audio samples in a manner which minimizes system bus bandwidth and cache size requirements. The end of a loop is used to truncate a normal cache request to exactly what is needed. A channel with a loopEnd in a request will be given higher priority in a two-stage priority scheme. The requested data is conformed by trimming to the minimum data block size of the bus, such a doubleword for a PCI bus. The audio data written into the cache can be shifted on a byte-wise basis, and unneeded bytes can be blocked and not written. Request data for which a bus request has been issued can be preempted by request data attaining a higher priority before a bus grant is received.

Abstract: Computer systems may be provided with additional performance for demanding applications while adding little additional hardware. For example, a slave device for a host computer system combines an embedded programmable controller with non-volatile memory, local RAM, and interface logic. The host computer system treats the slave device as if it would be a hierarchical memory system such as a conventional disk drive on which it may store and retrieve files. Additionally, the host computer system may program the controller to perform operations on stored information, including image processing and/or data compression. The non-volatile memory may include a disk drive, writable CD-ROM, optical drive, or non-volatile solid state memory.

Abstract: The processor includes at least a lower and a higher level non-inclusive cache, and a system bus controller. The system bus controller snoops commands on the system bus, and supplies the snooped commands to each level of cache. Additionally, the system bus controller receives the response to the snooped command from each level of cache, and generates a combined response thereto. When generating responses to the snooped command, each lower level cache supplies its responses to the next higher level cache. Higher level caches generate their responses to the snooped command based in part upon the response of the lower level caches. Also, high level caches determine whether or not the cache address, to which the real address of the snooped command maps, matches the cache address of at least one previous high level cache query.

Abstract: A method and a system for fast user mode cache synchronization. The present invention is implemented on a computer system having a instruction cache. The system of the present invention detects a simulated instruction from a process running on the computer system while the process is running in a user mode. The simulated instruction causes an error exception and the operating system traps the error. The kernel then interprets the simulated instruction is then as an instruction cache synchronization instruction. The instruction cache synchronization instruction is executed and the program counter is incremented. The present invention then returns to the process in user mode. During instruction execution, preloaded registers that contain a starting address and an ending address, defining an address range, are read. The entries of the instruction cache are read and those entries falling within the address range are marked as invalid to maintain instruction cache coherency.

Abstract: A multi-processor computer system with clustered processing units uses a cache coherency protocol having a "recent" coherency state to indicate that a particular cache block containing a valid copy of a value (instruction or data) was the most recently accessed block out of a group of cache blocks in different caches (but at the same cache level) that share valid copies of the value. The "recent" state can advantageously be used to implement optimized memory operations such as intervention, by sourcing the value from the cache block in the "recent" state, as opposed to sourcing the value from system memory (RAM), which would be a slower operation. In an exemplary implementation, the hierarchy has two cache levels supporting a given processing unit cluster; the "recent" state can be applied to a plurality of caches at the first level (each associated with a different processing unit cluster), and the "recent" state can further be applied to one of the caches at the second level.

Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.

Abstract: A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the processing units has at least one cache line with a block for storing the instruction or data value, and an indication is provided that a cache line having a block which contains the instruction or data value is in a "recently read" state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). A processing unit which desires to access a shared instruction or data value detects transmission of the indication from the cache having the most recently accessed copy, and the instruction or data value is sourced from this cache.

Abstract: This invention is developed to provide a computing system which can carry out a high speed access to a cache memory within one cycle even though data needed to be read is on the border of two pages. To realize the high speed computing system accessible to a split line on the border of two pages within one cycle, the computing system includes a translation lookaside buffer (TLB) which is designed to have a dual port structure, a prefetcher and a data/code cache memory which is improved for supporting the translated lookaside buffer (TLB).

Abstract: An apparatus and method for accelerating interpreters, interpretive environments, may manage pinning of a processor cache closest to a processor. An instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, the cache is pinned, disabled from flushing the contents or replacing the contents of any cache line. A fast load may flush the cache and run an application containing the entire virtual machine instruction set. A pin manager may be hooked into a scheduler in a multi-tasking operating system to load, pin, and unpin the processor cache as rapidly as needed. Thus, the processor cache may be available for general use, except when pinned for use by a virtual machine, such as an interpretive environment. Level-1 caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention.

Abstract: A computer memory system connectable to a processor and having programmable operational characteristics based on characteristics of the processor. The memory system includes several caches and a main memory connected to a bus. One cache can be programmed to store only code data. Another cache can be programmed to buffer data writes to the main memory only from the processor. The main memory supports fast page mode and can be programmed to selectively reopen either code or non-code data pages.

Abstract: A method and apparatus are provided for controlling communications on a small computer system interface (SCSI). A cache memory is arranged for storing an input queue, a status queue and a cache operation queue. An input engine detects unsolicited data from the SCSI and transfers the detected unsolicited data to the input queue. A status engine transfers status information between the SCSI and the status queue. A cache engine transfers data between the SCSI and the cache operation queue. Each of the input engine, the status engine, and the cache engine is independent to enable full duplex operation. A connection arbitrator is shared between the input engine, the status engine, and the cache engine enabling a connection to be shared by the input engine, the status engine, and the cache engine.

Abstract: A structure for, and a method of operating, an operand cache to store operands retrieved from a memory. An instruction requiring an operand stored in the memory, is allowed to speculatively execute in an execution unit of a processor using an operand stored in an entry (corresponding to the address of the instruction) of the operand cache. When the actual operand is later retrieved from the memory it is compared to the cached operand used for speculative execution. If the cached and actual operands are unequal then the speculatively executed instruction and all subsequent instructions are aborted and the processor resumes execution at the address of the instruction that was speculatively executed.

Abstract: An apparatus and method for accelerating interpreters, interpretive environments, and the like optimizes the use of caches closest to a processor. An instruction set implementing a virtual machine (interpreter, interpretive environment) is written to fit each instruction at an individual cache line's address in the processor cache. The processor cache may be loaded with the instruction set in a compiled, linked, loaded image. After loading the processor cache, the cache is pinned, locked, disabled from flushing the contents or replacing the contents of any cache line. Faster loading of the processor cache may be achieved by flushing the processor cache and running an application containing all of the instructions of the virtual machine instruction set. Level-1 processor caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention. Examples include Intel's Pentium.TM. class products and Motorola's Power PC Processors.

Abstract: A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.

Abstract: A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.