Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

Abstract: Disclosed systems and methods include a CPU coupled to one or more storage resources including a hybrid storage resource that is user-configurable during boot to allocate some, all, or none of its capacity as a conventional dual in-line memory module (DIMM) and some, all, or none of its capacity as a persistent storage resource. A utilization efficiency index (UEI) of the hybrid storage resource is assessed. The UEI may be determined based on a combination of memory resource utilization, a persistent storage resource utilization, and weighting parameters that reflect a comparative utility or value of memory vs storage resources. A target division between memory and storage resources may then be determined based on the UEI assessment. The hybrid storage resource may then be configured by dividing or allocating a first portion of its capacity to the volatile memory resource and a remaining portion of its capacity to the persistent storage resource.

Abstract: A memory controller maintains a mapping of target ranges in system memory space interleaved two-ways across locations in a three-rank environment. For each range of the target ranges, the mapping comprises a two-way interleaving of the range across two ranks of the three-rank environment and offsets from base locations in the two ranks. At least one of the ranges has offsets that differ relative to each other. Such offsets allow the three ranks to be fully interleaved, two ways. An instruction to read data at a rank-agnostic location in the diverse-offset range causes the memory controller to map the rank-agnostic location to two interleaved locations offset different amounts from their respective base locations in their ranks. The controller may then affect the transfer of the data at the two interleaved locations.

Abstract: A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.

Abstract: A memory control device of the present invention controls a memory that includes multiple bank groups each including multiple banks. The memory control device includes a request buffer configured to store memory requests to be issued to the banks, a bank busy manager configured to manage busy states of the banks, a bank group checker configured to, for each of the banks, manage the number of banks in not-busy state of the banks in each of the bank groups, a bank group determination unit configured to determine a bank group to which a memory request is issued, on the basis of the numbers of the banks in not-busy state in the respective bank groups, and a request issuer configured to issue the memory request in the request buffer to a bank in the determined bank group.

Abstract: An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.

Abstract: A storage device and a method of operating the storage device include various memory devices. The storage device includes a plurality of memory devices each including at least one or more read cache memory blocks and a plurality of main memory blocks; and a memory controller configured to spread and store data stored in an identical memory device, having a read count representing a number of read requests and exceeding a threshold value, among data stored in the plurality of main memory blocks, to the at least one or more read cache memory blocks included in each of the plurality of memory devices.

Abstract: There is provided a method for managing addresses in a distributed system. The distributed system comprises a client and a resource pool, the resource pool comprising multiple hosts, a host among the multiple hosts comprising a computing node. The method comprises: receiving an access request from the client, the access request being for accessing first target data in a physical memory of the computing node via a first virtual address; determining the physical memory on the basis of the first virtual address; and determining a first physical address of the first target data in the physical memory on the basis of the first virtual address, wherein the computing node is a graphics processing unit, and the physical memory is a memory of the graphics processing unit.

Abstract: A memory system having memory components and a processing device to receive, from a host system, write commands to store data in the memory components, store the write commands in a buffer, and execute at least a portion of the write commands. For example, this write buffer capacity can be represented by write credit values on the host and the subsystem. The processing device determines an amount of available capacity of the buffer that becomes available after execution of at least the portion of the write commands, and signals the host system to receive information identifying the amount of available capacity, without a pending information request received from the host system.

Abstract: A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

Abstract: A method involves compiling a first amount of high-level programming language code (for example, P4) and a second amount of a low-level programming language code (for example, C) thereby obtaining a first amount of native code and a second amount of native code. The high-level programming language code at least in part defines how an SDN switch performs matching in a first condition. The low-level programming language code at least in part defines how the SDN switch performs matching in a second condition. The low-level code can be a type of plugin or patch for handling special packets. The amounts of native code are loaded into the SDN switch such that a first processor (for example, x86 of the host) executes the first amount of native code and such that a second processor (for example, ME of an NFP on the NIC) executes the second amount of native code.

Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.

Abstract: A method or system for allocating the storage space of a storage medium into a permanently allocated media cache storage region, a dynamically mapped media cache storage region, and statically mapped storage region. In one implementation, the dynamically mapped media cache storage region is used for performance and/or reliability enhancing functions.

Abstract: Techniques are disclosed relating to processing data in a storage controller. In one embodiment, a method includes receiving data at a storage controller of a storage device. The method further includes processing data units of the data in parallel via a plurality of write pipelines in the storage controller. The method further includes writing the data units to a storage medium of the storage device. In some embodiments, the method may include inserting header information into the data for a plurality of data units before processing, and the header information may include sequence information. In some embodiments, writing the data units may include writing according to a sequence determined prior to processing the data units.

Abstract: A tag memory and a cache system with automating tag comparison mechanism and a cache method thereof are provided. The tag memory in the cache system includes a memory cell array, sensing amplifiers and a tag comparison circuit. The memory cell array stores cache tags, and outputs row tags of the cache tags according to an index in a memory address. The sensing amplifiers perform signal amplifications on the row tags to serve as comparison tags. The tag comparison circuit performs parallel comparisons between a target tag in the memory address and the row tags. When one of the row tags matches the target tag, the tag comparison circuit outputs a location of the matched row tag to serve as a first column address. The first column address is a column address where the memory address corresponds to a first data memory in the cache system.

Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.

Abstract: A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays. The interface circuit and the first and second memory cell arrays are provided in one common package, and is configured to access the first memory cell array when detecting the first chip select signal, and to access the second memory cell array when detecting the second chip select signal.

Abstract: A method or system for allocating the storage space of a storage medium into a permanently allocated media cache storage region; a dynamically mapped media cache storage region, and statically mapped storage region, wherein the dynamically mapped media cache storage region is used for performance and/or reliability enhancing functions.

Abstract: A thread processing method that is executed by a multi-core processor, includes supplying a command to execute a first thread to a first processor; judging a dependence relationship between the first thread and a second thread to be executed by a second processor; comparing a first threshold and a frequency of access of any one among shared memory and shared cache memory by the first thread; and changing a phase of a first operation clock of the first processor when the access frequency is greater than the first threshold and upon judging that no dependence relationship exists.

Abstract: Systems and methods for determining a representation of an execution trace include identifying at least one execution trace of a business process model, the business process model including parallel paths where a path influences an outcome of a decision. Path information of the business process model is determined using a processor, the path information including at least one of task execution order for each parallel path, task execution order across parallel paths, and dependency between parallel paths. A path representation for the at least one execution trace is selected based upon the path information to determine a representation of the at least one execution trace.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page.

Abstract: A multi-level cache structure in accordance with one embodiment includes a first cache structure and a second cache structure. The second cache structure is hierarchically above the first cache. The second cache includes a tag array comprising a plurality of tag entries corresponding to respective addresses of data within a system memory; a selector array associated with the tag array; and a data array configured to store a subset of the data. The selector array is configured to specify, for each corresponding tag entry, whether the data array includes the data corresponding to that tag entry.

Abstract: Systems, methods, and other embodiments associated with speculating whether a read request will cause an access to a memory are described. In one embodiment, a method includes detecting, in a memory, a read request from a processor and speculating whether the read request will cause an access to a memory bank in the memory based, at least in part, on an address identified by the read request. The method selectively enables power to the memory bank in the memory based, at least in part, on speculating whether the read request will cause an access to the memory bank.

Abstract: Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache.

Abstract: The present patent application discloses a method and apparatus for using external and internal memory for cancelling traffic interference comprising storing data in an external memory; and processing the data samples on an internal memory, wherein the external memory is low bandwidth memory; and the internal memory is high bandwidth on board cache. The present method and apparatus also comprises caching portions of the data on the internal memory, filling the internal memory by reading the newest data from the external memory and updating the internal memory; and writing the older data back to the external memory from the internal memory, wherein the data is incoming data samples.

Abstract: A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.

Abstract: Provided is a method for uniquely masking addressing to the cache memory for each user, thereby reducing risk of a timing attack by one user on another user. The method comprises assigning a first mask value to the first user and a second mask value to the second user. The mask values are unique to one another. While executing a first instruction on behalf of the first user, the method comprises applying the first mask value to set selection bits in a memory address accessed by the first instruction. While executing a second instruction on behalf of the second user, the method comprises applying the second mask value to set selection bits in the memory address accessed by the second instruction. The result offers an additional level of security between users as well as reducing the occurrence of threads or processes contending for the same memory address.

Abstract: A method and apparatus for de-interleaving interleaved data in a deinterleaver memory in an Orthogonal Frequency Division Multiplexing (OFDM) based Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver. In different embodiments, the apparatus comprises of a OFDM symbol counter along with a divider or a buffer pointer RAM with circular pointer logic, a first lookup table to obtain delay buffer size and interleaving lengths for a given OFDM transmission layer, and a second lookup table to obtain buffer base address and interleaving lengths for a given OFDM transmission layer.

Abstract: Disclosed is a method of pre-fetching NFA instructions to an NFA cell array. The method and system fetch instructions for use in an L1 cache during NFA instruction execution. Successive instructions from a current active state are fetched and loaded in the L1 cache. Disclosed is a system comprising an external memory, a cache line fetcher, and an L1 cache where the L1 cache is accessible and searchable by an NFA cell array and where successive instructions from a current active state in the NFA are fetched from external memory in an atomic cache line manner into a plurality of banks in the L1 cache.

Abstract: Various embodiments of the present invention manage access to a cache memory. In or more embodiments a request for a targeted interleave within a cache memory is received. The request is associated with an operation of a given type. The target is determined to be available. The request is granted in response to the determining that the target is available. A first interleave availability table associated with a first busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request. A second interleave availability table associated with a second busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request.

Abstract: A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter; selecting one of the plurality of requests as a selected request the selected request having been provided by a first state machine; determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache; determining that the location in the cache is unavailable; and replacing the mode with a modified mode that only includes the second step.

Abstract: An apparatus generates test data for a cache memory that caches data in a cache line in accordance with a memory address. The apparatus generates a memory address to be accessed, data to be arranged in a storage area designated by the memory address, an access instruction for the memory address, and an expected value of the data that is to be cached in the cache memory when memory access is performed in accordance with the access instruction. The apparatus generates an address list including the first memory address, the access instruction, and the expected value, so that the address list is stored in a cache block that is cacheable in the cache memory by one memory access. The apparatus generates test data in which the address list and the data are arranged, so that the address list is cached in a different cache line from the data.

Abstract: Memory management process for optimizing the access to a central memory located within a processing system comprising a set of specific units communicating with each other through said memory, said process involving the steps of: a) arranging in a local memory at least a first and a second bank of storage (A, B) for the purpose of temporary object exchanged between a first data object producer (400) and a second data object consumer (410); b) arranging a address translation process for mapping the real address of an object to be stored within said banks into the address of the bank; b) receiving one object produced by said producer and dividing it into stripes of reduced size; c) storing the first stripe into said first bank; d) storing the next stripe into said second bank while the preceding stripe is read by said object consumer (410); e) storing the next stripe into said first bank again while the preceding stripe is read by said object consumer (410).

Abstract: A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).

Abstract: Accelerated interleaved memory data transfers in microprocessor-based systems and related devices, methods, and computer-readable media are disclosed. Embodiments disclosed in the detailed description include accelerated interleaved memory data transfers in processor-based systems. Related devices, methods, and computer-readable media are also disclosed. Embodiments disclosed include accelerated large and small memory data transfers. As a non-limiting example, a large data transfer is a data transfer size greater than the interleaved address block size provided in the interleaved memory. As another non-limiting example, a small data transfer is a data transfer size less than the interleaved address block size provided in the interleaved memory.

Abstract: An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function ?(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0?i?k?1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where ?(i) is also a ith interleaving address generated by the apparatus.

Abstract: An apparatus includes a cache memory that includes a state array configured to store state information. The state information includes a state that indicates updated corresponding to a particular address of the cache memory is not stored in the cache memory but is available from at least one of multiple sources external to the cache memory, where at least one of the multiple sources is a store buffer.

Abstract: A method, system, and computer program product is disclosed for generating an ordered sequence from a predetermined sequence of symbols using protected interleaved caches, such as semaphore protected interleaved caches. The approach commences by dividing the predetermined sequence of symbols into two or more interleaved caches, then mapping each of the two or more interleaved caches to a particular semaphore of a group of semaphores. The group of semaphores is organized into bytes or machine words for storing the group of semaphores into a shared memory, the shared memory accessible by a plurality of session processes. Protected (serialized) access by the session processes is provided by granting access to one of the two or more interleaved caches only after one of the plurality of session processes performs a semaphore altering read-modify-write operation (e.g., a CAS) on the particular semaphore.

Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).

Abstract: Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.

Abstract: We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of a distributed memory, responsive to the predetermined memory access command. The memory interface includes a plurality of memory controllers coupled to the command bus, each memory controller being operable to control a corresponding memory channel responsive to the predetermined memory access command, and a push arbiter coupled to each memory controller. The push arbiter being is operable to merge and align data retrieved responsive to each split read align command.

Abstract: A cache memory associated with a main memory and a processor capable of executing a dataflow processing task, includes a plurality of disjoint storage segments, each associated with a distinct data category. A first segment is dedicated to input data originating from a dataflow consumed by the processing task. A second segment is dedicated to output data originating from a dataflow produced by the processing task. A third segment is dedicated to global constants, corresponding to data available in a single memory location to multiple instances of the processing task.

Abstract: A method and apparatus for de-interleaving interleaved data in a deinterleaver memory in an Orthogonal Frequency Division Multiplexing (OFDM) based Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver. In different embodiments, the apparatus comprises of a OFDM symbol counter along with a divider or a buffer pointer RAM with circular pointer logic, a first lookup table to obtain delay buffer size and interleaving lengths for a given OFDM transmission layer, and a second lookup table to obtain buffer base address and interleaving lengths for a given OFDM transmission layer.

Abstract: A method and system to facilitate full throughput operation of cache memory line split accesses in a device. By facilitating full throughput operation of cache memory line split accesses in the device, the device minimizes the performance and throughput loss associated with the handling of non-aligned cache memory accesses that cross two or more cache memory lines and/or page memory boundaries in one embodiment of the invention. When the device receives a non-aligned cache memory access request, the merge logic combines or merges the incoming data of a particular cache memory line from a data cache memory with the stored data of the preceding cache memory line of the particular cache memory line.

Abstract: A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.

Abstract: A method for protecting an operation sequence executed by a portable data carrier from spying out, wherein the data carrier has at least a processor core, a main memory and a cache memory with a plurality of cache lines. The processor core is able to access, upon executing the operation sequence, at least two data values, with the data values occupying at least one cache line in the cache memory and being respectively divided into several portions so that the occurrence of a cache miss or a cache hit is independent of which data value is accessed. A computer program product and a device have corresponding features. The invention serves to thwart attacks based on an evaluation of the cache accesses during the execution of the operation sequence.

Abstract: An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function ?(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein ?(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0?i?k?1.

Abstract: A computer readable storage medium for associating a phase with an activation of a computer program that supports garbage collection include: a plurality of stacks, each stack including at least one stack frame that includes an activation count; and a processor with logic for performing steps of: zeroing the activation count whenever the program creates a new stack frame and after garbage collection is performed; determining whether an interval has transpired during program execution; examining each stack frame's content and incrementing the activation count for each frame of the stacks once the interval has transpired; detecting the phase whose activation count is non-zero and associating the phase with the activation; and ensuring that when the phase ends, an action is immediately performed.

Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

Abstract: A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, and an instruction sequencing unit that fetches instructions for execution by the execution unit. The processor further includes an operand data structure and an address generation accelerator. The operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and a second relationship between addresses of sequential accesses within a second address region. The address generation accelerator computes a first address of a first memory access in the first address region by reference to the first relationship and a second address of a second memory access in the second address region by reference to the second relationship.