Abstract: A method and apparatus for analyzing the configuration of a computer main memory. A complex memory controller, which imposes restrictions on the memory's configuration, determines whether a user-selected configuration is consistent with those restrictions. The results of the determination are then reported to the user. The results may also be used to program the memory controller.

Abstract: The invention provides for cache organization of texture information and a method and apparatus for accessing cached texture information and an index for cached information. Texels are represented in two dimensions and stored in groups referred to as tiles. Cache is configured to contain multiple tiles of texture image data, each tile being stored as a line in the cache. A cache line can be multidimensional (e.g., two or three or more dimensions) and may be viewed as an identifiable storage element in the cache. Memory may consist of a plurality of cache lines. Direct mapped cache may be utilized wherein each DRAM location maps to a single cache line. A tag table contains the tag information for all tiles currently stored in cache. A portion of the texel information may be utilized as an index assigned to a specific cache line. Another portion of the tag information identifies the tile currently stored in cache.

Abstract: A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to assign memory interleaving schemes based on the number of available bank bits. In another embodiment, the percentage of concurrent memory operations is increased by assigning memory interleaving schemes to bank bits based on the classification of bank bits. The present invention supports a memory organization that provides separate memory busses that support independent simultaneous memory transactions, and memory bus segments that allow memory read operations to be overlapped with memory write operations, with each memory bus segment capable of carrying single memory operation at any given time.

Abstract: Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lead, and thus controls access to memories or memory access requested by the processing units. In the information processing system, a plurality of memory interfaces are included for enabling access to the second memories on an interleaving basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of memory interfaces are included for enabling access to tags on the interleaving basis. Since access to the memories and tags on the interleaving basis is thus enabled, even if the number of processing units increases, competition for the memory access control units subsides and the efficiency of memory access improves.

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract: A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to assign memory interleaving schemes based on the number of available bank bits. In another embodiment, the percentage of concurrent memory operations is increased by assigning memory interleaving schemes to bank bits based on the classification of bank bits. The present invention supports a memory organization that provides separate memory busses that support independent simultaneous memory transactions, and memory bus segments that allow memory read operations to be overlapped with memory write operations, with each memory bus segment capable of carrying single memory operation at any given time.

Abstract: Nine memories (10a˜10i) are provided, out of which five memories are made memories for the present processing. Meanwhile, the remaining four memories are made memories for receiving and storing data to be inputted during the processing. Then, the memories (10a˜10i) which have accepted input data to be inputted at each duration of 1 sound group (SG) are switched to be used for processing, and the memories (10a˜10i) which have been for processing are switched to be used for receiving input data, but a memory (10a˜10i) which has stored the latest data in the memories for processing is left for processing. With this arrangement, memory capacity can be reduced.

Abstract: Two-way set associative data is stored in a cache memory array. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned horizontally within the odd set data bank. An even set data bank stores even number sets of the two-way set associative data, where the two ways of each even number set are aligned horizontally within the even set data bank. Also, the odd set data bank is aligned horizontally with the even set data bank such that each odd number set is aligned horizontally with a next even number set. The horizontally aligned ways are interleaved for data path width reduction. Set and way selection circuits extract lines of data from the array. The array may be structurally implemented by single-ported RAM cells.

Abstract: A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.

Abstract: A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and providing write control to said two-way interleaved L1 cache. The processor has Double Word wide execution dataflow. An instruction decoder receiving instruction data from a unified cache before decoding causes, for stores, I-unit logic to initiate a request ahead of execution to tell the buffer control element that stores will be made from the E-unit, and E-unit logic sends a store request to initiate a store after decoding corresponding instruction data which indicates what address in the cache the DoubleWord data is to be stored to.

Abstract: The present invention discloses a register file in which a read access time is reduced, a data bus width is made expandable, more rapid decoding can be given at a time of data readout, and the whole logic unit is made higher in performance. For these purposes, in the register file of the invention, register arrays are classified into a plurality of banks, and a sense amplifier is provided for each of the banks. Further, the register file includes a decoder to select a word corresponding to a result of decoding of partial bits of a read address so as to read the word from the register array in each of the banks, a decoder to specify a bank corresponding to a result of decoding of remaining bits of the read address, and a multiplexer to select the word from the bank specified by the decoder so as to output the word to the read port.

Abstract: The present invention provides a cache memory system which allows a user to update cache memory in advance without adding special hardware. The cache memory system comprises cache memory composed of a plurality of banks, a cache controller which issues an update instruction as directed by a command, and a DMA controller which transfers data. The cache controller has a command register in which a cache update instruction from a central processing unit is stored. When a cache miss occurs or when the cache controller detects that data was written into the command register, the cache controller issues a DMA transfer instruction to the DMA controller.

Abstract: A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.

Abstract: In a memory system having a plurality of banks which forms interleave groups for independently forming an interleave, when a memory error is detected in an operating system resident space, the group having the error is interchanged with another group that has not had any error yet. After a group interchange, a page having the error is also deallocated. When a determination is made that the group interchange causes deterioration of performance, a bank deallocation can be also executed. As this criterion for determination, it is possible to employ a policy that a bank is deallocated when a capacity of a bank including an erroneous sub-bank is equal to or less than a predetermined rate of all the memory capacity and an interleaving factor is less than the interleaving factor of an interchange partner after the bank deallocation.

Abstract: An electronic memory device which includes a memory array having a plurality of memory cells arranged into a plurality of units. Each unit is divided into a first portion including only even addressed memory cells and a second portion including only odd addressed memory cells. A column decoder and row decoder are coupled to the memory array for selecting a number of the plurality of memory cells. A sense amplifier is coupled to the memory array for performing read and write operations from the selected memory cells. An address line is split for application of a split address to said even and odd addressed memory cells.

Abstract: A process and system for flushing high-speed buffers in a serial link used between a mover circuit (4) that executes data move operations and at least two memories through at least two channels (400, 401), the data move operations each being constituted by a move request followed by the return of a response or acknowledgement of the request, cyclically with interlacing, the responses following the same pair of serial channels (400, 401) as the requests for which they constitute the acknowledgements. The process comprises:a step for placing the mover circuit (4) into a so-called "absorption" mode of operation,a step for generating a specific write request and a specific read request, each of which comprises a so-called "barrier" marker contained in a control character preceding or following the request,a step for accumulating the responses received, anda step for comparing the responses received.

Abstract: A method and apparatus is disclosed to improve the transfer of data from a transition cache to a level one data cache wherein the transition cache is receiving data from a plurality of data devices. In particular, logic is implemented via a line fill sequencer that allows for the interleaving of data packets being written into the level one data cache. Thus, data packets originating from a "fast" level two data cache can be interleaved with data originating from a "slow" system bus to avoid delays to the data originating from the level two data cache. Accordingly, the cache miss sequencer tracking the data from the level two data cache can be retired sooner.

Abstract: In a computer capable of executing a superscalar and a very long instruction word instruction wherein the computer has compiled a number of primitive operations that can be executed in parallel into a single instruction having multiple parcels and each of the parcels correspond to an operation, the invention is an improved instruction cache to store all potential subsequent instructions and a method to select the subsequent instruction when several possible branches of execution are probable and must be evaluated. All branch conditions and all addresses of potential subsequent instructions of an instruction are replicated and stored in the instruction cache. All potential subsequent instructions are stored in the same block of the instruction cache having the same next address; individual instructions are identified by the replicated offset addresses. Further the instruction cache is divided into minicaches, each minicache to store one parcel, which allows rapid autonomous execution of each parcel.

Abstract: An address routing scheme supports a variety of memory sizes and interleaving schemes. In one embodiment, any address bit provided by the processor can be routed to any bank, row, or column bit, and can be used to generate any rank bit. This embodiment supports any type of interleaving scheme and memory modules constructed from a wide variety of DRAM chips. In another embodiment, a reduced routing function is used to generate rank bits and route address bits to subsets of bank, row, or column bits such that no route function encoding requires more than 3 bits. The second embodiment supports multi-cache line interleaving, cache effect interleaving, and DRAM page interleaving. Multi-cache line causes cache lines contained in small contiguous blocks to be contained in one DRAM page, while contiguous small contiguous blocks are stored on separate DRAM pages.

Abstract: A high performance cache unit in a multiprocessing computer system comprises a shared level n cache 15 which is divided into a number of independently operated cache cores each of which containing a cache array for being used as buffer between plurality of processing units PU0-PU1 and a memory 18. Data requests and response requests issued by the processing units are separately executed in an interleaved mode to achieve a high degree of concurrency. For this purpose each cache core comprises arbitration circuits 101, 106 for an independent selection of pending data requests and response requests for execution. Selected data requests are identified by a cache directory lookup as linefetch-match or linefetch-miss operations and separately stored during their execution in operation registers 112, 114. Selected response requests are stored independently of the data requests in registers 105, 108, 109 and successively executed during free operation cycles which are not used by the execution of data requests.

Abstract: A parallel type of memory is divided into P sub-arrays with which there are associated column and row decoding circuits and read circuits. Circuits are used to produce and give P addresses simultaneously to the decoding circuits on the basis of a given address so as to enable the simultaneous reading of P words from a single address. Circuits receive the P information elements extracted from the P words and give them in series at an output port at a frequency greater than the reading frequency. Thus the access time to the information elements seen from the exterior of the memory is reduced.

Abstract: A memory access system is provided for accessing a first data unit and a second data unit in a single memory access cycle. The memory access system provides at least a memory, an even address decoding circuit, an odd address decoder, and shift logic. The memory is interleaved by at least one address bus signal into an even memory bank and an odd memory bank. The even memory bank and the odd memory bank are each organized by a plurality of corresponding rows. Each one of the rows contains at least one storage location for a data unit, with one address mapped to one storage location. The even address decoding circuit decodes an address bus signal supplied to the input terminal and activates an output terminal coupled to enable the given row of the even memory bank. The odd address decoder decodes the address bus signal to activate an output terminal coupled to enable the row of the odd memory bank in which the first data unit resides.

Abstract: A system and method for allocating data among first and second banks of at least one SDRAM, the data including first, second and third words to be accessed during consecutive read operations. The method includes the following steps: storing the first and third words within the first bank, and storing the second word within the second bank. The texture mapping computer graphics system includes a host computer with a main memory that stores texture data including a plurality of texels, and a local memory that stores at least a portion of the texture data. The local memory includes at least one SDRAM.

Abstract: A "bit-sliced" construction of our cache module dictates dual TAG RAM structures and dual invalidation queues, yielding enhanced performance. By putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values, processor operations and invalidation operations can be "overlapped", and even operate simultaneously.

Abstract: A system interconnect architecture and associated arbitration scheme that provides for the interleaving of multiple accesses to a shared system resource by multiple components on a data block by data block basis. According to one embodiment, an access request is granted "immediately" upon receipt such that the effective access latency between an access request and the transfer of a first data block (e.g. a byte. a word, a long word, and a double long word as determined by the width or throughput of the data path) for the access is the minimum access latency to the shared system resource. If a second access request is received while a first access is being performed, the second access request is granted immediately, and the first and second access are thereafter interleaved such that data blocks of the accesses are alternately transferred by the system interconnect.

Abstract: A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilitates the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.

Abstract: A memory board which functions as a main memory of a CPU, is accessible at high speed and is usable in a disk manner is proposed. A flash memory and a D-RAM are mounted on the memory board. The flash memory has a S-RAM interface which synthesizes a row address and a column address transmitted via an address bus, through a latch circuit or a signal processing circuit, to define an address. The CPU, when accessing an address in the flash memory, converts an address signal using an interleave rule in reverse, and transmits the converted address to a system logic. As a result, data can be written into contiguously allotted addresses in the flash memory. The flash memory can thus be used in a disk-like manner.

Abstract: A method and apparatus for analyzing the configuration of a computer main memory. A complex memory controller which imposes restrictions on the memory's configuration, determines whether a configuration is consistent with those restrictions. The results of the determination are then reported to the user, the memory controller assesses a memory configuration's compliance with interleave restrictions, memory row size restrictions, and memory speed restrictions. In addition to reporting restriction non-compliance, the memory controller can also assess and report whether a particular configuration is optimal.

Abstract: A data transfer mechanism for a serial interface is provided whereby data transfer may be precisely controlled, eliminating the need for significant buffering. The data transfer mechanism also provides for flexible data transfer in either a byte mode or a burst mode so as to accommodate any of various telecommunications devices having a range of capabilities and data rates, and minimizes host involvement in the data transfer operation.

Abstract: A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.

Abstract: A high speed pseudo-, 8-, 16-, or greater, ported cache memory, and associated effective address generation scheme. Based upon either two-port building blocks, or twice as many single-port building blocks, which are interleaved, the cache memory is arranged as a functional equivalent to a true 8-, 16-, or greater ported interleaved cache memory.

Abstract: A computer system including a memory controller programmed with associated burst order translation logic and coupled to one or more microprocessors and including a memory circuit which supports either sequential or interleaved transmission of burst data communication between an I/O devices and one or more of the microprocessors. Data transmitted to or from an I/O device, processor or memory is temporarily stored in a buffer within the memory controller. The buffers contain multiple addresses with each address capable of containing a quadword of data. The quadwords of data are transferred to the addresses corresponding to which quadword is the requested quadword from the processor. The quadwords are transmitted, requested quadword first then the next quadword, continuing until all quadwords are transmitted. The corresponding addresses are determined through incrementing or decrementing a pointer to the corresponding addresses, dependent upon the burst ordering translation required.

Abstract: A computer system and method optimized for real-time multimedia applications are presented. The computer system, including a dedicated multimedia engine coupled directly to a real-time data cache, provides increased performance over current computer architectures. The multimedia engine includes at least one DSP engines which couple through at least one I/O channels to I/O ports. Obtaining multimedia commands and data from main memory and/or the real-time data cache, the multimedia engine performs a number of multimedia operations including audio and video functions. A CPU, coupled through a chip set logic or bridge logic to the main memory, generates multimedia commands and data. The CPU groups multimedia commands and data into separate command and data elements, and writes the command and data elements to a multimedia address space in main memory. The CPU also writes element structure information to the multimedia address space.

Abstract: A multiple-way cache memory system incorporating circuitry for selectively enabling the sense amplifiers in a given memory bank only when the memory bank contains data that is being accessed. In the disclosed embodiment of the invention, each bank of memory incorporates a bank of at least one sense amplifier that is enabled by a separate sense amplifier control signal. The sense amplifiers in each memory bank are controlled independent of the address decoding logic. Instead, the sense amplifier control signal for each memory bank is generated from tag RAM read hit information and read address data. Preferably, no more than one bank of sense amplifiers is enabled at a time, Power consumption in the cache memory system is thereby greatly reduced.

Abstract: A method and apparatus deinterleave data blocks each transmitted as a sequence of data groups including N bits of data from a single bit position of N words. A first data block is received (1004) and stored (1006) in a memory (402) in a manner that defines memory locations for each of the N words, thereby deinterleaving the first data block. A next data block is received by processing (1008) at least a portion of the N words stored previously in the memory, thereby providing free memory locations, and thereafter receiving (1012) new data including at least a portion of a next data group of the next data block. The new data is stored (1014) in at least a portion of the free memory locations, and processing continues until the next data block has been received and stored in entirety. The memory locations are then redefined (1018) for the N words, thereby deinterleaving the next data block.

Abstract: In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example, for example, more than the memory banks are grouped into a plurality of logical groups each spanning the real bank groups. Addresses are allocated in unit of each logical group in a block-interleaving manner. When a series of requests issued by a given requester include a plurality of requests for accessing the same row address in the same memory bank, that requester requests that the row address be locked for access by the plurality of requests. The lock request is retained by a row address management unit. When a succeeding request from another requester requests access to a row address other than the locked address in the same memory bank, a priority circuit selects a predetermined number of requests from the initial requester having locked the memory in preference to a request made by the other requester.

Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for application to each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.

Abstract: In a memory control apparatus which has a main memory constructed by a plurality of memory areas and a cache memory which can be accessed at a speed higher than that of the main memory and in which the main memory or the cache memory is accessed in response to a memory access request from an access request side and data is read out and transferred to the access request side, an accessing speed of every plurality of memory areas in the main memory is identified and an area that is cachable for the cache memory among the plurality of memory areas in the main memory is set in accordance with the identified accessing speed of every plurality of memory areas in the main memory.

Abstract: An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

Abstract: A method and apparatus for interfacing a memory card with a system having a smaller bus width while maintaining its interchangeability with other systems having larger bus widths. The host accesses data stored in the memory card using an interleaving scheme, such as a two-way interleaving scheme. The host provides a first enable signal and a second enable signal. In response to the first enable signal, data is accessed from a first section of the addressed memory location, and in response to the second enable signal, data is accessed from a second section of the addressed memory location. The first section of the addressed memory location may store even data bytes and the second section of the addressed memory location may store odd data bytes. The host may only access one section of the selected memory location at a time when using the interleaving scheme.

Abstract: An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.

Abstract: An address aggregation system enhances the performance of a processor that executes instructions out of order by enhancing the throughput of data addressing from the processor to a remote data cache (DCACHE). In essence, the processor is configured to concurrently address separate independent DCACHE banks, each preferably an inexpensive single ported random access memory (RAM), during each processor cycle. In the preferred implementation, the DCACHE has odd and even banks that are addressed by respective odd and even data addresses during each processor cycle. The processor comprises an instruction cache (ICACHE), an instruction fetch mechanism (IFETCH) for retrieving instructions from the ICACHE, a sort mechanism (SORT) for receiving instructions from the IFETCH and for sorting the instructions into arithmetic instructions and memory instructions, and a memory queue (MQUEUE) for receiving the memory instructions from the sort and permitting the instructions to execute out of order.

Abstract: A cache memory for a computer uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. The cache memory is partitioned in four subarrays, i.e., interleaved, providing a wide cache line (word lines) but shallow depth (bit lines). The cache can be accessed by multiple addresses, producing multiple data outputs in a given cycle. Two effective addresses and one real address are applied at one time, and if addresses are matched in different subarrays, or two on the same line in a single subarray, then multiple access is permitted. The two content-addressable memories, or CAMs, are used to select a cache line, and in parallel with this, arbitration logic in each subarray selects a word line (cache line).

Abstract: Graphic data having a two-dimensional spread is divided into data blocks having a two-dimensional spread, for example, data blocks of 8.times.8 pixels, and with these data blocks as units, cache control is performed. A tag memory for making a decision as to the occurrence of a cache hit, stores therein a tag and a valid flag as well as a bank address in a cache memory at which the data block in question is stored. As a result, the relationship between each bank of the cache memory and the address in the tag memory is not fixed, which ensures efficient use of the cache memory even in situations where accesses concentrate in one particular memory area.