Abstract: A method for maintaining statistics for data elements in a cache is disclosed. The method maintains a heterogeneous cache comprising a higher performance portion and a lower performance portion. The method maintains, within the lower performance portion, a ghost cache containing statistics for data elements that are currently contained in the heterogeneous cache, and data elements that have been demoted from the heterogeneous cache within a specified time interval. The method maintains updates to the statistics in an update area within the higher performance portion. The method determines whether the updates have reached a specified threshold and, in the event the updates have reached the specified threshold, flushes the updates from the update area to the ghost cache to update the statistics. A corresponding system and computer program product are also disclosed.

Abstract: Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

Abstract: A memory controller for processing a flush request includes: a request message controller configured to generate a command or control signal in response to a request of a host, a delay time determiner configured to, when the request is a current flush request, generate delay information based on a number of write requests between a last received flush request before the current flush request and the received flush request and a response message controller configured to generate a flush response corresponding to the received flush request message based on the delay information.

Abstract: An electronic device and a control method for controlling a memory are provided.

Abstract: Techniques manage metadata. Such techniques involve: in response to receiving a request for accessing metadata in a first page, determining, from a plurality of storage units including pages for storing metadata, a storage unit where the first page is located, the plurality of storage units including a first storage unit and a second storage unit, an access speed of the second storage unit exceeding an access speed of the first storage unit; accessing, from the determined storage unit, the first page for metadata; in response to the first page being accessed from the first storage unit, determining whether hotness of the first page exceeds a threshold level; and in response to the hotness of the first page exceeding the threshold level, transferring the first page from the first storage unit to the second storage unit. Accordingly, such techniques can improve the efficiency for accessing the metadata.

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

Abstract: Techniques are disclosed relating to controlling cache size and priority of data stored in the cache using machine learning techniques. A software cache may store data for a plurality of different user accounts using one or more hardware storage elements. In some embodiments, a machine learning module generates, based on access patterns to the software cache, a control value that specifies a size of the cache and generates time-to-live values for entries in the cache. In some embodiments, the system evicts data based on the time-to-live values. The disclosed techniques may reduce cache access times and/or improve cache hit rate.

Abstract: A technique for caching evidence for answering questions in a cache memory of a data processing system (that is configured to answer questions) includes receiving a first question. The first question is analyzed to identify a first set of characteristics of the first question. A first set of evidence for answering the first question is loaded into the cache memory. A second question is received. The second question is analyzed to identify a second set of characteristics of the second question. A portion of the first set of evidence, whose expected usage in answering the second question is below a determined threshold, is unloaded from the cache memory.

Abstract: Systems and techniques for information-centric network data cache management are described herein. A demand metric may be calculated for a content item requested from an information-centric network (ICN). A resistance metric may be calculated for each cache node of a set of cache nodes in the ICN based on the demand metric. A topology of the set of cache nodes may be evaluated to identify a transmission cost for each cache node of the set of cache nodes. An influencer node may be selected from the set of cache nodes based on the resistance metric for the influencer node and the transmission cost for the influencer node. The content item may be cached in a data cache of the influencer node.

Abstract: Managing applications in light of user use habits is disclosed. An indication that an application has been switched from a foreground environment to a background environment is detected. User historical use information associated with the application is accessed. Based at least in part on the user historical use information, it is determined that the application is not likely to be switched to the foreground environment. In response to the determination that the application is not likely to be switched to the foreground environment, one or more resources associated with the application are recycled.

Abstract: A technique for caching evidence for answering questions in a cache memory of a data processing system (that is configured to answer questions) includes receiving a first question. The first question is analyzed to identify a first set of characteristics of the first question. A first set of evidence for answering the first question is loaded into the cache memory. A second question is received. The second question is analyzed to identify a second set of characteristics of the second question. A portion of the first set of evidence, whose expected usage in answering the second question is below a determined threshold, is unloaded from the cache memory.

Abstract: Techniques are provided for managing a least recently used cache using a linked list with a reduced memory footprint. A cache manager receives an I/O request comprising a target address, wherein the cache manager manages a cache memory having a maximum allocated amount of cache entries, and a linked list having a maximum allocated amount of list elements which is less than the maximum allocated amount of cache entries. If the target address does correspond to a cache entry, the cache manager accesses the cache entry to obtain the cache data from cache memory, removes a list element from the linked list, which corresponds to the accessed cache entry, selects an existing cache entry which currently does not have a corresponding list element in the linked list, and adds a list element to a head position of the linked list which corresponds to the selected cache entry.

Abstract: A method for improving cache hit ratios for selected volumes when using synchronous I/O is disclosed. In one embodiment, such a method includes establishing, in cache, a first set of non-favored storage elements from non-favored storage areas. The method further establishes, in the cache, a second set of favored storage elements from favored storage areas. The method calculates a life expectancy for the non-favored storage elements to reside in the cache prior to eviction. The method further executes an eviction policy for the cache wherein the favored storage elements are maintained in the cache for longer than the life expectancy of the non-favored storage elements. A corresponding system and computer program product are also disclosed.

Abstract: Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute instructions; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In a representative embodiment, the processor core is further adapted to execute a non-cached load instruction to designate a general purpose register rather than a data cache for storage of data received from a memory circuit. The core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, and to generate one or more work descriptor data packets to another circuit for execution of corresponding execution threads.

Abstract: A method for improving cache hit ratios dedicates, within a cache, a portion of the cache to prefetched data elements. The method maintains a high priority LRU list designating an order in which high priority prefetched data elements are demoted, and a low priority LRU list designating an order in which low priority prefetched data elements are demoted. The method calculates, for the high priority LRU list, a first score based on a first priority and a first cache hit metric. The method calculates, for the low priority LRU list, a second score based on a second priority and a second cache hit metric. The method demotes, from the cache, a prefetched data element from the high priority LRU list or the low priority LRU list depending on which of the first score and the second score is lower. A corresponding system and computer program product are also disclosed.

Abstract: A processor includes processor memory arrays including one or more volatile memory arrays and one or more Non-Volatile Memory (NVM) arrays. Volatile memory locations in the one or more volatile memory arrays are paired with respective NVM locations in the one or more NVM arrays to form processor memory pairs. Process data is stored for different processes executed by at least one core of the processor in respective processor memory pairs. Processes are executed using the at least one core to directly access the process data stored in the respective processor memory pairs.

Abstract: A method by a computing device of a dispersed storage network (DSN) begins by determining whether alternate form data (AFD) exists for a data object. When the alternate form data does not exist, the method continues by identifying a content derivation function in accordance with an AFD policy of the DSN. The method continues by identifying a portion of the data object based on the content derivation function and identifying one or more sets of encoded data slices of a plurality of sets of encoded data slices corresponding to the portion of the data object. The method continues by generating at least a portion of the AFD based on the one or more sets of encoded data slices. The method continues by storing the at least a portion of the AFD within memory of the DSN in accordance with a storage approach.

Abstract: A method for improving cache hit ratios for selected storage elements within a storage system is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a first LRU list containing entries associated with non-favored storage elements and designating an order in which the non-favored storage elements are evicted from the cache, and a second LRU list containing entries associated with favored storage elements and designating an order in which the favored storage elements are evicted from the cache. The method moves entries between the first LRU list and the second LRU list as favored storage elements are changed to non-favored storage elements and vice versa. A corresponding system and computer program product are also disclosed.

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry (4) triggers at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines for which a physical address of the data stored by the cache line is within a physical page that corresponds to the virtual page identified by the virtual page address provided by the cache maintenance instruction.

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an IO request on a first node. It may be determined whether a virtual address for the IO request is in a virtual cache. A read to RAID may be issued using the virtual address when the virtual address for the IO request is not in the virtual cache. A return of a cached page associated with the virtual address may be issued when the virtual address for the IO request is in the virtual cache.

Abstract: A method for efficiently method for performing adaptive management of a cache with predetermined size and number of cells with different locations with respect to the top or bottom of the cache, for storing at different cells, data items to be retrieved upon request from a processor. A stream of requests for items, each of which has a temporal probability to be requested is received and the jump size is incremented on cache misses and decremented on cache hits by automatically choosing a smaller jump size and using a larger jump size when the probability of items to be requested is changed. The jump size represents the number of cells by which a current request is promoted in the cache, on its way from the bottom, in case of a cache hit, or from the outside in case of a cache miss, towards the top cell of the cache.

Abstract: A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.

Abstract: This disclosure provides a cache replacing method applied to a heterogeneous multi-core system, the method including: determining whether a first application currently running is an application running on the GPU; when it is determined that the first application currently running is an application running on the GPU, determining a cache priority of first data accessed by the first application according to a performance parameter of the first application, the cache priority of the first data including a priority other than a predefined highest cache priority; and caching the first data into a cache queue of the shared cache according to a predetermined cache replacement algorithm and the cache priority of the first data, and replacing data in the cache queue.

Abstract: A method for improving the execution time of a computer application comprises at least one cycle includes: a step of determining the type of memory access time sequence occurring during execution of the computer application; a step of preloading data, from a file system to a cache memory system, according to the determined type of memory access time sequence. The determination step is carried out by a learning model having been previously configured using a database of certain predetermined types of memory access time sequences.

Abstract: A system includes a request processing module configured to receive a chart description request associated with an asset. The system also includes a rules store configured to store rules, a rules application module configured to determine a set of rules and a set of results by applying each rule in the set of rules to chart data associated with the asset, a rules selector module configured to select a subset of results from the set of results, a text generation module configured to generate a text description based on the subset of results, and an output module configured to transmit the text description. Each of the rules includes a relevancy score. The selection of the subset of results is based on the score of each rule associated with the set of results. The description describes a chart associated with the asset.

Abstract: According to one embodiment, a memory system receives from a host read commands each designating both of a block address of a read target block and a read target storage location in the read target block, and executes a data read operation in accordance with each of the received read commands. In response to receiving from the host a first command to transition a first block to which data is already written to a reusable state of being reusable as a new write destination block, the memory system determine whether an incomplete read command designating a block address of the first block exists or not. In a case where the incomplete read command exists, the memory system executes the first command after execution of the incomplete read command is completed.

Abstract: A data storage device includes a nonvolatile memory device and a memory having an unmap command queue configured to store an unmap command received from a host, and a sequential unmap table configured to store a sequential unmap entry corresponding to an unmap command for sequential logical addresses, and a controller including a first core and a second core. The second core configured to read an unmap-target map segment including the sequential logical addresses from an address mapping table stored in the nonvolatile memory device, store the read unmap-target map segment in the memory, and change, within the stored unmap-target map segment, physical addresses mapped to the sequential logical addresses to trim instruction data at the same time, the trim instruction data being included in the sequential map entry.

Abstract: Aspects store configuration version data for an application into a shared cache in a structured data format; in response to a request at run-time for the configuration version data, determine whether run-time format data of the configuration version data is stored in a different, local cache; and in response to determining that the run-time format configuration version data is not stored in the local cache, during execution of the application, read the structured data format data from the shared cache, translate the read data into the run-time data format, store the translated data into the local cache in the run-time format file and return the configuration version run-time format data stored within the local cache in satisfaction of the request at run-time for the configuration version data of the application.

Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to move processed tracks. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end, wherein each insertion point of the insertion points identifies a track in the cache list. An insertion point of the insertion points is determined at which to move the processed track in response to determining that a processed track is indicated to move to the MRU end. The processed track is indicated at a position in the cache list with respect to the determined insertion point.

Abstract: A computer readable storage device includes a first memory section that stores operational instructions that, when executed, cause a computing device to, as data accesses occur for a plurality of data objects of a storage container, update object values to produce updated object values, update object retention costs to produce updated object retention costs, adjust a dynamic retention threshold based on the updated object values and the updated object retention costs and update a data object retention policy for a data object based on the dynamic retention threshold to produce an updated retention policy for the data object. The computer readable storage device includes a second memory section that stores operational instructions that, when executed, cause the computing device to, when a data access is a deletion request, utilizing a current updated data object retention policy to determine and execute a deletion-retention option for the data object.

Abstract: Exemplary methods and apparatus are disclosed to select data evacuation policies for use by a solid state device (SSD) to relocate data from an upper (high performance) memory tier to a lower memory tier. The upper tier may be, e.g., a single-layer cell (SLC) tier of a multi-tier NAND memory, whereas the lower tier may be, e.g., a triple-layer cell (TLC) or a quad-level cell (QLC) tier of the NAND memory. In one example, the SSD monitors its recent input/output (I/O) command history. If a most recent command was a read command, the SSD performs a “lazy” evacuation procedure to evacuate data from the upper tier storage area to the lower tier storage area. Otherwise, the SSD performs a “greedy” or “eager” evacuation procedure to evacuate the data from the upper tier to the lower tier. Other evacuation selection criteria are described herein based, e.g., upon predicting upcoming I/O commands.

Abstract: Systems, methods, and computer-readable media for lazy tracking mechanisms for web caching systems are provided. The lazy tracking mechanism may track and perform asynchronous (async) computation of dirty records for client-side caching mechanisms. The async computation of dirty records may include tracking or accounting for invalidated records relevant to a particular client or user system. Invalidation messages may be sent to client/user systems in response to receipt of a request for updated records, or in response to a request for a particular item. Other embodiments may be described and/or claimed.

Abstract: Cache management techniques are described for a content distribution network (CDN), for example, a video on demand (VOD) system supporting user requests and delivery of video content. A preferred cache size may be calculated for one or more cache devices in the CDN, for example, based on a maximum cache memory size, a bandwidth availability associated with the CDN, and a title dispersion calculation determined by the user requests within the CDN. After establishing the cache with a set of assets (e.g., video content), an asset replacement algorithm may be executed at one or more cache devices in the CDN. When a determination is made that a new asset should be added to a full cache, a multi-factor comparative analysis may be performed on the assets currently residing in the cache, comparing the popularity and size of assets and combinations of assets, along with other factors to determine which assets should be replaced in the cache device.

Abstract: Capacity enhancement of a direct communication link using a variable redundancy delivery network. An estimated information rate between a source node and a terminal node may be partitioned into a first information rate provided via the direct communication link and a second information rate to be provided via the variable redundancy delivery network. One or more parameters of the variable redundancy delivery network may be calculated to provide the second information rate based on a non-uniform probability density of messages requested by the terminal node. Capacity and reliability of storage media devices in the variable redundancy delivery network may be traded off to provide the second information rate. The variable redundancy delivery network may implement various coding schemes and per-message coding rates that may be determined based on the non-uniform probability distribution of the source message library.

Abstract: The present disclosure provides a cache system and an operating method thereof. The system includes an upper-level cache unit and a last level cache (LLC). The LLC includes a directory, a plurality of counters, and a register. The directory includes a status indicator recording a utilization status of the upper-level cache unit to the LLC. The counters are used to increase or decrease a counting value according to a variation of the status indicator, record an access number from the upper-level cache unit, and record a hit number of the upper-level cache unit accessing the LLC. According to the counting value, the access number, and the hit number, the first parameters of the register are controlled, so as to adjust a utilization strategy to the LLC.

Abstract: In one embodiment, performance-based multi-mode task dispatching for high temperature avoidance in accordance with the present description, includes selecting processor cores as available to receive a dispatched task. Tasks are dispatched to a set of available processor cores for processing in a performance-based dispatching mode. If monitored temperature rises above a threshold temperature value, task dispatching logic switches to a thermal-based dispatching mode. If a monitored temperature falls below another threshold temperature value, dispatching logic switches back to the performance-based dispatching mode. If a monitored temperature of an individual processor core rises above a threshold temperature value, the processor core is redesignated as unavailable to receive a dispatched task. If the temperature of an individual processor core falls below another threshold temperature value, the processor core is redesignated as available to receive a dispatched task.

Abstract: An interface is provided for controlling transfer of electronic transaction messages between a financial institution and switches distributed amongst a plurality of switch sites. The financial institution and the switches are connected via a data communications network. Communication circuitry is operable to transmit a test message to one of the switch sites over the data network if no transaction message is received from that switch site for a predetermined time. And, in response to the test message, the communication circuitry is operable to receive an echo of the test message from the switch site. If the echo is received within a defined time, processing circuitry is operable to then set the operational status of the switch site as operational, and if the echo is not received within the defined time, the operational status of the switch site is set as not operational.

Abstract: Internet protocol packets are statelessly identified as associated with a particular session-instance by identifying a key, or session-instance identifier, within the data (or payload) portion of a user plane packet. This identifier is specific to the session-instance and remains constant throughout the session-instance. Using this stateless identification, transmitted user plane packets are automatically routed at the transmission speed of the transmission link using a method that automatically balances the analysis processing load between network probes. The load is balanced by routing the user plane packet to a network probe that is either already analyzing the session-instance or by routing the user plane packet to a system that has processing capacity to analyze a new session-instance. The network probe then analyzes the user plane packet and the session-instance to measure the quality of the user experience of the session-instance and performance of the network.

Abstract: A method, storage system and non-transitory computer readable medium. The method may include receiving or generating, and for each storage entity out of multiple storage entities of the storage system, a storage entity distribution of cache hits over a caching period related to cached data associated with the storage entity and determining an allocation of quotas of the cache space to the multiple storage entities. The determining may include: (a) for each storage entity, determining a hit score indicative of a number of cache hits per a caching sub-period of the caching period related to the storage entity; (b) simulating, in an iterative manner, an allocation of quotas of the cache space to the storage entities that substantially maximizes the number of cache hits; and (c) allocating quotas of the cache space to the storage entities of the multiple storage entities, based on an outcome of the simulation.

Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for consensus system downtime recovery. One of the methods includes: multicasting a pre-prepare message to at least some of the backup nodes; obtaining (Q?1) or more prepare messages respectively from (Q?1) or more of the backup nodes, wherein the prepare messages each indicate an acceptance of the pre-prepare message by the corresponding backup node; storing the pre-prepare message and the (Q?1) or more prepare messages; multicasting a commit message to at least some of the backup nodes, the commit message indicating that the primary node agrees to the (Q?1) or more prepare messages; and obtaining, respectively from Q or more nodes among the primary node and the backup nodes, Q or more commit messages each indicating that the corresponding node agrees to (Q?1) or more prepare messages received by the corresponding node.

Abstract: Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.

Abstract: Systems, methods, and storage media for managing traffic on a digital content delivery network are disclosed. Exemplary implementations may: receive an item of digital content on a digital content delivery network; assign a type category to the item of digital content; determine an update time variable of the item of digital content; determine a cache time for the item of digital content based on the type category of the item of digital content and the update time variable of the item of digital content and; and cache an instance of the item of digital content in a cache memory associated with the content delivery network for the cache time and removing the instance from the cache memory after the cache time has lapsed.

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transform matrices into a row-interleaved format. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of source and destination matrices, wherein the opcode indicates that the processor is to transform the specified source matrix into the specified destination matrix having the row-interleaved format; and execution circuitry to respond to the decoded instruction by transforming the specified source matrix into the specified RowInt-formatted destination matrix by interleaving J elements of each J-element sub-column of the specified source matrix in either row-major or column-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements.

Abstract: A system and method for efficiently handling data selected for eviction in a computing system. In various embodiments, a computing system includes one or more processors, a system memory, and a victim cache. The cache controller of a particular cache in a cache memory subsystem includes an allocator for determining whether to allocate data evicted from the particular cache into the victim cache. The data fetched into the first cache includes data fetched to service miss requests, which includes demand requests and prefetch requests. To determine whether to allocate, the allocator determines whether a usefulness of data fetched into the particular cache exceeds a threshold. If so, the evicted data is stored in the victim cache. If not, the evicted data bypasses the victim cache. Data determined to be accessed by a processor is deemed to be of a higher usefulness.

Abstract: A computing system includes: a host configured to provide data and address information on the data; and a memory system configured to store the data, wherein the memory system comprises: a plurality of memory devices configured to be grouped into at least one memory device group; and a controller configured to control each of the plurality of memory devices, wherein the controller comprises: a group setter configured to set the memory device groups with respect to a type of the data by a request of the host; and a processor configured to read the data from, or write the data to, the memory device group corresponding to the type of the data.

Abstract: A data processing system includes a plurality of processor cores each having a respective associated cache memory, a memory controller, and a system memory coupled to the memory controller. A zero request of a processor core among the plurality of processor cores is transmitted on an interconnect fabric of the data processing system. The zero request specifies a target address of a target memory block to be zeroed and has no associated data payload. The memory controller receives the zero request on the interconnect fabric and services the zero request by zeroing in the system memory the target memory block identified by the target address, such that the target memory block is zeroed without caching the zeroed target memory block in the cache memory of the processor core.